X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_pipe.h;h=e5acd415423ea9b00e8095860b5b907c105fac32;hb=9fd68be13333140767822c5f5149956333b726e0;hp=d04fef80df1f3ddc773737937631e0e7d066d1b5;hpb=79f28cdb983b7faf9d3008fae541a30e34ccce5a;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index d04fef80df1..e5acd415423 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -26,45 +26,78 @@ #ifndef R600_PIPE_H #define R600_PIPE_H -#include "../radeon/r600_pipe_common.h" -#include "../radeon/r600_cs.h" - -#include "r600_llvm.h" +#include "radeon/r600_pipe_common.h" +#include "radeon/r600_cs.h" #include "r600_public.h" +#include "pipe/p_defines.h" -#include "util/u_blitter.h" #include "util/u_suballoc.h" -#include "util/u_double_list.h" +#include "util/list.h" #include "util/u_transfer.h" - -#define R600_NUM_ATOMS 73 +#include "util/u_memory.h" + +#include "tgsi/tgsi_scan.h" + +#define R600_NUM_ATOMS 52 + +/* read caches */ +#define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0) +#define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1) +#define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2) +/* read-write caches */ +#define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3) +#define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4) +#define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5) +#define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6) +#define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7) +/* engine synchronization */ +#define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8) +#define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9) +#define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10) /* the number of CS dwords for flushing and drawing */ -#define R600_MAX_FLUSH_CS_DWORDS 16 -#define R600_MAX_DRAW_CS_DWORDS 37 -#define R600_TRACE_CS_DWORDS 7 +#define R600_MAX_FLUSH_CS_DWORDS 18 +#define R600_MAX_DRAW_CS_DWORDS 58 +#define R600_MAX_PFP_SYNC_ME_DWORDS 16 #define R600_MAX_USER_CONST_BUFFERS 13 -#define R600_MAX_DRIVER_CONST_BUFFERS 4 +#define R600_MAX_DRIVER_CONST_BUFFERS 3 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS) /* start driver buffers after user buffers */ -#define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS) -#define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1) -#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2) -#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 3) +#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS) +#define R600_UCP_SIZE (4*4*8) +#define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE) +#define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1) +/* + * Note GS doesn't use a constant buffer binding, just a resource index, + * so it's fine to have it exist at index 16. + */ +#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2) +/* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit + * of 16 const buffers. + * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id. + * + * In order to support d3d 11 mandated minimum of 15 user const buffers + * we'd have to squash all use cases into one driver buffer. + */ #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4])) -#ifdef PIPE_ARCH_BIG_ENDIAN -#define R600_BIG_ENDIAN 1 -#else -#define R600_BIG_ENDIAN 0 -#endif +/* HW stages */ +#define R600_HW_STAGE_PS 0 +#define R600_HW_STAGE_VS 1 +#define R600_HW_STAGE_GS 2 +#define R600_HW_STAGE_ES 3 +#define EG_HW_STAGE_LS 4 +#define EG_HW_STAGE_HS 5 + +#define R600_NUM_HW_STAGES 4 +#define EG_NUM_HW_STAGES 6 struct r600_context; struct r600_bytecode; -struct r600_shader_key; +union r600_shader_key; /* This is an atom containing GPU commands that never change. * This is supposed to be copied directly into the CS. */ @@ -82,14 +115,16 @@ struct r600_db_state { struct r600_db_misc_state { struct r600_atom atom; - bool occlusion_query_enabled; + bool occlusion_queries_disabled; bool flush_depthstencil_through_cb; - bool flush_depthstencil_in_place; + bool flush_depth_inplace; + bool flush_stencil_inplace; bool copy_depth, copy_stencil; unsigned copy_sample; unsigned log_samples; unsigned db_shader_control; bool htile_clear; + uint8_t ps_conservative_z; }; struct r600_cb_misc_state { @@ -109,6 +144,7 @@ struct r600_clip_misc_state { unsigned clip_plane_enable; /* from rasterizer */ unsigned clip_dist_write; /* from vertex shader */ boolean clip_disable; /* from vertex shader */ + boolean vs_out_viewport; /* from vertex shader */ }; struct r600_alphatest_state { @@ -124,6 +160,7 @@ struct r600_vgt_state { uint32_t vgt_multi_prim_ib_reset_en; uint32_t vgt_multi_prim_ib_reset_indx; uint32_t vgt_indx_offset; + bool last_draw_was_indirect; }; struct r600_blend_color { @@ -139,6 +176,7 @@ struct r600_clip_state { struct r600_cs_shader_state { struct r600_atom atom; unsigned kernel_index; + unsigned pc; struct r600_pipe_compute *shader; }; @@ -150,6 +188,8 @@ struct r600_framebuffer { bool export_16bpc; bool cb0_is_integer; bool is_msaa_resolve; + bool dual_src_blend; + bool do_update_surf_dirtiness; }; struct r600_sample_mask { @@ -161,6 +201,8 @@ struct r600_config_state { struct r600_atom atom; unsigned sq_gpr_resource_mgmt_1; unsigned sq_gpr_resource_mgmt_2; + unsigned sq_gpr_resource_mgmt_3; + bool dyn_gpr_enabled; }; struct r600_stencil_ref @@ -176,12 +218,6 @@ struct r600_stencil_ref_state { struct pipe_stencil_ref pipe_state; }; -struct r600_viewport_state { - struct r600_atom atom; - struct pipe_viewport_state state; - int idx; -}; - struct r600_shader_stages_state { struct r600_atom atom; unsigned geom_enable; @@ -196,8 +232,7 @@ struct r600_gs_rings_state { /* This must start from 16. */ /* features */ -#define DBG_LLVM (1 << 17) -#define DBG_NO_CP_DMA (1 << 18) +#define DBG_NO_CP_DMA (1 << 30) /* shader backend */ #define DBG_NO_SB (1 << 21) #define DBG_SB_CS (1 << 22) @@ -226,6 +261,7 @@ struct r600_pipe_sampler_view { struct r600_resource *tex_resource; uint32_t tex_resource_words[8]; bool skip_mip_address_reloc; + bool is_stencil_sampler; }; struct r600_rasterizer_state { @@ -240,8 +276,11 @@ struct r600_rasterizer_state { float offset_units; float offset_scale; bool offset_enable; + bool offset_units_unscaled; bool scissor_enable; bool multisample_enable; + bool clip_halfz; + bool rasterizer_discard; }; struct r600_poly_offset_state { @@ -249,6 +288,7 @@ struct r600_poly_offset_state { enum pipe_format zs_format; float offset_units; float offset_scale; + bool offset_units_unscaled; }; struct r600_blend_state { @@ -277,12 +317,20 @@ struct r600_pipe_shader_selector { struct tgsi_token *tokens; struct pipe_stream_output_info so; + struct tgsi_shader_info info; unsigned num_shaders; - /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ - unsigned type; + enum pipe_shader_type type; + + /* geometry shader properties */ + enum pipe_prim_type gs_output_prim; + unsigned gs_max_out_vertices; + unsigned gs_num_invocations; + /* TCS/VS */ + uint64_t lds_patch_outputs_written_mask; + uint64_t lds_outputs_written_mask; unsigned nr_ps_max_color_exports; }; @@ -308,7 +356,6 @@ struct r600_samplerview_state { uint32_t dirty_mask; uint32_t compressed_depthtex_mask; /* which textures are depth */ uint32_t compressed_colortex_mask; - boolean dirty_txq_constants; boolean dirty_buffer_constants; }; @@ -324,11 +371,15 @@ struct r600_textures_info { struct r600_samplerview_state views; struct r600_sampler_states states; bool is_array_sampler[NUM_TEX_UNITS]; +}; - /* cube array txq workaround */ - uint32_t *txq_constants; - /* buffer related workarounds */ - uint32_t *buffer_constants; +struct r600_shader_driver_constants_info { + /* currently 128 bytes for UCP/samplepos + sampler buffer constants */ + uint32_t *constants; + uint32_t alloc_size; + bool vs_ucp_dirty; + bool texture_const_dirty; + bool ps_sample_pos_dirty; }; struct r600_constbuf_state @@ -355,14 +406,6 @@ struct r600_cso_state struct r600_command_buffer *cb; }; -struct r600_scissor_state -{ - struct r600_atom atom; - struct pipe_scissor_state scissor; - bool enable; /* r6xx only */ - int idx; -}; - struct r600_fetch_shader { struct r600_resource *buffer; unsigned offset; @@ -381,8 +424,8 @@ struct r600_context { /* Hardware info. */ boolean has_vertex_cache; - boolean keep_tiling_flags; - unsigned default_ps_gprs, default_vs_gprs; + unsigned default_gprs[EG_NUM_HW_STAGES]; + unsigned current_gprs[EG_NUM_HW_STAGES]; unsigned r6xx_num_clause_temp_gprs; /* Miscellaneous state objects. */ @@ -402,6 +445,8 @@ struct r600_context { /* State binding slots are here. */ struct r600_atom *atoms[R600_NUM_ATOMS]; + /* Dirty atom bitmask for fast tests */ + uint64_t dirty_atoms; /* States for CS initialization. */ struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ /** Compute specific registers initializations. The start_cs_cmd atom @@ -421,23 +466,21 @@ struct r600_context { struct r600_poly_offset_state poly_offset_state; struct r600_cso_state rasterizer_state; struct r600_sample_mask sample_mask; - struct r600_scissor_state scissor[16]; struct r600_seamless_cube_map seamless_cube_map; struct r600_config_state config_state; struct r600_stencil_ref_state stencil_ref; struct r600_vgt_state vgt_state; - struct r600_viewport_state viewport[16]; /* Shaders and shader resources. */ struct r600_cso_state vertex_fetch_shader; - struct r600_shader_state vertex_shader; - struct r600_shader_state pixel_shader; - struct r600_shader_state geometry_shader; - struct r600_shader_state export_shader; + struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES]; struct r600_cs_shader_state cs_shader_state; struct r600_shader_stages_state shader_stages; struct r600_gs_rings_state gs_rings; struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES]; struct r600_textures_info samplers[PIPE_SHADER_TYPES]; + + struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES]; + /** Vertex buffers for fetch shaders */ struct r600_vertexbuf_state vertex_buffer_state; /** Vertex buffers for compute shaders */ @@ -448,54 +491,90 @@ struct r600_context { struct r600_pipe_shader_selector *ps_shader; struct r600_pipe_shader_selector *vs_shader; struct r600_pipe_shader_selector *gs_shader; + + struct r600_pipe_shader_selector *tcs_shader; + struct r600_pipe_shader_selector *tes_shader; + + struct r600_pipe_shader_selector *fixed_func_tcs_shader; + struct r600_rasterizer_state *rasterizer; bool alpha_to_one; bool force_blend_disable; boolean dual_src_blend; unsigned zwritemask; + int ps_iter_samples; - /* Index buffer. */ - struct pipe_index_buffer index_buffer; + /* The list of all texture buffer objects in this context. + * This list is walked when a buffer is invalidated/reallocated and + * the GPU addresses are updated. */ + struct list_head texture_buffers; /* Last draw state (-1 = unset). */ - int last_primitive_type; /* Last primitive type used in draw_vbo. */ - int last_start_instance; + enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */ + enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ + enum pipe_prim_type last_rast_prim; + unsigned last_start_instance; void *sb_context; struct r600_isa *isa; + float sample_positions[4 * 16]; + float tess_state[8]; + bool tess_state_dirty; + struct r600_pipe_shader_selector *last_ls; + struct r600_pipe_shader_selector *last_tcs; + unsigned last_num_tcs_input_cp; + unsigned lds_alloc; }; -static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs, +static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs, struct r600_command_buffer *cb) { - assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS); - memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw); - cs->cdw += cb->num_dw; + assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); + memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw); + cs->current.cdw += cb->num_dw; } -void r600_trace_emit(struct r600_context *rctx); +static inline void r600_set_atom_dirty(struct r600_context *rctx, + struct r600_atom *atom, + bool dirty) +{ + uint64_t mask; + + assert(atom->id != 0); + assert(atom->id < sizeof(mask) * 8); + mask = 1ull << atom->id; + if (dirty) + rctx->dirty_atoms |= mask; + else + rctx->dirty_atoms &= ~mask; +} + +static inline void r600_mark_atom_dirty(struct r600_context *rctx, + struct r600_atom *atom) +{ + r600_set_atom_dirty(rctx, atom, true); +} -static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) +static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) { atom->emit(&rctx->b, atom); - atom->dirty = false; - if (rctx->screen->b.trace_bo) { - r600_trace_emit(rctx); - } + r600_set_atom_dirty(rctx, atom, false); } -static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso) +static inline void r600_set_cso_state(struct r600_context *rctx, + struct r600_cso_state *state, void *cso) { state->cso = cso; - state->atom.dirty = cso != NULL; + r600_set_atom_dirty(rctx, &state->atom, cso != NULL); } -static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso, +static inline void r600_set_cso_state_with_cb(struct r600_context *rctx, + struct r600_cso_state *state, void *cso, struct r600_command_buffer *cb) { state->cb = cb; state->atom.num_dw = cb ? cb->num_dw : 0; - r600_set_cso_state(state, cso); + r600_set_cso_state(rctx, state, cso); } /* compute_memory_pool.c */ @@ -504,11 +583,6 @@ void compute_memory_pool_delete(struct compute_memory_pool* pool); struct compute_memory_pool* compute_memory_pool_new( struct r600_screen *rscreen); -/* evergreen_compute.c */ -void evergreen_set_cs_sampler_view(struct pipe_context *ctx_, - unsigned start_slot, unsigned count, - struct pipe_sampler_view **views); - /* evergreen_state.c */ struct pipe_sampler_view * evergreen_create_sampler_view_custom(struct pipe_context *ctx, @@ -516,7 +590,8 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, const struct pipe_sampler_view *state, unsigned width0, unsigned height0, unsigned force_level); -void evergreen_init_common_regs(struct r600_command_buffer *cb, +void evergreen_init_common_regs(struct r600_context *ctx, + struct r600_command_buffer *cb, enum chip_class ctx_chip_class, enum radeon_family ctx_family, int ctx_drm_minor); @@ -531,6 +606,8 @@ void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); +void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); +void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); void *evergreen_create_db_flush_dsa(struct r600_context *rctx); void *evergreen_create_resolve_blend(struct r600_context *rctx); void *evergreen_create_decompress_blend(struct r600_context *rctx); @@ -545,18 +622,25 @@ void evergreen_init_color_surface(struct r600_context *rctx, void evergreen_init_color_surface_rat(struct r600_context *rctx, struct r600_surface *surf); void evergreen_update_db_shader_control(struct r600_context * rctx); - +bool evergreen_adjust_gprs(struct r600_context *rctx); /* r600_blit.c */ void r600_init_blit_functions(struct r600_context *rctx); void r600_decompress_depth_textures(struct r600_context *rctx, struct r600_samplerview_state *textures); void r600_decompress_color_textures(struct r600_context *rctx, struct r600_samplerview_state *textures); +void r600_resource_copy_region(struct pipe_context *ctx, + struct pipe_resource *dst, + unsigned dst_level, + unsigned dstx, unsigned dsty, unsigned dstz, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box); /* r600_shader.c */ int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, - struct r600_shader_key key); + union r600_shader_key key); void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); @@ -590,13 +674,15 @@ void r600_context_gfx_flush(void *context, unsigned flags, void r600_begin_new_cs(struct r600_context *ctx); void r600_flush_emit(struct r600_context *ctx); void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); +void r600_emit_pfp_sync_me(struct r600_context *rctx); void r600_cp_dma_copy_buffer(struct r600_context *rctx, struct pipe_resource *dst, uint64_t dst_offset, struct pipe_resource *src, uint64_t src_offset, unsigned size); void evergreen_cp_dma_clear_buffer(struct r600_context *rctx, struct pipe_resource *dst, uint64_t offset, - unsigned size, uint32_t clear_value); + unsigned size, uint32_t clear_value, + enum r600_coherency coher); void r600_dma_copy_buffer(struct r600_context *rctx, struct pipe_resource *dst, struct pipe_resource *src, @@ -613,6 +699,18 @@ void evergreen_dma_copy_buffer(struct r600_context *rctx, uint64_t dst_offset, uint64_t src_offset, uint64_t size); +void evergreen_setup_tess_constants(struct r600_context *rctx, + const struct pipe_draw_info *info, + unsigned *num_patches); +uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx, + const struct pipe_draw_info *info, + unsigned num_patches); +void evergreen_set_ls_hs_config(struct r600_context *rctx, + struct radeon_winsys_cs *cs, + uint32_t ls_hs_config); +void evergreen_set_lds_alloc(struct r600_context *rctx, + struct radeon_winsys_cs *cs, + uint32_t lds_alloc); /* r600_state_common.c */ void r600_init_common_state_functions(struct r600_context *rctx); @@ -622,8 +720,8 @@ void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom); -void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a); +void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id); void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id, void (*emit)(struct r600_context *ctx, struct r600_atom *state), unsigned num_dw); @@ -633,28 +731,23 @@ void r600_sampler_views_dirty(struct r600_context *rctx, void r600_sampler_states_dirty(struct r600_context *rctx, struct r600_sampler_states *state); void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); -void r600_draw_rectangle(struct blitter_context *blitter, - int x1, int y1, int x2, int y2, float depth, - enum blitter_attrib_type type, const union pipe_color_union *attrib); +void r600_set_sample_locations_constant_buffer(struct r600_context *rctx); uint32_t r600_translate_stencil_op(int s_op); uint32_t r600_translate_fill(uint32_t func); unsigned r600_tex_wrap(unsigned wrap); -unsigned r600_tex_filter(unsigned filter); unsigned r600_tex_mipfilter(unsigned filter); unsigned r600_tex_compare(unsigned compare); bool sampler_state_needs_border_color(const struct pipe_sampler_state *state); -struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe, - struct pipe_resource *texture, - const struct pipe_surface *templ, - unsigned width, unsigned height); unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, const unsigned char *swizzle_view, boolean vtx); uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, const unsigned char *swizzle_view, - uint32_t *word4_p, uint32_t *yuv_format_p); -uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format); -uint32_t r600_colorformat_endian_swap(uint32_t colorformat); + uint32_t *word4_p, uint32_t *yuv_format_p, + bool do_endian_swap); +uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format, + bool do_endian_swap); +uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap); /* r600_uvd.c */ struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context, @@ -678,9 +771,9 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, #define R600_LOOP_CONST_OFFSET 0X0003E200 #define EG_LOOP_CONST_OFFSET 0x0003A200 -#define PKT_TYPE_S(x) (((x) & 0x3) << 30) -#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) -#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) +#define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30) +#define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16) +#define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8) #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) @@ -689,19 +782,19 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, /*Evergreen Compute packet3*/ #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) -static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) +static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value) { cb->buf[cb->num_dw++] = value; } -static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr) +static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr) { assert(cb->num_dw+num <= cb->max_num_dw); memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0])); cb->num_dw += num; } -static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) +static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg < R600_CONTEXT_REG_OFFSET); assert(cb->num_dw+2+num <= cb->max_num_dw); @@ -713,7 +806,7 @@ static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, uns * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute * shaders. */ -static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) +static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); assert(cb->num_dw+2+num <= cb->max_num_dw); @@ -725,7 +818,7 @@ static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, un * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute * shaders. */ -static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) +static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); assert(cb->num_dw+2+num <= cb->max_num_dw); @@ -733,7 +826,7 @@ static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsi cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; } -static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) +static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_LOOP_CONST_OFFSET); assert(cb->num_dw+2+num <= cb->max_num_dw); @@ -745,7 +838,7 @@ static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, uns * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute * shaders. */ -static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) +static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= EG_LOOP_CONST_OFFSET); assert(cb->num_dw+2+num <= cb->max_num_dw); @@ -753,31 +846,31 @@ static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsig cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; } -static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) +static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) { r600_store_config_reg_seq(cb, reg, 1); r600_store_value(cb, value); } -static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) +static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) { r600_store_context_reg_seq(cb, reg, 1); r600_store_value(cb, value); } -static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) +static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) { r600_store_ctl_const_seq(cb, reg, 1); r600_store_value(cb, value); } -static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) +static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) { r600_store_loop_const_seq(cb, reg, 1); r600_store_value(cb, value); } -static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) +static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) { eg_store_loop_const_seq(cb, reg, 1); r600_store_value(cb, value); @@ -786,92 +879,77 @@ static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw); void r600_release_command_buffer(struct r600_command_buffer *cb); -static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) { - r600_write_context_reg_seq(cs, reg, num); + radeon_set_context_reg_seq(cs, reg, num); /* Set the compute bit on the packet header */ - cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; + cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; } -static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); - assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); - cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; + assert(cs->current.cdw + 2 + num <= cs->current.max_dw); + radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0)); + radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2); } -static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) { - r600_write_compute_context_reg_seq(cs, reg, 1); + radeon_compute_set_context_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag) +static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag) { if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) { - r600_write_compute_context_reg(cs, reg, value); + radeon_compute_set_context_reg(cs, reg, value); } else { - r600_write_context_reg(cs, reg, value); + radeon_set_context_reg(cs, reg, value); } } -static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) { - r600_write_ctl_const_seq(cs, reg, 1); + radeon_set_ctl_const_seq(cs, reg, 1); radeon_emit(cs, value); } /* * common helpers */ -static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) +static inline uint32_t S_FIXED(float value, uint32_t frac_bits) { return value * (1 << frac_bits); } -#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) /* 12.4 fixed-point */ -static INLINE unsigned r600_pack_float_12p4(float x) +static inline unsigned r600_pack_float_12p4(float x) { return x <= 0 ? 0 : x >= 4096 ? 0xffff : x * 16; } -/* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */ -static INLINE bool r600_can_read_depth(struct r600_texture *rtex) +static inline unsigned r600_get_flush_flags(enum r600_coherency coher) { - return rtex->resource.b.b.nr_samples <= 1 && - (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM || - rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT); + switch (coher) { + default: + case R600_COHERENCY_NONE: + return 0; + case R600_COHERENCY_SHADER: + return R600_CONTEXT_INV_CONST_CACHE | + R600_CONTEXT_INV_VERTEX_CACHE | + R600_CONTEXT_INV_TEX_CACHE | + R600_CONTEXT_STREAMOUT_FLUSH; + case R600_COHERENCY_CB_META: + return R600_CONTEXT_FLUSH_AND_INV_CB | + R600_CONTEXT_FLUSH_AND_INV_CB_META; + } } #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2 -static INLINE unsigned r600_conv_prim_to_gs_out(unsigned mode) -{ - static const int prim_conv[] = { - V_028A6C_OUTPRIM_TYPE_POINTLIST, - V_028A6C_OUTPRIM_TYPE_LINESTRIP, - V_028A6C_OUTPRIM_TYPE_LINESTRIP, - V_028A6C_OUTPRIM_TYPE_LINESTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP, - V_028A6C_OUTPRIM_TYPE_LINESTRIP, - V_028A6C_OUTPRIM_TYPE_LINESTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP, - V_028A6C_OUTPRIM_TYPE_TRISTRIP - }; - assert(mode < Elements(prim_conv)); - - return prim_conv[mode]; -} - +unsigned r600_conv_prim_to_gs_out(unsigned mode); #endif