X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_pipe_common.c;h=486e503422efcd61518969600f242ff7ce2df377;hb=882ca6dfb0f3d17e0f8bc917307d915ab1718069;hp=e02c43f93b8cd823f3a90fde2f31b23f103cc23c;hpb=5c78d000e60266fcee08c8c7f509913a49e68c56;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c index e02c43f93b8..486e503422e 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.c +++ b/src/gallium/drivers/r600/r600_pipe_common.c @@ -30,7 +30,7 @@ #include "util/list.h" #include "util/u_draw_quad.h" #include "util/u_memory.h" -#include "util/u_format_s3tc.h" +#include "util/format/u_format_s3tc.h" #include "util/u_upload_mgr.h" #include "util/os_time.h" #include "vl/vl_decoder.h" @@ -39,18 +39,10 @@ #include #include -#ifndef HAVE_LLVM -#define HAVE_LLVM 0 -#endif - -#if HAVE_LLVM +#ifdef LLVM_AVAILABLE #include #endif -#ifndef MESA_LLVM_VERSION_PATCH -#define MESA_LLVM_VERSION_PATCH 0 -#endif - struct r600_multi_fence { struct pipe_reference reference; struct pipe_fence_handle *gfx; @@ -63,27 +55,6 @@ struct r600_multi_fence { } gfx_unflushed; }; -/* - * shader binary helpers. - */ -void radeon_shader_binary_init(struct ac_shader_binary *b) -{ - memset(b, 0, sizeof(*b)); -} - -void radeon_shader_binary_clean(struct ac_shader_binary *b) -{ - if (!b) - return; - FREE(b->code); - FREE(b->config); - FREE(b->rodata); - FREE(b->global_symbol_offsets); - FREE(b->relocs); - FREE(b->disasm_string); - FREE(b->llvm_ir_string); -} - /* * pipe_context */ @@ -105,7 +76,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx, struct r600_resource *buf, uint64_t va, uint32_t new_fence, unsigned query_type) { - struct radeon_winsys_cs *cs = ctx->gfx.cs; + struct radeon_cmdbuf *cs = ctx->gfx.cs; unsigned op = EVENT_TYPE(event) | EVENT_INDEX(5) | event_flags; @@ -127,16 +98,17 @@ unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen) { unsigned dwords = 6; - if (!screen->info.has_virtual_memory) + if (!screen->info.r600_has_virtual_memory) dwords += 2; return dwords; } void r600_gfx_wait_fence(struct r600_common_context *ctx, + struct r600_resource *buf, uint64_t va, uint32_t ref, uint32_t mask) { - struct radeon_winsys_cs *cs = ctx->gfx.cs; + struct radeon_cmdbuf *cs = ctx->gfx.cs; radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1)); @@ -145,6 +117,10 @@ void r600_gfx_wait_fence(struct r600_common_context *ctx, radeon_emit(cs, ref); /* reference value */ radeon_emit(cs, mask); /* mask */ radeon_emit(cs, 4); /* poll interval */ + + if (buf) + r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ, + RADEON_PRIO_QUERY); } void r600_draw_rectangle(struct blitter_context *blitter, @@ -237,7 +213,7 @@ void r600_draw_rectangle(struct blitter_context *blitter, static void r600_dma_emit_wait_idle(struct r600_common_context *rctx) { - struct radeon_winsys_cs *cs = rctx->dma.cs; + struct radeon_cmdbuf *cs = rctx->dma.cs; if (rctx->chip_class >= EVERGREEN) radeon_emit(cs, 0xf0000000); /* NOP */ @@ -285,7 +261,7 @@ void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw, * engine busy while uploads are being submitted. */ num_dw++; /* for emit_wait_idle below */ - if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) || + if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw, false) || ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 || !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) { ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL); @@ -306,15 +282,13 @@ void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw, /* If GPUVM is not supported, the CS checker needs 2 entries * in the buffer list per packet, which has to be done manually. */ - if (ctx->screen->info.has_virtual_memory) { + if (ctx->screen->info.r600_has_virtual_memory) { if (dst) radeon_add_to_buffer_list(ctx, &ctx->dma, dst, - RADEON_USAGE_WRITE, - RADEON_PRIO_SDMA_BUFFER); + RADEON_USAGE_WRITE, 0); if (src) radeon_add_to_buffer_list(ctx, &ctx->dma, src, - RADEON_USAGE_READ, - RADEON_PRIO_SDMA_BUFFER); + RADEON_USAGE_READ, 0); } /* this function is called before all DMA calls, so increment this. */ @@ -324,7 +298,7 @@ void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw, void r600_preflush_suspend_features(struct r600_common_context *ctx) { /* suspend queries */ - if (!LIST_IS_EMPTY(&ctx->active_queries)) + if (!list_is_empty(&ctx->active_queries)) r600_suspend_queries(ctx); ctx->streamout.suspended = false; @@ -342,52 +316,16 @@ void r600_postflush_resume_features(struct r600_common_context *ctx) } /* resume queries */ - if (!LIST_IS_EMPTY(&ctx->active_queries)) + if (!list_is_empty(&ctx->active_queries)) r600_resume_queries(ctx); } -static void r600_add_fence_dependency(struct r600_common_context *rctx, - struct pipe_fence_handle *fence) -{ - struct radeon_winsys *ws = rctx->ws; - - if (rctx->dma.cs) - ws->cs_add_fence_dependency(rctx->dma.cs, fence); - ws->cs_add_fence_dependency(rctx->gfx.cs, fence); -} - static void r600_fence_server_sync(struct pipe_context *ctx, struct pipe_fence_handle *fence) { - struct r600_common_context *rctx = (struct r600_common_context *)ctx; - struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence; - - /* Only amdgpu needs to handle fence dependencies (for fence imports). - * radeon synchronizes all rings by default and will not implement + /* radeon synchronizes all rings by default and will not implement * fence imports. */ - if (rctx->screen->info.drm_major == 2) - return; - - /* Only imported fences need to be handled by fence_server_sync, - * because the winsys handles synchronizations automatically for BOs - * within the process. - * - * Simply skip unflushed fences here, and the winsys will drop no-op - * dependencies (i.e. dependencies within the same ring). - */ - if (rfence->gfx_unflushed.ctx) - return; - - /* All unflushed commands will not start execution before - * this fence dependency is signalled. - * - * Should we flush the context to allow more GPU parallelism? - */ - if (rfence->sdma) - r600_add_fence_dependency(rctx, rfence->sdma); - if (rfence->gfx) - r600_add_fence_dependency(rctx, rfence->gfx); } static void r600_flush_from_st(struct pipe_context *ctx, @@ -463,7 +401,7 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags, struct pipe_fence_handle **fence) { struct r600_common_context *rctx = (struct r600_common_context *)ctx; - struct radeon_winsys_cs *cs = rctx->dma.cs; + struct radeon_cmdbuf *cs = rctx->dma.cs; struct radeon_saved_cs saved; bool check_vm = (rctx->screen->debug_flags & DBG_CHECK_VM) && @@ -497,7 +435,7 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags, * Store a linearized copy of all chunks of \p cs together with the buffer * list in \p saved. */ -void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, +void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved, bool get_buffer_list) { uint32_t *buf; @@ -547,14 +485,8 @@ void radeon_clear_saved_cs(struct radeon_saved_cs *saved) static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx) { struct r600_common_context *rctx = (struct r600_common_context *)ctx; - unsigned latest = rctx->ws->query_value(rctx->ws, - RADEON_GPU_RESET_COUNTER); - if (rctx->gpu_reset_counter == latest) - return PIPE_NO_RESET; - - rctx->gpu_reset_counter = latest; - return PIPE_UNKNOWN_CONTEXT_RESET; + return rctx->ws->ctx_query_reset_status(rctx->ctx); } static void r600_set_debug_callback(struct pipe_context *ctx, @@ -674,13 +606,7 @@ bool r600_common_context_init(struct r600_common_context *rctx, else rctx->b.buffer_subdata = r600_buffer_subdata; - if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) { - rctx->b.get_device_reset_status = r600_get_reset_status; - rctx->gpu_reset_counter = - rctx->ws->query_value(rctx->ws, - RADEON_GPU_RESET_COUNTER); - } - + rctx->b.get_device_reset_status = r600_get_reset_status; rctx->b.set_device_reset_callback = r600_set_device_reset_callback; r600_init_context_texture_functions(rctx); @@ -712,7 +638,7 @@ bool r600_common_context_init(struct r600_common_context *rctx, if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) { rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA, r600_flush_dma_ring, - rctx); + rctx, false); rctx->dma.flush = r600_flush_dma_ring; } @@ -806,13 +732,6 @@ static const char* r600_get_device_vendor(struct pipe_screen* pscreen) return "AMD"; } -static const char *r600_get_marketing_name(struct radeon_winsys *ws) -{ - if (!ws->get_chip_name) - return NULL; - return ws->get_chip_name(ws); -} - static const char *r600_get_family_name(const struct r600_common_screen *rscreen) { switch (rscreen->info.family) { @@ -851,27 +770,28 @@ static void r600_disk_cache_create(struct r600_common_screen *rscreen) if (rscreen->debug_flags & DBG_ALL_SHADERS) return; - uint32_t mesa_timestamp; - if (disk_cache_get_function_timestamp(r600_disk_cache_create, - &mesa_timestamp)) { - char *timestamp_str; - int res = -1; - - res = asprintf(×tamp_str, "%u",mesa_timestamp); - if (res != -1) { - /* These flags affect shader compilation. */ - uint64_t shader_debug_flags = - rscreen->debug_flags & - (DBG_FS_CORRECT_DERIVS_AFTER_KILL | - DBG_UNSAFE_MATH); - - rscreen->disk_shader_cache = - disk_cache_create(r600_get_family_name(rscreen), - timestamp_str, - shader_debug_flags); - free(timestamp_str); - } - } + struct mesa_sha1 ctx; + unsigned char sha1[20]; + char cache_id[20 * 2 + 1]; + + _mesa_sha1_init(&ctx); + if (!disk_cache_get_function_identifier(r600_disk_cache_create, + &ctx)) + return; + + _mesa_sha1_final(&ctx, sha1); + disk_cache_format_hex_id(cache_id, sha1, 20 * 2); + + /* These flags affect shader compilation. */ + uint64_t shader_debug_flags = + rscreen->debug_flags & + (DBG_FS_CORRECT_DERIVS_AFTER_KILL | + DBG_UNSAFE_MATH); + + rscreen->disk_shader_cache = + disk_cache_create(r600_get_family_name(rscreen), + cache_id, + shader_debug_flags); } static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen) @@ -905,11 +825,10 @@ static float r600_get_paramf(struct pipe_screen* pscreen, return 16.0f; case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: return 16.0f; - case PIPE_CAPF_GUARD_BAND_LEFT: - case PIPE_CAPF_GUARD_BAND_TOP: - case PIPE_CAPF_GUARD_BAND_RIGHT: - case PIPE_CAPF_GUARD_BAND_BOTTOM: - return 0.0f; + case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: + case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: + case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: + return 0.0f; } return 0.0f; } @@ -996,7 +915,7 @@ static unsigned get_max_threads_per_block(struct r600_common_screen *screen, if (ir_type != PIPE_SHADER_IR_TGSI) return 256; if (screen->chip_class >= EVERGREEN) - return 2048; + return 1024; return 256; } @@ -1167,10 +1086,10 @@ static void r600_fence_reference(struct pipe_screen *screen, *rdst = rsrc; } -static boolean r600_fence_finish(struct pipe_screen *screen, - struct pipe_context *ctx, - struct pipe_fence_handle *fence, - uint64_t timeout) +static bool r600_fence_finish(struct pipe_screen *screen, + struct pipe_context *ctx, + struct pipe_fence_handle *fence, + uint64_t timeout) { struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws; struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence; @@ -1247,12 +1166,8 @@ static void r600_query_memory_info(struct pipe_screen *screen, info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024; - if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4) - info->nr_device_memory_evictions = - ws->query_value(ws, RADEON_NUM_EVICTIONS); - else - /* Just return the number of evicted 64KB pages. */ - info->nr_device_memory_evictions = info->device_memory_evicted / 64; + /* Just return the number of evicted 64KB pages. */ + info->nr_device_memory_evictions = info->device_memory_evicted / 64; } struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen, @@ -1268,34 +1183,28 @@ struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen, bool r600_common_screen_init(struct r600_common_screen *rscreen, struct radeon_winsys *ws) { - char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {}; + char family_name[32] = {}, kernel_version[128] = {}; struct utsname uname_data; const char *chip_name; ws->query_info(ws, &rscreen->info); rscreen->ws = ws; - if ((chip_name = r600_get_marketing_name(ws))) - snprintf(family_name, sizeof(family_name), "%s / ", - r600_get_family_name(rscreen) + 4); - else - chip_name = r600_get_family_name(rscreen); + chip_name = r600_get_family_name(rscreen); if (uname(&uname_data) == 0) snprintf(kernel_version, sizeof(kernel_version), " / %s", uname_data.release); - if (HAVE_LLVM > 0) { - snprintf(llvm_string, sizeof(llvm_string), - ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff, - HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH); - } - snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string), - "%s (%sDRM %i.%i.%i%s%s)", + "%s (%sDRM %i.%i.%i%s" +#ifdef LLVM_AVAILABLE + ", LLVM " MESA_LLVM_VERSION_STRING +#endif + ")", chip_name, family_name, rscreen->info.drm_major, rscreen->info.drm_minor, rscreen->info.drm_patchlevel, - kernel_version, llvm_string); + kernel_version); rscreen->b.get_name = r600_get_name; rscreen->b.get_vendor = r600_get_vendor; @@ -1356,7 +1265,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024)); printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size); printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram); - printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory); + printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory); printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2); printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode); printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);