X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_resource.h;h=4c55f66e50c4f3e33cde0d5c5405eac22c96e89c;hb=033eec4145df132b961b8e5c83e222424859db4d;hp=d07ff9e1e0437b5173ea1693a4f558870bd2023e;hpb=2c339f801516d4f6201e8bd4cd0fe0033f36046a;p=mesa.git

diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index d07ff9e1e04..4c55f66e50c 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -41,7 +41,7 @@ struct r600_resource {
 	struct radeon_winsys_cs_handle	*cs_buf;
 
 	/* Resource state. */
-	unsigned			domains;
+	enum radeon_bo_domain		domains;
 
 	/* The buffer range which is initialized (with a write transfer,
 	 * streamout, DMA, or as a random access target). The rest of
@@ -84,11 +84,15 @@ struct r600_texture {
 	/* FMASK and CMASK can only be used with MSAA textures for now.
 	 * MSAA textures cannot have mipmaps. */
 	unsigned			fmask_offset, fmask_size, fmask_bank_height;
-	unsigned			cmask_offset, cmask_size, cmask_slice_tile_max;
+	unsigned			fmask_slice_tile_max;
+	unsigned			cmask_offset, cmask_size;
+	unsigned			cmask_slice_tile_max;
 
 	struct r600_resource		*htile;
 	/* use htile only for first level */
 	float				depth_clear;
+
+	unsigned			color_clear_value[2];
 };
 
 #define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
@@ -97,6 +101,7 @@ struct r600_fmask_info {
 	unsigned size;
 	unsigned alignment;
 	unsigned bank_height;
+	unsigned slice_tile_max;
 };
 
 struct r600_cmask_info {