X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_state.c;h=e38d1c9099ff0fb8a8bd3f06a377adb16ed16e89;hb=dbd24b5df6739b85638020c0e5ab1cc9ff84a4b7;hp=f6a840a9cde9192118e828a46984011e9adaee07;hpb=b205f53c7fe1a1b63465ad8b55047d7b5490d4b6;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index f6a840a9cde..e38d1c9099f 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -261,11 +261,11 @@ static uint32_t r600_translate_dbformat(enum pipe_format format) return V_028010_DEPTH_16; case PIPE_FORMAT_Z24X8_UNORM: return V_028010_DEPTH_X8_24; - case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: return V_028010_DEPTH_8_24; case PIPE_FORMAT_Z32_FLOAT: return V_028010_DEPTH_32_FLOAT; - case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED: + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: return V_028010_DEPTH_X24_8_32_FLOAT; default: return ~0U; @@ -277,10 +277,16 @@ static uint32_t r600_translate_colorswap(enum pipe_format format) switch (format) { /* 8-bit buffers. */ case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_A8_UINT: + case PIPE_FORMAT_A8_SINT: case PIPE_FORMAT_R4A4_UNORM: return V_0280A0_SWAP_ALT_REV; case PIPE_FORMAT_I8_UNORM: case PIPE_FORMAT_L8_UNORM: + case PIPE_FORMAT_I8_UINT: + case PIPE_FORMAT_I8_SINT: + case PIPE_FORMAT_L8_UINT: + case PIPE_FORMAT_L8_SINT: case PIPE_FORMAT_L8_SRGB: case PIPE_FORMAT_R8_UNORM: case PIPE_FORMAT_R8_SNORM: @@ -306,12 +312,18 @@ static uint32_t r600_translate_colorswap(enum pipe_format format) return V_0280A0_SWAP_STD; case PIPE_FORMAT_L8A8_UNORM: + case PIPE_FORMAT_L8A8_UINT: + case PIPE_FORMAT_L8A8_SINT: case PIPE_FORMAT_L8A8_SRGB: return V_0280A0_SWAP_ALT; case PIPE_FORMAT_R8G8_UNORM: + case PIPE_FORMAT_R8G8_UINT: + case PIPE_FORMAT_R8G8_SINT: return V_0280A0_SWAP_STD; case PIPE_FORMAT_R16_UNORM: + case PIPE_FORMAT_R16_UINT: + case PIPE_FORMAT_R16_SINT: case PIPE_FORMAT_R16_FLOAT: return V_0280A0_SWAP_STD; @@ -334,6 +346,8 @@ static uint32_t r600_translate_colorswap(enum pipe_format format) case PIPE_FORMAT_R8G8B8X8_UNORM: case PIPE_FORMAT_R8G8B8A8_SSCALED: case PIPE_FORMAT_R8G8B8A8_USCALED: + case PIPE_FORMAT_R8G8B8A8_SINT: + case PIPE_FORMAT_R8G8B8A8_UINT: return V_0280A0_SWAP_STD; case PIPE_FORMAT_A8B8G8R8_UNORM: @@ -342,11 +356,11 @@ static uint32_t r600_translate_colorswap(enum pipe_format format) return V_0280A0_SWAP_STD_REV; case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: return V_0280A0_SWAP_STD; case PIPE_FORMAT_X8Z24_UNORM: - case PIPE_FORMAT_S8_USCALED_Z24_UNORM: + case PIPE_FORMAT_S8_UINT_Z24_UNORM: return V_0280A0_SWAP_STD; case PIPE_FORMAT_R10G10B10A2_UNORM: @@ -360,23 +374,35 @@ static uint32_t r600_translate_colorswap(enum pipe_format format) case PIPE_FORMAT_R11G11B10_FLOAT: case PIPE_FORMAT_R16G16_UNORM: case PIPE_FORMAT_R16G16_FLOAT: + case PIPE_FORMAT_R16G16_UINT: + case PIPE_FORMAT_R16G16_SINT: + case PIPE_FORMAT_R32_UINT: + case PIPE_FORMAT_R32_SINT: case PIPE_FORMAT_R32_FLOAT: case PIPE_FORMAT_Z32_FLOAT: return V_0280A0_SWAP_STD; /* 64-bit buffers. */ case PIPE_FORMAT_R32G32_FLOAT: + case PIPE_FORMAT_R32G32_UINT: + case PIPE_FORMAT_R32G32_SINT: case PIPE_FORMAT_R16G16B16A16_UNORM: case PIPE_FORMAT_R16G16B16A16_SNORM: case PIPE_FORMAT_R16G16B16A16_USCALED: case PIPE_FORMAT_R16G16B16A16_SSCALED: + case PIPE_FORMAT_R16G16B16A16_UINT: + case PIPE_FORMAT_R16G16B16A16_SINT: case PIPE_FORMAT_R16G16B16A16_FLOAT: - case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED: + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: /* 128-bit buffers. */ case PIPE_FORMAT_R32G32B32A32_FLOAT: case PIPE_FORMAT_R32G32B32A32_SNORM: case PIPE_FORMAT_R32G32B32A32_UNORM: + case PIPE_FORMAT_R32G32B32A32_USCALED: + case PIPE_FORMAT_R32G32B32A32_SSCALED: + case PIPE_FORMAT_R32G32B32A32_SINT: + case PIPE_FORMAT_R32G32B32A32_UINT: return V_0280A0_SWAP_STD; default: R600_ERR("unsupported colorswap format %d\n", format); @@ -395,11 +421,19 @@ static uint32_t r600_translate_colorformat(enum pipe_format format) /* 8-bit buffers. */ case PIPE_FORMAT_A8_UNORM: + case PIPE_FORMAT_A8_UINT: + case PIPE_FORMAT_A8_SINT: case PIPE_FORMAT_I8_UNORM: + case PIPE_FORMAT_I8_UINT: + case PIPE_FORMAT_I8_SINT: case PIPE_FORMAT_L8_UNORM: + case PIPE_FORMAT_L8_UINT: + case PIPE_FORMAT_L8_SINT: case PIPE_FORMAT_L8_SRGB: case PIPE_FORMAT_R8_UNORM: case PIPE_FORMAT_R8_SNORM: + case PIPE_FORMAT_R8_UINT: + case PIPE_FORMAT_R8_SINT: return V_0280A0_COLOR_8; /* 16-bit buffers. */ @@ -418,11 +452,17 @@ static uint32_t r600_translate_colorformat(enum pipe_format format) return V_0280A0_COLOR_16; case PIPE_FORMAT_L8A8_UNORM: + case PIPE_FORMAT_L8A8_UINT: + case PIPE_FORMAT_L8A8_SINT: case PIPE_FORMAT_L8A8_SRGB: case PIPE_FORMAT_R8G8_UNORM: + case PIPE_FORMAT_R8G8_UINT: + case PIPE_FORMAT_R8G8_SINT: return V_0280A0_COLOR_8_8; case PIPE_FORMAT_R16_UNORM: + case PIPE_FORMAT_R16_UINT: + case PIPE_FORMAT_R16_SINT: return V_0280A0_COLOR_16; case PIPE_FORMAT_R16_FLOAT: @@ -444,6 +484,8 @@ static uint32_t r600_translate_colorformat(enum pipe_format format) case PIPE_FORMAT_X8B8G8R8_UNORM: case PIPE_FORMAT_X8R8G8B8_UNORM: case PIPE_FORMAT_R8G8B8_UNORM: + case PIPE_FORMAT_R8G8B8A8_SINT: + case PIPE_FORMAT_R8G8B8A8_UINT: return V_0280A0_COLOR_8_8_8_8; case PIPE_FORMAT_R10G10B10A2_UNORM: @@ -453,14 +495,14 @@ static uint32_t r600_translate_colorformat(enum pipe_format format) return V_0280A0_COLOR_2_10_10_10; case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: return V_0280A0_COLOR_8_24; case PIPE_FORMAT_X8Z24_UNORM: - case PIPE_FORMAT_S8_USCALED_Z24_UNORM: + case PIPE_FORMAT_S8_UINT_Z24_UNORM: return V_0280A0_COLOR_24_8; - case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED: + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: return V_0280A0_COLOR_X24_8_32_FLOAT; case PIPE_FORMAT_R32_FLOAT: @@ -472,6 +514,8 @@ static uint32_t r600_translate_colorformat(enum pipe_format format) case PIPE_FORMAT_R16G16_SSCALED: case PIPE_FORMAT_R16G16_UNORM: + case PIPE_FORMAT_R16G16_UINT: + case PIPE_FORMAT_R16G16_SINT: return V_0280A0_COLOR_16_16; case PIPE_FORMAT_R11G11B10_FLOAT: @@ -481,6 +525,8 @@ static uint32_t r600_translate_colorformat(enum pipe_format format) case PIPE_FORMAT_R16G16B16_USCALED: case PIPE_FORMAT_R16G16B16A16_USCALED: case PIPE_FORMAT_R16G16B16_SSCALED: + case PIPE_FORMAT_R16G16B16A16_UINT: + case PIPE_FORMAT_R16G16B16A16_SINT: case PIPE_FORMAT_R16G16B16A16_SSCALED: case PIPE_FORMAT_R16G16B16A16_UNORM: case PIPE_FORMAT_R16G16B16A16_SNORM: @@ -495,6 +541,8 @@ static uint32_t r600_translate_colorformat(enum pipe_format format) case PIPE_FORMAT_R32G32_USCALED: case PIPE_FORMAT_R32G32_SSCALED: + case PIPE_FORMAT_R32G32_SINT: + case PIPE_FORMAT_R32G32_UINT: return V_0280A0_COLOR_32_32; /* 96-bit buffers. */ @@ -506,6 +554,10 @@ static uint32_t r600_translate_colorformat(enum pipe_format format) return V_0280A0_COLOR_32_32_32_32_FLOAT; case PIPE_FORMAT_R32G32B32A32_SNORM: case PIPE_FORMAT_R32G32B32A32_UNORM: + case PIPE_FORMAT_R32G32B32A32_SSCALED: + case PIPE_FORMAT_R32G32B32A32_USCALED: + case PIPE_FORMAT_R32G32B32A32_SINT: + case PIPE_FORMAT_R32G32B32A32_UINT: return V_0280A0_COLOR_32_32_32_32; /* YUV buffers. */ @@ -651,12 +703,12 @@ void r600_polygon_offset_update(struct r600_pipe_context *rctx) switch (rctx->framebuffer.zsbuf->texture->format) { case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_USCALED: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: depth = -24; offset_units *= 2.0f; break; case PIPE_FORMAT_Z32_FLOAT: - case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED: + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: depth = -23; offset_units *= 1.0f; offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); @@ -887,6 +939,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx, unsigned tmp; unsigned prov_vtx = 1, polygon_dual_mode; unsigned clip_rule; + unsigned sc_mode_cntl; if (rs == NULL) { return NULL; @@ -906,7 +959,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx, rstate->id = R600_PIPE_STATE_RASTERIZER; if (state->flatshade_first) prov_vtx = 0; - tmp = S_0286D4_FLAT_SHADE_ENA(1); + tmp = S_0286D4_FLAT_SHADE_ENA(state->flatshade); if (state->sprite_coord_enable) { tmp |= S_0286D4_PNT_SPRITE_ENA(1) | S_0286D4_PNT_SPRITE_OVRD_X(2) | @@ -944,7 +997,21 @@ static void *r600_create_rs_state(struct pipe_context *ctx, tmp = (unsigned)state->line_width * 8; r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL, 0); + if (state->line_stipple_enable) { + r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, + S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | + S_028A0C_REPEAT_COUNT(state->line_stipple_factor), + 0x9FFFFFFF, NULL, 0); + } + + if (rctx->chip_class >= R700) + sc_mode_cntl = 0x514002; + else + sc_mode_cntl = 0x4102; + sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable); + + r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl, + 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0); @@ -956,7 +1023,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx, r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL, 0); + r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0); return rstate; @@ -977,7 +1044,7 @@ static void *r600_create_sampler_state(struct pipe_context *ctx, ss->seamless_cube_map = state->seamless_cube_map; rstate = &ss->rstate; rstate->id = R600_PIPE_STATE_SAMPLER; - util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); + util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0, S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | @@ -994,10 +1061,10 @@ static void *r600_create_sampler_state(struct pipe_context *ctx, S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL, 0); if (uc.ui) { - r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL, 0); + r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), 0xFFFFFFFF, NULL, 0); + r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), 0xFFFFFFFF, NULL, 0); + r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), 0xFFFFFFFF, NULL, 0); + r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), 0xFFFFFFFF, NULL, 0); } return rstate; } @@ -1009,11 +1076,9 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); struct r600_pipe_resource_state *rstate; struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; - struct r600_resource *rbuffer; unsigned format, endian; uint32_t word4 = 0, yuv_format = 0, pitch = 0; unsigned char swizzle[4], array_mode = 0, tile_type = 0; - struct r600_bo *bo[2]; unsigned width, height, depth, offset_level, last_level; if (view == NULL) @@ -1047,15 +1112,6 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c endian = r600_colorformat_endian_swap(format); - if (tmp->force_int_type) { - word4 &= C_038010_NUM_FORMAT_ALL; - word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); - } - - rbuffer = &tmp->resource; - bo[0] = rbuffer->bo; - bo[1] = rbuffer->bo; - offset_level = state->u.tex.first_level; last_level = state->u.tex.last_level - offset_level; width = u_minify(texture->width0, offset_level); @@ -1074,8 +1130,8 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c depth = texture->array_size; } - rstate->bo[0] = bo[0]; - rstate->bo[1] = bo[1]; + rstate->bo[0] = &tmp->resource; + rstate->bo[1] = &tmp->resource; rstate->bo_usage[0] = RADEON_USAGE_READ; rstate->bo_usage[1] = RADEON_USAGE_READ; @@ -1385,7 +1441,6 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta const struct pipe_framebuffer_state *state, int cb) { struct r600_resource_texture *rtex; - struct r600_resource *rbuffer; struct r600_surface *surf; unsigned level = state->cbufs[cb]->u.tex.level; unsigned pitch, slice; @@ -1393,7 +1448,6 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta unsigned format, swap, ntype, endian; unsigned offset; const struct util_format_description *desc; - struct r600_bo *bo[3]; int i; surf = (struct r600_surface *)state->cbufs[cb]; @@ -1407,11 +1461,6 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta rtex = rtex->flushed_depth_texture; } - rbuffer = &rtex->resource; - bo[0] = rbuffer->bo; - bo[1] = rbuffer->bo; - bo[2] = rbuffer->bo; - /* XXX quite sure for dx10+ hw don't need any offset hacks */ offset = r600_texture_get_offset(rtex, level, state->cbufs[cb]->u.tex.first_layer); @@ -1424,24 +1473,30 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta break; } } + ntype = V_0280A0_NUMBER_UNORM; if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) ntype = V_0280A0_NUMBER_SRGB; - else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) - ntype = V_0280A0_NUMBER_SNORM; + else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { + if (desc->channel[i].normalized) + ntype = V_0280A0_NUMBER_SNORM; + else if (desc->channel[i].pure_integer) + ntype = V_0280A0_NUMBER_SINT; + } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { + if (desc->channel[i].normalized) + ntype = V_0280A0_NUMBER_UNORM; + else if (desc->channel[i].pure_integer) + ntype = V_0280A0_NUMBER_UINT; + } format = r600_translate_colorformat(surf->base.format); swap = r600_translate_colorswap(surf->base.format); - if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) { + if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) { endian = ENDIAN_NONE; } else { endian = r600_colorformat_endian_swap(format); } - /* disable when gallium grows int textures */ - if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type) - ntype = V_0280A0_NUMBER_UINT; - color_info = S_0280A0_FORMAT(format) | S_0280A0_COMP_SWAP(swap) | S_0280A0_ARRAY_MODE(rtex->array_mode[level]) | @@ -1482,10 +1537,10 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta r600_pipe_state_add_reg(rstate, R_028040_CB_COLOR0_BASE + cb * 4, - offset >> 8, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE); + offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE); r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + cb * 4, - color_info, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE); + color_info, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE); r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + cb * 4, S_028060_PITCH_TILE_MAX(pitch) | @@ -1496,10 +1551,10 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta 0x00000000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_0280E0_CB_COLOR0_FRAG + cb * 4, - 0, 0xFFFFFFFF, bo[1], RADEON_USAGE_READWRITE); + 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE); r600_pipe_state_add_reg(rstate, R_0280C0_CB_COLOR0_TILE + cb * 4, - 0, 0xFFFFFFFF, bo[2], RADEON_USAGE_READWRITE); + 0, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE); r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + cb * 4, 0x00000000, 0xFFFFFFFF, NULL, 0); @@ -1509,11 +1564,8 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta const struct pipe_framebuffer_state *state) { struct r600_resource_texture *rtex; - struct r600_resource *rbuffer; struct r600_surface *surf; - unsigned level; - unsigned pitch, slice, format; - unsigned offset; + unsigned level, pitch, slice, format, offset, array_mode; if (state->zsbuf == NULL) return; @@ -1523,7 +1575,9 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta surf = (struct r600_surface *)state->zsbuf; rtex = (struct r600_resource_texture*)state->zsbuf->texture; - rbuffer = &rtex->resource; + /* XXX remove this once tiling is properly supported */ + array_mode = rtex->array_mode[level] ? rtex->array_mode[level] : + V_0280A0_ARRAY_1D_TILED_THIN1; /* XXX quite sure for dx10+ hw don't need any offset hacks */ offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture, @@ -1533,14 +1587,14 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta format = r600_translate_dbformat(state->zsbuf->texture->format); r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE, - offset >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE); + offset >> 8, 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE); r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice), 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO, - S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format), - 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE); + S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format), + 0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE); r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL, 0); } @@ -1955,7 +2009,6 @@ void r600_init_config(struct r600_pipe_context *rctx) r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL, 0); } else { r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, @@ -1966,7 +2019,6 @@ void r600_init_config(struct r600_pipe_context *rctx) r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL, 0); } r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0); @@ -2010,6 +2062,7 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad struct r600_shader *rshader = &shader->shader; unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; int pos_index = -1, face_index = -1; + unsigned tmp, sid; rstate->nregs = 0; @@ -2018,6 +2071,30 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad pos_index = i; if (rshader->input[i].name == TGSI_SEMANTIC_FACE) face_index = i; + + sid = rshader->input[i].spi_sid; + + tmp = S_028644_SEMANTIC(sid); + + if (rshader->input[i].name == TGSI_SEMANTIC_COLOR || + rshader->input[i].name == TGSI_SEMANTIC_BCOLOR || + rshader->input[i].name == TGSI_SEMANTIC_POSITION) { + tmp |= S_028644_FLAT_SHADE(1); + } + + if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && + rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) { + tmp |= S_028644_PT_SPRITE_TEX(1); + } + + if (rshader->input[i].centroid) + tmp |= S_028644_SEL_CENTROID(1); + + if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) + tmp |= S_028644_SEL_LINEAR(1); + + r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, + tmp, 0xFFFFFFFF, NULL, 0); } db_shader_control = 0; @@ -2071,8 +2148,8 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ); r600_pipe_state_add_reg(rstate, R_028850_SQ_PGM_RESOURCES_PS, - S_028868_NUM_GPRS(rshader->bc.ngpr) | - S_028868_STACK_SIZE(rshader->bc.nstack), + S_028850_NUM_GPRS(rshader->bc.ngpr) | + S_028850_STACK_SIZE(rshader->bc.nstack), 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(rstate, R_028854_SQ_PGM_EXPORTS_PS, @@ -2095,6 +2172,8 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad r600_pipe_state_add_reg(rstate, R_03E200_SQ_LOOP_CONST_0, 0x01000FFF, 0xFFFFFFFF, NULL, 0); + + shader->sprite_coord_enable = rctx->sprite_coord_enable; } void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) @@ -2102,23 +2181,20 @@ void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shad struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; struct r600_pipe_state *rstate = &shader->rstate; struct r600_shader *rshader = &shader->shader; - unsigned spi_vs_out_id[10]; - unsigned i, tmp, nparams; + unsigned spi_vs_out_id[10] = {}; + unsigned i, tmp, nparams = 0; /* clear previous register */ rstate->nregs = 0; - /* so far never got proper semantic id from tgsi */ - /* FIXME better to move this in config things so they get emited - * only one time per cs - */ - for (i = 0; i < 10; i++) { - spi_vs_out_id[i] = 0; - } - for (i = 0; i < 32; i++) { - tmp = i << ((i & 3) * 8); - spi_vs_out_id[i / 4] |= tmp; + for (i = 0; i < rshader->noutput; i++) { + if (rshader->output[i].spi_sid) { + tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); + spi_vs_out_id[nparams / 4] |= tmp; + nparams++; + } } + for (i = 0; i < 10; i++) { r600_pipe_state_add_reg(rstate, R_028614_SPI_VS_OUT_ID_0 + i * 4, @@ -2129,7 +2205,6 @@ void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shad * VS is required to export at least one param and r600_shader_from_tgsi() * takes care of adding a dummy export. */ - nparams = rshader->noutput - rshader->npos; if (nparams < 1) nparams = 1; @@ -2231,9 +2306,9 @@ void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, enum radeon_bo_usage usage) { rstate->val[0] = offset; - rstate->bo[0] = rbuffer->bo; + rstate->bo[0] = rbuffer; rstate->bo_usage[0] = usage; - rstate->val[1] = rbuffer->bo_size - offset - 1; + rstate->val[1] = rbuffer->buf->size - offset - 1; rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | S_038008_STRIDE(stride); }