X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_state_common.c;h=31d08a877e13b8d556f36dfe5b0a529d821f944b;hb=9bc47dbe5062fe1f462f62bf3a2dda7b2f3ddea3;hp=5ba043087f8fa12bd8170c10b07090144ef814b4;hpb=faaba52aedf9807ced2ddfccc4133589a7bacd5f;p=mesa.git

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 5ba043087f8..31d08a877e1 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -25,17 +25,21 @@
  *          Jerome Glisse <jglisse@redhat.com>
  */
 #include "r600_formats.h"
+#include "r600_shader.h"
 #include "r600d.h"
 
 #include "util/u_draw_quad.h"
+#include "util/u_index_modify.h"
+#include "util/u_memory.h"
 #include "util/u_upload_mgr.h"
+#include "util/u_math.h"
 #include "tgsi/tgsi_parse.h"
-#include <byteswap.h>
 
 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
 
 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
 {
+	assert(!cb->buf);
 	cb->buf = CALLOC(1, 4 * num_dw);
 	cb->max_num_dw = num_dw;
 }
@@ -54,24 +58,23 @@ void r600_init_atom(struct r600_context *rctx,
 	assert(id < R600_NUM_ATOMS);
 	assert(rctx->atoms[id] == NULL);
 	rctx->atoms[id] = atom;
-	atom->id = id;
-	atom->emit = emit;
+	atom->emit = (void*)emit;
 	atom->num_dw = num_dw;
 	atom->dirty = false;
 }
 
 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
 {
-	r600_emit_command_buffer(rctx->cs, ((struct r600_cso_state*)atom)->cb);
+	r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
 }
 
 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
 {
-	struct radeon_winsys_cs *cs = rctx->cs;
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 	struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
 	unsigned alpha_ref = a->sx_alpha_ref;
 
-	if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
+	if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
 		alpha_ref &= ~0x1FFF;
 	}
 
@@ -85,12 +88,10 @@ static void r600_texture_barrier(struct pipe_context *ctx)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
 
-	rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
-
-	/* R6xx errata */
-	if (rctx->chip_class == R600) {
-		rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
-	}
+	rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
+		       R600_CONTEXT_FLUSH_AND_INV_CB |
+		       R600_CONTEXT_FLUSH_AND_INV |
+		       R600_CONTEXT_WAIT_3D_IDLE;
 }
 
 static unsigned r600_conv_pipe_prim(unsigned prim)
@@ -140,7 +141,7 @@ static void r600_bind_blend_state_internal(struct r600_context *rctx,
 		rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
 		update_cb = true;
 	}
-	if (rctx->chip_class <= R700 &&
+	if (rctx->b.chip_class <= R700 &&
 	    rctx->cb_misc_state.cb_color_control != color_control) {
 		rctx->cb_misc_state.cb_color_control = color_control;
 		update_cb = true;
@@ -176,31 +177,25 @@ static void r600_set_blend_color(struct pipe_context *ctx,
 
 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
 {
-	struct radeon_winsys_cs *cs = rctx->cs;
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 	struct pipe_blend_color *state = &rctx->blend_color.state;
 
 	r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
-	r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
-	r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
-	r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
-	r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
+	radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
+	radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
+	radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
+	radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
 }
 
 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
 {
-	struct radeon_winsys_cs *cs = rctx->cs;
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 	struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
 
 	r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
-	r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
-}
-
-void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
-{
-	struct radeon_winsys_cs *cs = rctx->cs;
-	struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
-
-	r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
+	r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
+	radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
+	radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
 }
 
 static void r600_set_clip_state(struct pipe_context *ctx,
@@ -216,7 +211,7 @@ static void r600_set_clip_state(struct pipe_context *ctx,
 	cb.user_buffer = state->ucp;
 	cb.buffer_offset = 0;
 	cb.buffer_size = 4*4*8;
-	ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
+	ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
 	pipe_resource_reference(&cb.buffer, NULL);
 }
 
@@ -231,15 +226,15 @@ static void r600_set_stencil_ref(struct pipe_context *ctx,
 
 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
 {
-	struct radeon_winsys_cs *cs = rctx->cs;
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 	struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
 
 	r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
-	r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
+	radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
 			 S_028430_STENCILREF(a->state.ref_value[0]) |
 			 S_028430_STENCILMASK(a->state.valuemask[0]) |
 			 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
-	r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
+	radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
 			 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
 			 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
 			 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
@@ -249,7 +244,7 @@ static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 				      const struct pipe_stencil_ref *state)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
+	struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
 	struct r600_stencil_ref ref;
 
 	rctx->stencil_ref.pipe_state = *state;
@@ -270,15 +265,13 @@ static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_pipe_dsa *dsa = state;
-	struct r600_pipe_state *rstate;
+	struct r600_dsa_state *dsa = state;
 	struct r600_stencil_ref ref;
 
 	if (state == NULL)
 		return;
-	rstate = &dsa->rstate;
-	rctx->states[rstate->id] = rstate;
-	r600_context_pipe_state_set(rctx, rstate);
+
+	r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
 
 	ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
 	ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
@@ -286,6 +279,16 @@ static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 	ref.valuemask[1] = dsa->valuemask[1];
 	ref.writemask[0] = dsa->writemask[0];
 	ref.writemask[1] = dsa->writemask[1];
+	if (rctx->zwritemask != dsa->zwritemask) {
+		rctx->zwritemask = dsa->zwritemask;
+		if (rctx->b.chip_class >= EVERGREEN) {
+			/* work around some issue when not writting to zbuffer
+			 * we are having lockup on evergreen so do not enable
+			 * hyperz when not writting zbuffer
+			 */
+			rctx->db_misc_state.atom.dirty = true;
+		}
+	}
 
 	r600_set_stencil_ref(ctx, &ref);
 
@@ -295,43 +298,32 @@ static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 		rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
 		rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
 		rctx->alphatest_state.atom.dirty = true;
+		if (rctx->b.chip_class >= EVERGREEN) {
+			evergreen_update_db_shader_control(rctx);
+		} else {
+			r600_update_db_shader_control(rctx);
+		}
 	}
 }
 
-void r600_set_max_scissor(struct r600_context *rctx)
-{
-	/* Set a scissor state such that it doesn't do anything. */
-	struct pipe_scissor_state scissor;
-	scissor.minx = 0;
-	scissor.miny = 0;
-	scissor.maxx = 8192;
-	scissor.maxy = 8192;
-
-	r600_set_scissor_state(rctx, &scissor);
-}
-
 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 {
-	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+	struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 	struct r600_context *rctx = (struct r600_context *)ctx;
 
 	if (state == NULL)
 		return;
 
-	rctx->sprite_coord_enable = rs->sprite_coord_enable;
-	rctx->two_side = rs->two_side;
-	rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
-	rctx->multisample_enable = rs->multisample_enable;
-
 	rctx->rasterizer = rs;
 
-	rctx->states[rs->rstate.id] = &rs->rstate;
-	r600_context_pipe_state_set(rctx, &rs->rstate);
+	r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
 
-	if (rctx->chip_class >= EVERGREEN) {
-		evergreen_polygon_offset_update(rctx);
-	} else {
-		r600_polygon_offset_update(rctx);
+	if (rs->offset_enable &&
+	    (rs->offset_units != rctx->poly_offset_state.offset_units ||
+	     rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
+		rctx->poly_offset_state.offset_units = rs->offset_units;
+		rctx->poly_offset_state.offset_scale = rs->offset_scale;
+		rctx->poly_offset_state.atom.dirty = true;
 	}
 
 	/* Update clip_misc_state. */
@@ -343,31 +335,22 @@ static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 	}
 
 	/* Workaround for a missing scissor enable on r600. */
-	if (rctx->chip_class == R600) {
-		if (rs->scissor_enable != rctx->scissor_enable) {
-			rctx->scissor_enable = rs->scissor_enable;
-
-			if (rs->scissor_enable) {
-				r600_set_scissor_state(rctx, &rctx->scissor);
-			} else {
-				r600_set_max_scissor(rctx);
-			}
-		}
+	if (rctx->b.chip_class == R600 &&
+	    rs->scissor_enable != rctx->scissor.enable) {
+		rctx->scissor.enable = rs->scissor_enable;
+		rctx->scissor.atom.dirty = true;
 	}
+
+	/* Re-emit PA_SC_LINE_STIPPLE. */
+	rctx->last_primitive_type = -1;
 }
 
 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 {
-	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+	struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 
-	if (rctx->rasterizer == rs) {
-		rctx->rasterizer = NULL;
-	}
-	if (rctx->states[rs->rstate.id] == &rs->rstate) {
-		rctx->states[rs->rstate.id] = NULL;
-	}
-	free(rs);
+	r600_release_command_buffer(&rs->buffer);
+	FREE(rs);
 }
 
 static void r600_sampler_view_destroy(struct pipe_context *ctx,
@@ -384,7 +367,7 @@ void r600_sampler_states_dirty(struct r600_context *rctx,
 {
 	if (state->dirty_mask) {
 		if (state->dirty_mask & state->has_bordercolor_mask) {
-			rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+			rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
 		}
 		state->atom.num_dw =
 			util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
@@ -443,11 +426,11 @@ static void r600_bind_sampler_states(struct pipe_context *pipe,
 	r600_sampler_states_dirty(rctx, &dst->states);
 
 	/* Seamless cubemap state. */
-	if (rctx->chip_class <= R700 &&
+	if (rctx->b.chip_class <= R700 &&
 	    seamless_cube_map != -1 &&
 	    seamless_cube_map != rctx->seamless_cube_map.enabled) {
 		/* change in TA_CNTL_AUX need a pipeline flush */
-		rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+		rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
 		rctx->seamless_cube_map.enabled = seamless_cube_map;
 		rctx->seamless_cube_map.atom.dirty = true;
 	}
@@ -477,45 +460,26 @@ static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
 	FREE(blend);
 }
 
-static void r600_delete_state(struct pipe_context *ctx, void *state)
+static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
 {
-	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+	struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
 
-	if (rctx->states[rstate->id] == rstate) {
-		rctx->states[rstate->id] = NULL;
-	}
-	for (int i = 0; i < rstate->nregs; i++) {
-		pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
-	}
-	free(rstate);
+	r600_release_command_buffer(&dsa->buffer);
+	free(dsa);
 }
 
 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 
-	rctx->vertex_elements = v;
-	if (v) {
-		rctx->states[v->rstate.id] = &v->rstate;
-		r600_context_pipe_state_set(rctx, &v->rstate);
-	}
+	r600_set_cso_state(&rctx->vertex_fetch_shader, state);
 }
 
 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
 {
-	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
-
-	if (rctx->states[v->rstate.id] == &v->rstate) {
-		rctx->states[v->rstate.id] = NULL;
-	}
-	if (rctx->vertex_elements == state)
-		rctx->vertex_elements = NULL;
-
-	pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
-	FREE(state);
+	struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
+	pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
+	FREE(shader);
 }
 
 static void r600_set_index_buffer(struct pipe_context *ctx,
@@ -525,7 +489,8 @@ static void r600_set_index_buffer(struct pipe_context *ctx,
 
 	if (ib) {
 		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
-	        memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+		memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+		r600_context_add_resource_size(ctx, ib->buffer);
 	} else {
 		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 	}
@@ -534,48 +499,50 @@ static void r600_set_index_buffer(struct pipe_context *ctx,
 void r600_vertex_buffers_dirty(struct r600_context *rctx)
 {
 	if (rctx->vertex_buffer_state.dirty_mask) {
-		rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
-		rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
+		rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
+		rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
 					       util_bitcount(rctx->vertex_buffer_state.dirty_mask);
 		rctx->vertex_buffer_state.atom.dirty = true;
 	}
 }
 
-static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
-			     const struct pipe_vertex_buffer *input)
+static void r600_set_vertex_buffers(struct pipe_context *ctx,
+				    unsigned start_slot, unsigned count,
+				    const struct pipe_vertex_buffer *input)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
 	struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
-	struct pipe_vertex_buffer *vb = state->vb;
+	struct pipe_vertex_buffer *vb = state->vb + start_slot;
 	unsigned i;
-	/* This sets 1-bit for buffers with index >= count. */
-	uint32_t disable_mask = ~((1ull << count) - 1);
+	uint32_t disable_mask = 0;
 	/* These are the new buffers set by this function. */
 	uint32_t new_buffer_mask = 0;
 
-	/* Set buffers with index >= count to NULL. */
-	uint32_t remaining_buffers_mask =
-		rctx->vertex_buffer_state.enabled_mask & disable_mask;
-
-	while (remaining_buffers_mask) {
-		i = u_bit_scan(&remaining_buffers_mask);
-		pipe_resource_reference(&vb[i].buffer, NULL);
-	}
-
 	/* Set vertex buffers. */
-	for (i = 0; i < count; i++) {
-		if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
-			if (input[i].buffer) {
-				vb[i].stride = input[i].stride;
-				vb[i].buffer_offset = input[i].buffer_offset;
-				pipe_resource_reference(&vb[i].buffer, input[i].buffer);
-				new_buffer_mask |= 1 << i;
-			} else {
-				pipe_resource_reference(&vb[i].buffer, NULL);
-				disable_mask |= 1 << i;
+	if (input) {
+		for (i = 0; i < count; i++) {
+			if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
+				if (input[i].buffer) {
+					vb[i].stride = input[i].stride;
+					vb[i].buffer_offset = input[i].buffer_offset;
+					pipe_resource_reference(&vb[i].buffer, input[i].buffer);
+					new_buffer_mask |= 1 << i;
+					r600_context_add_resource_size(ctx, input[i].buffer);
+				} else {
+					pipe_resource_reference(&vb[i].buffer, NULL);
+					disable_mask |= 1 << i;
+				}
 			}
 		}
-        }
+	} else {
+		for (i = 0; i < count; i++) {
+			pipe_resource_reference(&vb[i].buffer, NULL);
+		}
+		disable_mask = ((1ull << count) - 1);
+	}
+
+	disable_mask <<= start_slot;
+	new_buffer_mask <<= start_slot;
 
 	rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
 	rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
@@ -589,8 +556,8 @@ void r600_sampler_views_dirty(struct r600_context *rctx,
 			      struct r600_samplerview_state *state)
 {
 	if (state->dirty_mask) {
-		rctx->flags |= R600_CONTEXT_TEX_FLUSH;
-		state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
+		rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
+		state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
 				     util_bitcount(state->dirty_mask);
 		state->atom.dirty = true;
 	}
@@ -633,22 +600,23 @@ static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 			struct r600_texture *rtex =
 				(struct r600_texture*)rviews[i]->base.texture;
 
-			if (rtex->is_depth && !rtex->is_flushing_texture) {
-				dst->views.compressed_depthtex_mask |= 1 << i;
-			} else {
-				dst->views.compressed_depthtex_mask &= ~(1 << i);
-			}
-
-			/* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
-			if (rctx->chip_class != CAYMAN && rtex->cmask_size && rtex->fmask_size) {
-				dst->views.compressed_colortex_mask |= 1 << i;
-			} else {
-				dst->views.compressed_colortex_mask &= ~(1 << i);
+			if (rviews[i]->base.texture->target != PIPE_BUFFER) {
+				if (rtex->is_depth && !rtex->is_flushing_texture) {
+					dst->views.compressed_depthtex_mask |= 1 << i;
+				} else {
+					dst->views.compressed_depthtex_mask &= ~(1 << i);
+				}
+
+				/* Track compressed colorbuffers. */
+				if (rtex->cmask_size && rtex->fmask_size) {
+					dst->views.compressed_colortex_mask |= 1 << i;
+				} else {
+					dst->views.compressed_colortex_mask &= ~(1 << i);
+				}
 			}
-
 			/* Changing from array to non-arrays textures and vice versa requires
 			 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
-			if (rctx->chip_class <= R700 &&
+			if (rctx->b.chip_class <= R700 &&
 			    (dst->states.enabled_mask & (1 << i)) &&
 			    (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
 			     rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
@@ -657,6 +625,7 @@ static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 
 			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
 			new_mask |= 1 << i;
+			r600_context_add_resource_size(pipe, views[i]->texture);
 		} else {
 			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 			disable_mask |= 1 << i;
@@ -669,7 +638,8 @@ static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 	dst->views.dirty_mask |= new_mask;
 	dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
 	dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
-
+	dst->views.dirty_txq_constants = TRUE;
+	dst->views.dirty_buffer_constants = TRUE;
 	r600_sampler_views_dirty(rctx, &dst->views);
 
 	if (dirty_sampler_states_mask) {
@@ -690,8 +660,10 @@ static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
 	r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
 }
 
-static void r600_set_viewport_state(struct pipe_context *ctx,
-				    const struct pipe_viewport_state *state)
+static void r600_set_viewport_states(struct pipe_context *ctx,
+                                     unsigned start_slot,
+                                     unsigned num_viewports,
+                                     const struct pipe_viewport_state *state)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
 
@@ -701,37 +673,16 @@ static void r600_set_viewport_state(struct pipe_context *ctx,
 
 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
 {
-	struct radeon_winsys_cs *cs = rctx->cs;
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 	struct pipe_viewport_state *state = &rctx->viewport.state;
 
 	r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
-	r600_write_value(cs, fui(state->scale[0]));     /* R_02843C_PA_CL_VPORT_XSCALE_0  */
-	r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
-	r600_write_value(cs, fui(state->scale[1]));     /* R_028444_PA_CL_VPORT_YSCALE_0  */
-	r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
-	r600_write_value(cs, fui(state->scale[2]));     /* R_02844C_PA_CL_VPORT_ZSCALE_0  */
-	r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
-}
-
-static void *r600_create_vertex_elements(struct pipe_context *ctx, unsigned count,
-					 const struct pipe_vertex_element *elements)
-{
-	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
-
-	assert(count < 32);
-	if (!v)
-		return NULL;
-
-	v->count = count;
-	memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
-
-	if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
-		FREE(v);
-		return NULL;
-	}
-
-	return v;
+	radeon_emit(cs, fui(state->scale[0]));     /* R_02843C_PA_CL_VPORT_XSCALE_0  */
+	radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
+	radeon_emit(cs, fui(state->scale[1]));     /* R_028444_PA_CL_VPORT_YSCALE_0  */
+	radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
+	radeon_emit(cs, fui(state->scale[2]));     /* R_02844C_PA_CL_VPORT_ZSCALE_0  */
+	radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
 }
 
 /* Compute the key for the hw shader variant */
@@ -743,12 +694,14 @@ static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_contex
 	memset(&key, 0, sizeof(key));
 
 	if (sel->type == PIPE_SHADER_FRAGMENT) {
-		key.color_two_side = rctx->two_side;
+		key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
 		key.alpha_to_one = rctx->alpha_to_one &&
-				   rctx->multisample_enable &&
+				   rctx->rasterizer && rctx->rasterizer->multisample_enable &&
 				   !rctx->framebuffer.cb0_is_integer;
-		key.dual_src_blend = rctx->dual_src_blend;
 		key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
+		/* Dual-source blending only makes sense with nr_cbufs == 1. */
+		if (key.nr_cbufs == 1 && rctx->dual_src_blend)
+			key.nr_cbufs = 2;
 	}
 	return key;
 }
@@ -757,13 +710,14 @@ static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_contex
  * (*dirty) is set to 1 if current variant was changed */
 static int r600_shader_select(struct pipe_context *ctx,
         struct r600_pipe_shader_selector* sel,
-        unsigned *dirty)
+        bool *dirty)
 {
 	struct r600_shader_key key;
 	struct r600_context *rctx = (struct r600_context *)ctx;
 	struct r600_pipe_shader * shader = NULL;
 	int r;
 
+	memset(&key, 0, sizeof(key));
 	key = r600_shader_selector_key(ctx, sel);
 
 	/* Check if we don't need to change anything.
@@ -798,6 +752,7 @@ static int r600_shader_select(struct pipe_context *ctx,
 			R600_ERR("Failed to build shader variant (type=%u) %d\n",
 				 sel->type, r);
 			sel->current = NULL;
+			FREE(shader);
 			return r;
 		}
 
@@ -810,20 +765,16 @@ static int r600_shader_select(struct pipe_context *ctx,
 			key = r600_shader_selector_key(ctx, sel);
 		}
 
-		shader->key = key;
+		memcpy(&shader->key, &key, sizeof(key));
 		sel->num_shaders++;
 	}
 
 	if (dirty)
-		*dirty = 1;
+		*dirty = true;
 
 	shader->next_variant = sel->current;
 	sel->current = shader;
 
-	if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
-		r600_adjust_gprs(rctx);
-	}
-
 	if (rctx->ps_shader &&
 	    rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 		rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
@@ -869,45 +820,52 @@ static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
 	if (!state)
 		state = rctx->dummy_pixel_shader;
 
-	rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
-	r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
+	rctx->pixel_shader.shader = rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
+	rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
+	rctx->pixel_shader.atom.dirty = true;
+
+	r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
 
-	if (rctx->chip_class <= R700) {
+	if (rctx->b.chip_class <= R700) {
 		bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
 
 		if (rctx->cb_misc_state.multiwrite != multiwrite) {
 			rctx->cb_misc_state.multiwrite = multiwrite;
 			rctx->cb_misc_state.atom.dirty = true;
 		}
-
-		if (rctx->vs_shader)
-			r600_adjust_gprs(rctx);
 	}
 
 	if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 		rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 		rctx->cb_misc_state.atom.dirty = true;
 	}
+
+	if (rctx->b.chip_class >= EVERGREEN) {
+		evergreen_update_db_shader_control(rctx);
+	} else {
+		r600_update_db_shader_control(rctx);
+	}
 }
 
 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
 
-	rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
-	if (state) {
-		r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
+	if (!state)
+		return;
+
+	rctx->vertex_shader.shader = rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
+	rctx->vertex_shader.atom.dirty = true;
+	rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
 
-		if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
-			r600_adjust_gprs(rctx);
+	r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
 
-		/* Update clip misc state. */
-		if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
-		    rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
-			rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
-			rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
-			rctx->clip_misc_state.atom.dirty = true;
-		}
+	/* Update clip misc state. */
+	if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
+	    rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
+		rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
+		rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
+		rctx->clip_misc_state.atom.dirty = true;
 	}
 }
 
@@ -954,8 +912,8 @@ static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 {
 	if (state->dirty_mask) {
-		rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
-		state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
+		rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
+		state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 								   : util_bitcount(state->dirty_mask)*19;
 		state->atom.dirty = true;
 	}
@@ -972,7 +930,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint
 	/* Note that the state tracker can unbind constant buffers by
 	 * passing NULL here.
 	 */
-	if (unlikely(!input)) {
+	if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
 		state->enabled_mask &= ~(1 << index);
 		state->dirty_mask &= ~(1 << index);
 		pipe_resource_reference(&state->cb[index].buffer, NULL);
@@ -996,7 +954,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint
 			}
 
 			for (i = 0; i < size / 4; ++i) {
-				tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
+				tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
 			}
 
 			u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
@@ -1004,10 +962,13 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint
 		} else {
 			u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 		}
+		/* account it in gtt */
+		rctx->b.gtt += input->buffer_size;
 	} else {
 		/* Setup the hw buffer. */
 		cb->buffer_offset = input->buffer_offset;
 		pipe_resource_reference(&cb->buffer, input->buffer);
+		r600_context_add_resource_size(ctx, input->buffer);
 	}
 
 	state->enabled_mask |= 1 << index;
@@ -1015,86 +976,136 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint
 	r600_constant_buffers_dirty(rctx, state);
 }
 
-static struct pipe_stream_output_target *
-r600_create_so_target(struct pipe_context *ctx,
-		      struct pipe_resource *buffer,
-		      unsigned buffer_offset,
-		      unsigned buffer_size)
+static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 {
-	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_so_target *t;
-	void *ptr;
-
-	t = CALLOC_STRUCT(r600_so_target);
-	if (!t) {
-		return NULL;
-	}
-
-	t->b.reference.count = 1;
-	t->b.context = ctx;
-	pipe_resource_reference(&t->b.buffer, buffer);
-	t->b.buffer_offset = buffer_offset;
-	t->b.buffer_size = buffer_size;
+	struct r600_context *rctx = (struct r600_context*)pipe;
 
-	t->filled_size = (struct r600_resource*)
-		pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
-	ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
-	memset(ptr, 0, t->filled_size->buf->size);
-	rctx->ws->buffer_unmap(t->filled_size->cs_buf);
+	if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
+		return;
 
-	return &t->b;
+	rctx->sample_mask.sample_mask = sample_mask;
+	rctx->sample_mask.atom.dirty = true;
 }
 
-static void r600_so_target_destroy(struct pipe_context *ctx,
-				   struct pipe_stream_output_target *target)
+/*
+ * On r600/700 hw we don't have vertex fetch swizzle, though TBO
+ * doesn't require full swizzles it does need masking and setting alpha
+ * to one, so we setup a set of 5 constants with the masks + alpha value
+ * then in the shader, we AND the 4 components with 0xffffffff or 0,
+ * then OR the alpha with the value given here.
+ * We use a 6th constant to store the txq buffer size in
+ */
+static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
 {
-	struct r600_so_target *t = (struct r600_so_target*)target;
-	pipe_resource_reference(&t->b.buffer, NULL);
-	pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
-	FREE(t);
+	struct r600_textures_info *samplers = &rctx->samplers[shader_type];
+	int bits;
+	uint32_t array_size;
+	struct pipe_constant_buffer cb;
+	int i, j;
+
+	if (!samplers->views.dirty_buffer_constants)
+		return;
+
+	samplers->views.dirty_buffer_constants = FALSE;
+
+	bits = util_last_bit(samplers->views.enabled_mask);
+	array_size = bits * 8 * sizeof(uint32_t) * 4;
+	samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
+	memset(samplers->buffer_constants, 0, array_size);
+	for (i = 0; i < bits; i++) {
+		if (samplers->views.enabled_mask & (1 << i)) {
+			int offset = i * 8;
+			const struct util_format_description *desc;
+			desc = util_format_description(samplers->views.views[i]->base.format);
+
+			for (j = 0; j < 4; j++)
+				if (j < desc->nr_channels)
+					samplers->buffer_constants[offset+j] = 0xffffffff;
+				else
+					samplers->buffer_constants[offset+j] = 0x0;
+			if (desc->nr_channels < 4) {
+				if (desc->channel[0].pure_integer)
+					samplers->buffer_constants[offset+4] = 1;
+				else
+					samplers->buffer_constants[offset+4] = 0x3f800000;
+			} else
+				samplers->buffer_constants[offset + 4] = 0;
+
+			samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+		}
+	}
+
+	cb.buffer = NULL;
+	cb.user_buffer = samplers->buffer_constants;
+	cb.buffer_offset = 0;
+	cb.buffer_size = array_size;
+	rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
+	pipe_resource_reference(&cb.buffer, NULL);
 }
 
-static void r600_set_so_targets(struct pipe_context *ctx,
-				unsigned num_targets,
-				struct pipe_stream_output_target **targets,
-				unsigned append_bitmask)
+/* On evergreen we only need to store the buffer size for TXQ */
+static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
 {
-	struct r600_context *rctx = (struct r600_context *)ctx;
-	unsigned i;
+	struct r600_textures_info *samplers = &rctx->samplers[shader_type];
+	int bits;
+	uint32_t array_size;
+	struct pipe_constant_buffer cb;
+	int i;
 
-	/* Stop streamout. */
-	if (rctx->num_so_targets && !rctx->streamout_start) {
-		r600_context_streamout_end(rctx);
-	}
+	if (!samplers->views.dirty_buffer_constants)
+		return;
 
-	/* Set the new targets. */
-	for (i = 0; i < num_targets; i++) {
-		pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
-	}
-	for (; i < rctx->num_so_targets; i++) {
-		pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
-	}
+	samplers->views.dirty_buffer_constants = FALSE;
 
-	rctx->num_so_targets = num_targets;
-	rctx->streamout_start = num_targets != 0;
-	rctx->streamout_append_bitmask = append_bitmask;
+	bits = util_last_bit(samplers->views.enabled_mask);
+	array_size = bits * sizeof(uint32_t) * 4;
+	samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
+	memset(samplers->buffer_constants, 0, array_size);
+	for (i = 0; i < bits; i++)
+		if (samplers->views.enabled_mask & (1 << i))
+		   samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+
+	cb.buffer = NULL;
+	cb.user_buffer = samplers->buffer_constants;
+	cb.buffer_offset = 0;
+	cb.buffer_size = array_size;
+	rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
+	pipe_resource_reference(&cb.buffer, NULL);
 }
 
-static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
 {
-	struct r600_context *rctx = (struct r600_context*)pipe;
+	struct r600_textures_info *samplers = &rctx->samplers[shader_type];
+	int bits;
+	uint32_t array_size;
+	struct pipe_constant_buffer cb;
+	int i;
 
-	if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
+	if (!samplers->views.dirty_txq_constants)
 		return;
 
-	rctx->sample_mask.sample_mask = sample_mask;
-	rctx->sample_mask.atom.dirty = true;
+	samplers->views.dirty_txq_constants = FALSE;
+
+	bits = util_last_bit(samplers->views.enabled_mask);
+	array_size = bits * sizeof(uint32_t) * 4;
+	samplers->txq_constants = realloc(samplers->txq_constants, array_size);
+	memset(samplers->txq_constants, 0, array_size);
+	for (i = 0; i < bits; i++)
+		if (samplers->views.enabled_mask & (1 << i))
+			samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
+
+	cb.buffer = NULL;
+	cb.user_buffer = samplers->txq_constants;
+	cb.buffer_offset = 0;
+	cb.buffer_size = array_size;
+	rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
+	pipe_resource_reference(&cb.buffer, NULL);
 }
 
-static void r600_update_derived_state(struct r600_context *rctx)
+static bool r600_update_derived_state(struct r600_context *rctx)
 {
 	struct pipe_context * ctx = (struct pipe_context*)rctx;
-	unsigned ps_dirty = 0;
+	bool ps_dirty = false;
 	bool blend_disable;
 
 	if (!rctx->blitter->running) {
@@ -1114,20 +1125,49 @@ static void r600_update_derived_state(struct r600_context *rctx)
 
 	r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
 
-	if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
-		(rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
-		(rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
+	if (rctx->ps_shader && rctx->rasterizer &&
+	    ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
+	     (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
 
-		if (rctx->chip_class >= EVERGREEN)
-			evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
+		if (rctx->b.chip_class >= EVERGREEN)
+			evergreen_update_ps_state(ctx, rctx->ps_shader->current);
 		else
-			r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
+			r600_update_ps_state(ctx, rctx->ps_shader->current);
+
+		ps_dirty = true;
+	}
 
-		ps_dirty = 1;
+	if (ps_dirty) {
+		rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
+		rctx->pixel_shader.atom.dirty = true;
 	}
 
-	if (ps_dirty)
-		r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
+	/* on R600 we stuff masks + txq info into one constant buffer */
+	/* on evergreen we only need a txq info one */
+	if (rctx->b.chip_class < EVERGREEN) {
+		if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
+			r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
+		if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
+			r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
+	} else {
+		if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
+			eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
+		if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
+			eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
+	}
+
+
+	if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
+		r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
+	if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
+		r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
+
+	if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
+		if (!r600_adjust_gprs(rctx)) {
+			/* discard rendering */
+			return false;
+		}
+	}
 
 	blend_disable = (rctx->dual_src_blend &&
 			rctx->ps_shader->current->nr_ps_color_outputs < 2);
@@ -1138,12 +1178,7 @@ static void r600_update_derived_state(struct r600_context *rctx)
 					       rctx->blend_state.cso,
 					       blend_disable);
 	}
-
-	if (rctx->chip_class >= EVERGREEN) {
-		evergreen_update_dual_export_state(rctx);
-	} else {
-		r600_update_dual_export_state(rctx);
-	}
+	return true;
 }
 
 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
@@ -1172,7 +1207,7 @@ static unsigned r600_conv_prim_to_gs_out(unsigned mode)
 
 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
 {
-	struct radeon_winsys_cs *cs = rctx->cs;
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 	struct r600_clip_misc_state *state = &rctx->clip_misc_state;
 
 	r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
@@ -1189,10 +1224,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 	struct pipe_draw_info info = *dinfo;
 	struct pipe_index_buffer ib = {};
 	unsigned i;
-	struct r600_block *dirty_block = NULL, *next_block = NULL;
-	struct radeon_winsys_cs *cs = rctx->cs;
-	uint64_t va;
-	uint8_t *ptr;
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 
 	if (!info.count && (info.indexed || !info.count_from_stream_output)) {
 		assert(0);
@@ -1204,7 +1236,17 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		return;
 	}
 
-	r600_update_derived_state(rctx);
+	/* make sure that the gfx ring is only one active */
+	if (rctx->b.rings.dma.cs) {
+		rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
+	}
+
+	if (!r600_update_derived_state(rctx)) {
+		/* useless to render because current rendering command
+		 * can't be achieved
+		 */
+		return;
+	}
 
 	if (info.indexed) {
 		/* Initialize the index buffer struct. */
@@ -1213,38 +1255,57 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		ib.index_size = rctx->index_buffer.index_size;
 		ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
 
-		/* Translate or upload, if needed. */
-		r600_translate_index_buffer(rctx, &ib, info.count);
+		/* Translate 8-bit indices to 16-bit. */
+		if (ib.index_size == 1) {
+			struct pipe_resource *out_buffer = NULL;
+			unsigned out_offset;
+			void *ptr;
 
-		ptr = (uint8_t*)ib.user_buffer;
-		if (!ib.buffer && ptr) {
+			u_upload_alloc(rctx->uploader, 0, info.count * 2,
+				       &out_offset, &out_buffer, &ptr);
+
+			util_shorten_ubyte_elts_to_userptr(
+						&rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
+
+			pipe_resource_reference(&ib.buffer, NULL);
+			ib.user_buffer = NULL;
+			ib.buffer = out_buffer;
+			ib.offset = out_offset;
+			ib.index_size = 2;
+		}
+
+		/* Upload the index buffer.
+		 * The upload is skipped for small index counts on little-endian machines
+		 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
+		 * Note: Instanced rendering in combination with immediate indices hangs. */
+		if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
+				       info.count*ib.index_size > 20)) {
 			u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
-				      ptr, &ib.offset, &ib.buffer);
+				      ib.user_buffer, &ib.offset, &ib.buffer);
+			ib.user_buffer = NULL;
 		}
 	} else {
 		info.index_bias = info.start;
 	}
 
-	/* Enable stream out if needed. */
-	if (rctx->streamout_start) {
-		r600_context_streamout_begin(rctx);
-		rctx->streamout_start = FALSE;
-	}
-
-	/* Set the index offset and multi primitive */
-	if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
-		rctx->vgt2_state.vgt_indx_offset = info.index_bias;
-		rctx->vgt2_state.atom.dirty = true;
-	}
+	/* Set the index offset and primitive restart. */
 	if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
-	    rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
+	    rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
+	    rctx->vgt_state.vgt_indx_offset != info.index_bias) {
 		rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
 		rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
+		rctx->vgt_state.vgt_indx_offset = info.index_bias;
 		rctx->vgt_state.atom.dirty = true;
 	}
 
-	/* Emit states (the function expects that we emit at most 17 dwords here). */
-	r600_need_cs_space(rctx, 0, TRUE);
+	/* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
+	if (rctx->b.chip_class == R600) {
+		rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+		rctx->cb_misc_state.atom.dirty = true;
+	}
+
+	/* Emit states. */
+	r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
 	r600_flush_emit(rctx);
 
 	for (i = 0; i < R600_NUM_ATOMS; i++) {
@@ -1253,10 +1314,6 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 		}
 		r600_emit_atom(rctx, rctx->atoms[i]);
 	}
-	LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
-		r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
-	}
-	rctx->pm4_dirty_cdwords = 0;
 
 	/* Update start instance. */
 	if (rctx->last_start_instance != info.start_instance) {
@@ -1275,7 +1332,8 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 			ls_mask = 2;
 
 		r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
-				       S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
+				       S_028A0C_AUTO_RESET_CNTL(ls_mask) |
+				       (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
 		r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
 				       r600_conv_prim_to_gs_out(info.mode));
 		r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
@@ -1293,19 +1351,28 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 					(VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
 					(VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
 
-		va = r600_resource_va(ctx->screen, ib.buffer);
-		va += ib.offset;
-		cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
-		cs->buf[cs->cdw++] = va;
-		cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
-		cs->buf[cs->cdw++] = info.count;
-		cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
-		cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
-		cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
+		if (ib.user_buffer) {
+			unsigned size_bytes = info.count*ib.index_size;
+			unsigned size_dw = align(size_bytes, 4) / 4;
+			cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
+			cs->buf[cs->cdw++] = info.count;
+			cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
+			memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
+			cs->cdw += size_dw;
+		} else {
+			uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
+			cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
+			cs->buf[cs->cdw++] = va;
+			cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
+			cs->buf[cs->cdw++] = info.count;
+			cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
+			cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
+			cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
+		}
 	} else {
 		if (info.count_from_stream_output) {
 			struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
-			uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
+			uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
 
 			r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
 
@@ -1317,7 +1384,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 			cs->buf[cs->cdw++] = 0; /* unused */
 
 			cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
-			cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
+			cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
 		}
 
 		cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
@@ -1326,6 +1393,10 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 					(info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
 	}
 
+	if (rctx->screen->trace_bo) {
+		r600_trace_emit(rctx);
+	}
+
 	/* Set the depth buffer as dirty. */
 	if (rctx->framebuffer.state.zsbuf) {
 		struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
@@ -1349,6 +1420,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 	}
 
 	pipe_resource_reference(&ib.buffer, NULL);
+	rctx->num_draw_calls++;
 }
 
 void r600_draw_rectangle(struct blitter_context *blitter,
@@ -1379,7 +1451,7 @@ void r600_draw_rectangle(struct blitter_context *blitter,
 	viewport.translate[1] = 0.0f;
 	viewport.translate[2] = 0.0f;
 	viewport.translate[3] = 0.0f;
-	rctx->context.set_viewport_state(&rctx->context, &viewport);
+	rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
 
 	/* Upload vertices. The hw rectangle has only 3 vertices,
 	 * I guess the 4th one is derived from the first 3.
@@ -1407,46 +1479,11 @@ void r600_draw_rectangle(struct blitter_context *blitter,
 	}
 
 	/* draw */
-	util_draw_vertex_buffer(&rctx->context, NULL, buf, offset,
+	util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
 				R600_PRIM_RECTANGLE_LIST, 3, 2);
 	pipe_resource_reference(&buf, NULL);
 }
 
-void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
-				 struct r600_pipe_state *state,
-				 uint32_t offset, uint32_t value,
-				 uint32_t range_id, uint32_t block_id,
-				 struct r600_resource *bo,
-				 enum radeon_bo_usage usage)
-			      
-{
-	struct r600_range *range;
-	struct r600_block *block;
-
-	if (bo) assert(usage);
-
-	range = &ctx->range[range_id];
-	block = range->blocks[block_id];
-	state->regs[state->nregs].block = block;
-	state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
-
-	state->regs[state->nregs].value = value;
-	state->regs[state->nregs].bo = bo;
-	state->regs[state->nregs].bo_usage = usage;
-
-	state->nregs++;
-	assert(state->nregs < R600_BLOCK_MAX_REG);
-}
-
-void _r600_pipe_state_add_reg(struct r600_context *ctx,
-			      struct r600_pipe_state *state,
-			      uint32_t offset, uint32_t value,
-			      uint32_t range_id, uint32_t block_id)
-{
-	_r600_pipe_state_add_reg_bo(ctx, state, offset, value,
-				    range_id, block_id, NULL, 0);
-}
-
 uint32_t r600_translate_stencil_op(int s_op)
 {
 	switch (s_op) {
@@ -1559,41 +1596,89 @@ unsigned r600_tex_compare(unsigned compare)
 	}
 }
 
+static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
+{
+	return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
+	       wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
+	       (linear_filter &&
+	        (wrap == PIPE_TEX_WRAP_CLAMP ||
+		 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
+}
+
+bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
+{
+	bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
+			     state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
+
+	return (state->border_color.ui[0] || state->border_color.ui[1] ||
+		state->border_color.ui[2] || state->border_color.ui[3]) &&
+	       (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
+		wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
+		wrap_mode_uses_border_color(state->wrap_r, linear_filter));
+}
+
+void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
+{
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+	struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader->current;
+
+	r600_emit_command_buffer(cs, &shader->command_buffer);
+
+	radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+	radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
+}
+
 /* keep this at the end of this file, please */
 void r600_init_common_state_functions(struct r600_context *rctx)
 {
-	rctx->context.create_fs_state = r600_create_ps_state;
-	rctx->context.create_vs_state = r600_create_vs_state;
-	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
-	rctx->context.bind_blend_state = r600_bind_blend_state;
-	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
-	rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
-	rctx->context.bind_fs_state = r600_bind_ps_state;
-	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
-	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
-	rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
-	rctx->context.bind_vs_state = r600_bind_vs_state;
-	rctx->context.delete_blend_state = r600_delete_blend_state;
-	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
-	rctx->context.delete_fs_state = r600_delete_ps_state;
-	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
-	rctx->context.delete_sampler_state = r600_delete_sampler_state;
-	rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
-	rctx->context.delete_vs_state = r600_delete_vs_state;
-	rctx->context.set_blend_color = r600_set_blend_color;
-	rctx->context.set_clip_state = r600_set_clip_state;
-	rctx->context.set_constant_buffer = r600_set_constant_buffer;
-	rctx->context.set_sample_mask = r600_set_sample_mask;
-	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
-	rctx->context.set_viewport_state = r600_set_viewport_state;
-	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
-	rctx->context.set_index_buffer = r600_set_index_buffer;
-	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
-	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
-	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
-	rctx->context.texture_barrier = r600_texture_barrier;
-	rctx->context.create_stream_output_target = r600_create_so_target;
-	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
-	rctx->context.set_stream_output_targets = r600_set_so_targets;
-	rctx->context.draw_vbo = r600_draw_vbo;
+	rctx->b.b.create_fs_state = r600_create_ps_state;
+	rctx->b.b.create_vs_state = r600_create_vs_state;
+	rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
+	rctx->b.b.bind_blend_state = r600_bind_blend_state;
+	rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
+	rctx->b.b.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
+	rctx->b.b.bind_fs_state = r600_bind_ps_state;
+	rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
+	rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
+	rctx->b.b.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
+	rctx->b.b.bind_vs_state = r600_bind_vs_state;
+	rctx->b.b.delete_blend_state = r600_delete_blend_state;
+	rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
+	rctx->b.b.delete_fs_state = r600_delete_ps_state;
+	rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
+	rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
+	rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
+	rctx->b.b.delete_vs_state = r600_delete_vs_state;
+	rctx->b.b.set_blend_color = r600_set_blend_color;
+	rctx->b.b.set_clip_state = r600_set_clip_state;
+	rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
+	rctx->b.b.set_sample_mask = r600_set_sample_mask;
+	rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
+	rctx->b.b.set_viewport_states = r600_set_viewport_states;
+	rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
+	rctx->b.b.set_index_buffer = r600_set_index_buffer;
+	rctx->b.b.set_fragment_sampler_views = r600_set_ps_sampler_views;
+	rctx->b.b.set_vertex_sampler_views = r600_set_vs_sampler_views;
+	rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
+	rctx->b.b.texture_barrier = r600_texture_barrier;
+	rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
+	rctx->b.b.draw_vbo = r600_draw_vbo;
+}
+
+void r600_trace_emit(struct r600_context *rctx)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+	uint64_t va;
+	uint32_t reloc;
+
+	va = r600_resource_va(&rscreen->b.b, (void*)rscreen->trace_bo);
+	reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
+	radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
+	radeon_emit(cs, va & 0xFFFFFFFFUL);
+	radeon_emit(cs, (va >> 32UL) & 0xFFUL);
+	radeon_emit(cs, cs->cdw);
+	radeon_emit(cs, rscreen->cs_count);
+	radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+	radeon_emit(cs, reloc);
 }