X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_state_common.c;h=6f888df6a301603c04adc868a66536363263b3c4;hb=507337864fa80caf9f26602324d2c28dd0a75d61;hp=3c93f4945bc85d84571ea0efd1da8515047cc77f;hpb=68bbfc1afe210d82acfb14a78b0fd8c436a8f78c;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 3c93f4945bc..6f888df6a30 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -28,7 +28,9 @@ #include "r600d.h" #include "util/u_blitter.h" +#include "util/u_upload_mgr.h" #include "tgsi/tgsi_parse.h" +#include static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom) { @@ -156,11 +158,10 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state) rstate = &blend->rstate; rctx->states[rstate->id] = rstate; rctx->cb_target_mask = blend->cb_target_mask; - /* Replace every bit except MULTIWRITE_ENABLE. */ rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE; rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE; - + rctx->dual_src_blend = blend->dual_src_blend; r600_context_pipe_state_set(rctx, rstate); } @@ -174,10 +175,10 @@ void r600_set_blend_color(struct pipe_context *ctx, return; rstate->id = R600_PIPE_STATE_BLEND_COLOR; - r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0); - r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0); - r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0); - r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0); + r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0])); + r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1])); + r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); + r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]); rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate; @@ -198,14 +199,12 @@ static void r600_set_stencil_ref(struct pipe_context *ctx, R_028430_DB_STENCILREFMASK, S_028430_STENCILREF(state->ref_value[0]) | S_028430_STENCILMASK(state->valuemask[0]) | - S_028430_STENCILWRITEMASK(state->writemask[0]), - NULL, 0); + S_028430_STENCILWRITEMASK(state->writemask[0])); r600_pipe_state_add_reg(rstate, R_028434_DB_STENCILREFMASK_BF, S_028434_STENCILREF_BF(state->ref_value[1]) | S_028434_STENCILMASK_BF(state->valuemask[1]) | - S_028434_STENCILWRITEMASK_BF(state->writemask[1]), - NULL, 0); + S_028434_STENCILWRITEMASK_BF(state->writemask[1])); free(rctx->states[R600_PIPE_STATE_STENCIL_REF]); rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate; @@ -359,8 +358,6 @@ void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) rctx->vertex_elements = v; if (v) { r600_inval_shader_cache(rctx); - u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state, - v->vmgr_elements); rctx->states[v->rstate.id] = &v->rstate; r600_context_pipe_state_set(rctx, &v->rstate); @@ -379,17 +376,20 @@ void r600_delete_vertex_element(struct pipe_context *ctx, void *state) rctx->vertex_elements = NULL; pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL); - u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements); FREE(state); } - void r600_set_index_buffer(struct pipe_context *ctx, const struct pipe_index_buffer *ib) { struct r600_context *rctx = (struct r600_context *)ctx; - u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib); + if (ib) { + pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); + memcpy(&rctx->index_buffer, ib, sizeof(*ib)); + } else { + pipe_resource_reference(&rctx->index_buffer.buffer, NULL); + } } void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, @@ -397,8 +397,12 @@ void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, { struct r600_context *rctx = (struct r600_context *)ctx; - u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers); - rctx->vertex_buffers_dirty = true; + util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count); + + r600_inval_vertex_cache(rctx); + rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) * + rctx->nr_vertex_buffers; + r600_atom_dirty(rctx, &rctx->vertex_buffer_state); } void *r600_create_vertex_elements(struct pipe_context *ctx, @@ -413,9 +417,7 @@ void *r600_create_vertex_elements(struct pipe_context *ctx, return NULL; v->count = count; - v->vmgr_elements = - u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count, - elements, v->elements); + memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); if (r600_vertex_elements_build_fetch_shader(rctx, v)) { FREE(v); @@ -513,7 +515,7 @@ static void r600_update_alpha_ref(struct r600_context *rctx) rstate.nregs = 0; if (rctx->export_16bpc) alpha_ref &= ~0x1FFF; - r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0); + r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref); r600_context_pipe_state_set(rctx, &rstate); rctx->alpha_ref_dirty = false; @@ -521,19 +523,19 @@ static void r600_update_alpha_ref(struct r600_context *rctx) void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state) { + r600_inval_shader_cache(rctx); state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20 : util_bitcount(state->dirty_mask)*19; r600_atom_dirty(rctx, &state->atom); } void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, - struct pipe_resource *buffer) + struct pipe_constant_buffer *input) { struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_resource *rbuffer = r600_resource(buffer); struct r600_constbuf_state *state; - struct r600_constant_buffer *cb; - uint32_t offset; + struct pipe_constant_buffer *cb; + uint8_t *ptr; switch (shader) { case PIPE_SHADER_VERTEX: @@ -549,27 +551,47 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, /* Note that the state tracker can unbind constant buffers by * passing NULL here. */ - if (buffer == NULL) { + if (unlikely(!input)) { state->enabled_mask &= ~(1 << index); state->dirty_mask &= ~(1 << index); pipe_resource_reference(&state->cb[index].buffer, NULL); return; } - r600_inval_shader_cache(rctx); - r600_upload_const_buffer(rctx, &rbuffer, &offset); - cb = &state->cb[index]; - pipe_resource_reference(&cb->buffer, &rbuffer->b.b.b); - cb->buffer_offset = offset; - cb->buffer_size = buffer->width0; + cb->buffer_size = input->buffer_size; + + ptr = input->buffer->user_ptr; + + if (ptr) { + /* Upload the user buffer. */ + if (R600_BIG_ENDIAN) { + uint32_t *tmpPtr; + unsigned i, size = input->buffer_size; + + if (!(tmpPtr = malloc(size))) { + R600_ERR("Failed to allocate BE swap buffer.\n"); + return; + } + + for (i = 0; i < size / 4; ++i) { + tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]); + } + + u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer); + free(tmpPtr); + } else { + u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer); + } + } else { + /* Setup the hw buffer. */ + cb->buffer_offset = input->buffer_offset; + pipe_resource_reference(&cb->buffer, input->buffer); + } state->enabled_mask |= 1 << index; state->dirty_mask |= 1 << index; r600_constant_buffers_dirty(rctx, state); - - if (buffer != &rbuffer->b.b.b) - pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL); } struct pipe_stream_output_target * @@ -595,9 +617,9 @@ r600_create_so_target(struct pipe_context *ctx, t->filled_size = (struct r600_resource*) pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4); - ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE); + ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE); memset(ptr, 0, t->filled_size->buf->size); - rctx->ws->buffer_unmap(t->filled_size->buf); + rctx->ws->buffer_unmap(t->filled_size->cs_buf); return &t->b; } @@ -687,6 +709,10 @@ static void r600_update_derived_state(struct r600_context *rctx) r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate); } + if (rctx->dual_src_blend) + rctx->cb_shader_mask = rctx->ps_shader->ps_cb_shader_mask | rctx->fb_cb_shader_mask; + else + rctx->cb_shader_mask = rctx->fb_cb_shader_mask; } static unsigned r600_conv_prim_to_gs_out(unsigned mode) @@ -722,9 +748,10 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) struct r600_atom *state = NULL, *next_state = NULL; struct radeon_winsys_cs *cs = rctx->cs; uint64_t va; + uint8_t *ptr; if ((!info.count && (info.indexed || !info.count_from_stream_output)) || - (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) || + (info.indexed && !rctx->index_buffer.buffer) || !r600_conv_pipe_prim(info.mode, &prim)) { assert(0); return; @@ -737,27 +764,19 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) r600_update_derived_state(rctx); - /* Update vertex buffers. */ - if ((u_vbuf_draw_begin(rctx->vbuf_mgr, &info) & U_VBUF_BUFFERS_UPDATED) || - rctx->vertex_buffers_dirty) { - r600_inval_vertex_cache(rctx); - rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) * - rctx->vbuf_mgr->nr_real_vertex_buffers; - r600_atom_dirty(rctx, &rctx->vertex_buffer_state); - rctx->vertex_buffers_dirty = FALSE; - } - if (info.indexed) { /* Initialize the index buffer struct. */ - pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer); - ib.index_size = rctx->vbuf_mgr->index_buffer.index_size; - ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size; + pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer); + ib.index_size = rctx->index_buffer.index_size; + ib.offset = rctx->index_buffer.offset + info.start * ib.index_size; /* Translate or upload, if needed. */ r600_translate_index_buffer(rctx, &ib, info.count); - if (u_vbuf_resource(ib.buffer)->user_ptr) { - r600_upload_index_buffer(rctx, &ib, info.count); + ptr = ib.buffer->user_ptr; + if (ptr) { + u_upload_data(rctx->uploader, 0, info.count * ib.index_size, + ptr, &ib.offset, &ib.buffer); } } else { info.index_bias = info.start; @@ -771,24 +790,31 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) if (rctx->vgt.id != R600_PIPE_STATE_VGT) { rctx->vgt.id = R600_PIPE_STATE_VGT; rctx->vgt.nregs = 0; - r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim); + r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask); + r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias); + r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index); + r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart); + r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance); + r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0); if (rctx->chip_class <= R700) - r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control); + r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0); + + if (rctx->chip_class <= R700) + r600_pipe_state_add_reg(&rctx->vgt, R_0280A4_CB_COLOR1_INFO, 0); + else + r600_pipe_state_add_reg(&rctx->vgt, 0x28CAC, 0); } rctx->vgt.nregs = 0; r600_pipe_state_mod_reg(&rctx->vgt, prim); r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode)); r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask); + r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask); r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias); r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index); r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart); @@ -810,6 +836,11 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) rctx->vs_shader->shader.vs_prohibit_ucps ? 0 : rctx->rasterizer->clip_plane_enable & 0x3F)); + if (rctx->dual_src_blend) { + r600_pipe_state_mod_reg(&rctx->vgt, + rctx->color0_format); + } + r600_context_pipe_state_set(rctx, &rctx->vgt); /* Emit states (the function expects that we emit at most 17 dwords here). */ @@ -865,15 +896,15 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) } pipe_resource_reference(&ib.buffer, NULL); - u_vbuf_draw_end(rctx->vbuf_mgr); } -void _r600_pipe_state_add_reg(struct r600_context *ctx, - struct r600_pipe_state *state, - uint32_t offset, uint32_t value, - uint32_t range_id, uint32_t block_id, - struct r600_resource *bo, - enum radeon_bo_usage usage) +void _r600_pipe_state_add_reg_bo(struct r600_context *ctx, + struct r600_pipe_state *state, + uint32_t offset, uint32_t value, + uint32_t range_id, uint32_t block_id, + struct r600_resource *bo, + enum radeon_bo_usage usage) + { struct r600_range *range; struct r600_block *block; @@ -893,6 +924,15 @@ void _r600_pipe_state_add_reg(struct r600_context *ctx, assert(state->nregs < R600_BLOCK_MAX_REG); } +void _r600_pipe_state_add_reg(struct r600_context *ctx, + struct r600_pipe_state *state, + uint32_t offset, uint32_t value, + uint32_t range_id, uint32_t block_id) +{ + _r600_pipe_state_add_reg_bo(ctx, state, offset, value, + range_id, block_id, NULL, 0); +} + void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, uint32_t offset, uint32_t value, struct r600_resource *bo,