X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_texture.c;h=36cca17eb110ae0be0f6d4fbfcfa951f9f0a9165;hb=033eec4145df132b961b8e5c83e222424859db4d;hp=507dc16752be8a84a3d00bea9cf5dd34d72f9234;hpb=e6dfc8c77bc00c06a35270a4e50aa52c738c8629;p=mesa.git

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 507dc16752b..36cca17eb11 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -25,50 +25,113 @@
  *      Corbin Simpson
  */
 #include "r600_formats.h"
+#include "evergreen_compute.h"
 #include "r600d.h"
 
 #include <errno.h>
 #include "util/u_format_s3tc.h"
 #include "util/u_memory.h"
 
+
+/* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
+static void r600_copy_region_with_blit(struct pipe_context *pipe,
+				       struct pipe_resource *dst,
+                                       unsigned dst_level,
+                                       unsigned dstx, unsigned dsty, unsigned dstz,
+                                       struct pipe_resource *src,
+                                       unsigned src_level,
+                                       const struct pipe_box *src_box)
+{
+	struct pipe_blit_info blit;
+
+	memset(&blit, 0, sizeof(blit));
+	blit.src.resource = src;
+	blit.src.format = src->format;
+	blit.src.level = src_level;
+	blit.src.box = *src_box;
+	blit.dst.resource = dst;
+	blit.dst.format = dst->format;
+	blit.dst.level = dst_level;
+	blit.dst.box.x = dstx;
+	blit.dst.box.y = dsty;
+	blit.dst.box.z = dstz;
+	blit.dst.box.width = src_box->width;
+	blit.dst.box.height = src_box->height;
+	blit.dst.box.depth = src_box->depth;
+	blit.mask = util_format_get_mask(src->format) &
+		    util_format_get_mask(dst->format);
+	blit.filter = PIPE_TEX_FILTER_NEAREST;
+
+	if (blit.mask) {
+		pipe->blit(pipe, &blit);
+	}
+}
+
 /* Copy from a full GPU texture to a transfer's staging one. */
 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
 {
+	struct r600_context *rctx = (struct r600_context*)ctx;
 	struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
-	struct pipe_resource *texture = transfer->resource;
+	struct pipe_resource *dst = &rtransfer->staging->b.b;
+	struct pipe_resource *src = transfer->resource;
 
-	ctx->resource_copy_region(ctx, &rtransfer->staging->b.b,
-				0, 0, 0, 0, texture, transfer->level,
-				&transfer->box);
-}
+	if (src->nr_samples > 1) {
+		r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
+					   src, transfer->level, &transfer->box);
+		return;
+	}
 
+	if (!rctx->screen->dma_blit(ctx, dst, 0, 0, 0, 0,
+				    src, transfer->level,
+				    &transfer->box)) {
+		ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
+					  src, transfer->level, &transfer->box);
+	}
+}
 
 /* Copy from a transfer's staging texture to a full GPU one. */
 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
 {
+	struct r600_context *rctx = (struct r600_context*)ctx;
 	struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
-	struct pipe_resource *texture = transfer->resource;
+	struct pipe_resource *dst = transfer->resource;
+	struct pipe_resource *src = &rtransfer->staging->b.b;
 	struct pipe_box sbox;
 
-	u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox);
+	u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
 
-	ctx->resource_copy_region(ctx, texture, transfer->level,
-				  transfer->box.x, transfer->box.y, transfer->box.z,
-				  &rtransfer->staging->b.b,
-				  0, &sbox);
+	if (dst->nr_samples > 1) {
+		r600_copy_region_with_blit(ctx, dst, transfer->level,
+					   transfer->box.x, transfer->box.y, transfer->box.z,
+					   src, 0, &sbox);
+		return;
+	}
+
+	if (!rctx->screen->dma_blit(ctx, dst, transfer->level,
+				    transfer->box.x, transfer->box.y, transfer->box.z,
+				    src, 0, &sbox)) {
+		ctx->resource_copy_region(ctx, dst, transfer->level,
+					  transfer->box.x, transfer->box.y, transfer->box.z,
+					  src, 0, &sbox);
+	}
 }
 
-unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
-					unsigned level, unsigned layer)
+static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
+					const struct pipe_box *box)
 {
-	return rtex->offset[level] + layer * rtex->layer_size[level];
+	enum pipe_format format = rtex->resource.b.b.format;
+
+	return rtex->surface.level[level].offset +
+	       box->z * rtex->surface.level[level].slice_size +
+	       box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
+	       box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 }
 
 static int r600_init_surface(struct r600_screen *rscreen,
 			     struct radeon_surface *surface,
 			     const struct pipe_resource *ptex,
 			     unsigned array_mode,
-			     bool is_transfer, bool is_flushed_depth)
+			     bool is_flushed_depth)
 {
 	const struct util_format_description *desc =
 		util_format_description(ptex->format);
@@ -86,8 +149,7 @@ static int r600_init_surface(struct r600_screen *rscreen,
 	surface->array_size = 1;
 	surface->last_level = ptex->last_level;
 
-	if (rscreen->chip_class >= EVERGREEN &&
-	    !is_transfer && !is_flushed_depth &&
+	if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
 	    ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
 		surface->bpe = 4; /* stencil is allocated separately on evergreen */
 	} else {
@@ -98,8 +160,9 @@ static int r600_init_surface(struct r600_screen *rscreen,
 		}
 	}
 
-	surface->nsamples = 1;
+	surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
 	surface->flags = 0;
+
 	switch (array_mode) {
 	case V_038000_ARRAY_1D_TILED_THIN1:
 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
@@ -131,6 +194,7 @@ static int r600_init_surface(struct r600_screen *rscreen,
 		surface->array_size = ptex->array_size;
 		break;
 	case PIPE_TEXTURE_2D_ARRAY:
+	case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d layout for now */
 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
 		surface->array_size = ptex->array_size;
 		break;
@@ -145,19 +209,19 @@ static int r600_init_surface(struct r600_screen *rscreen,
 		surface->flags |= RADEON_SURF_SCANOUT;
 	}
 
-	if (!is_transfer && !is_flushed_depth && is_depth) {
+	if (!is_flushed_depth && is_depth) {
 		surface->flags |= RADEON_SURF_ZBUFFER;
 
 		if (is_stencil) {
-			surface->flags |= RADEON_SURF_SBUFFER;
+			surface->flags |= RADEON_SURF_SBUFFER |
+                                          RADEON_SURF_HAS_SBUFFER_MIPTREE;
 		}
 	}
 	return 0;
 }
 
 static int r600_setup_surface(struct pipe_screen *screen,
-			      struct r600_resource_texture *rtex,
-			      unsigned array_mode,
+			      struct r600_texture *rtex,
 			      unsigned pitch_in_bytes_override)
 {
 	struct pipe_resource *ptex = &rtex->resource.b.b;
@@ -178,13 +242,11 @@ static int r600_setup_surface(struct pipe_screen *screen,
 		rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
 		rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
 		if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
-			rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
+			rtex->surface.stencil_offset =
+			rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
 		}
 	}
 	for (i = 0; i <= ptex->last_level; i++) {
-		rtex->offset[i] = rtex->surface.level[i].offset;
-		rtex->layer_size[i] = rtex->surface.level[i].slice_size;
-		rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
 		switch (rtex->surface.level[i].mode) {
 		case RADEON_SURF_MODE_LINEAR_ALIGNED:
 			rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
@@ -208,7 +270,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 					struct pipe_resource *ptex,
 					struct winsys_handle *whandle)
 {
-	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+	struct r600_texture *rtex = (struct r600_texture*)ptex;
 	struct r600_resource *resource = &rtex->resource;
 	struct radeon_surface *surface = &rtex->surface;
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
@@ -223,53 +285,165 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 				       surface->tile_split,
 				       surface->stencil_tile_split,
 				       surface->mtilea,
-				       rtex->pitch_in_bytes[0]);
+				       rtex->surface.level[0].pitch_bytes);
 
 	return rscreen->ws->buffer_get_handle(resource->buf,
-					      rtex->pitch_in_bytes[0], whandle);
+					      rtex->surface.level[0].pitch_bytes, whandle);
 }
 
 static void r600_texture_destroy(struct pipe_screen *screen,
 				 struct pipe_resource *ptex)
 {
-	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+	struct r600_texture *rtex = (struct r600_texture*)ptex;
 	struct r600_resource *resource = &rtex->resource;
 
 	if (rtex->flushed_depth_texture)
 		pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 
+        pipe_resource_reference((struct pipe_resource**)&rtex->htile, NULL);
 	pb_reference(&resource->buf, NULL);
 	FREE(rtex);
 }
 
-static const struct u_resource_vtbl r600_texture_vtbl =
+static const struct u_resource_vtbl r600_texture_vtbl;
+
+/* The number of samples can be specified independently of the texture. */
+void r600_texture_get_fmask_info(struct r600_screen *rscreen,
+				 struct r600_texture *rtex,
+				 unsigned nr_samples,
+				 struct r600_fmask_info *out)
 {
-	r600_texture_get_handle,	/* get_handle */
-	r600_texture_destroy,		/* resource_destroy */
-	r600_texture_get_transfer,	/* get_transfer */
-	r600_texture_transfer_destroy,	/* transfer_destroy */
-	r600_texture_transfer_map,	/* transfer_map */
-	NULL,				/* transfer_flush_region */
-	r600_texture_transfer_unmap,	/* transfer_unmap */
-	NULL				/* transfer_inline_write */
-};
+	/* FMASK is allocated like an ordinary texture. */
+	struct radeon_surface fmask = rtex->surface;
+
+	memset(out, 0, sizeof(*out));
+
+	fmask.bo_alignment = 0;
+	fmask.bo_size = 0;
+	fmask.nsamples = 1;
+	fmask.flags |= RADEON_SURF_FMASK;
+
+	switch (nr_samples) {
+	case 2:
+	case 4:
+		fmask.bpe = 1;
+		fmask.bankh = 4;
+		break;
+	case 8:
+		fmask.bpe = 4;
+		break;
+	default:
+		R600_ERR("Invalid sample count for FMASK allocation.\n");
+		return;
+	}
+
+	/* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
+	 * This can be fixed by writing a separate FMASK allocator specifically
+	 * for R600-R700 asics. */
+	if (rscreen->chip_class <= R700) {
+		fmask.bpe *= 2;
+	}
+
+	if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
+		R600_ERR("Got error in surface_init while allocating FMASK.\n");
+		return;
+	}
+
+	assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
+
+	out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
+	if (out->slice_tile_max)
+		out->slice_tile_max -= 1;
+
+	out->bank_height = fmask.bankh;
+	out->alignment = MAX2(256, fmask.bo_alignment);
+	out->size = fmask.bo_size;
+}
+
+static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
+					struct r600_texture *rtex)
+{
+	struct r600_fmask_info fmask;
+
+	r600_texture_get_fmask_info(rscreen, rtex,
+				    rtex->resource.b.b.nr_samples, &fmask);
+
+	rtex->fmask_bank_height = fmask.bank_height;
+	rtex->fmask_slice_tile_max = fmask.slice_tile_max;
+	rtex->fmask_offset = align(rtex->size, fmask.alignment);
+	rtex->fmask_size = fmask.size;
+	rtex->size = rtex->fmask_offset + rtex->fmask_size;
+#if 0
+	printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
+	       fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
+#endif
+}
+
+void r600_texture_get_cmask_info(struct r600_screen *rscreen,
+				 struct r600_texture *rtex,
+				 struct r600_cmask_info *out)
+{
+	unsigned cmask_tile_width = 8;
+	unsigned cmask_tile_height = 8;
+	unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
+	unsigned element_bits = 4;
+	unsigned cmask_cache_bits = 1024;
+	unsigned num_pipes = rscreen->tiling_info.num_channels;
+	unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+
+	unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
+	unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
+	unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
+	unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
+	unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
+
+	unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
+	unsigned height = align(rtex->surface.npix_y, macro_tile_height);
+
+	unsigned base_align = num_pipes * pipe_interleave_bytes;
+	unsigned slice_bytes =
+		((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
+
+	assert(macro_tile_width % 128 == 0);
+	assert(macro_tile_height % 128 == 0);
+
+	out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
+	out->alignment = MAX2(256, base_align);
+	out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+}
+
+static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
+					struct r600_texture *rtex)
+{
+	struct r600_cmask_info cmask;
 
-static struct r600_resource_texture *
+	r600_texture_get_cmask_info(rscreen, rtex, &cmask);
+
+	rtex->cmask_slice_tile_max = cmask.slice_tile_max;
+	rtex->cmask_offset = align(rtex->size, cmask.alignment);
+	rtex->cmask_size = cmask.size;
+	rtex->size = rtex->cmask_offset + rtex->cmask_size;
+#if 0
+	printf("CMASK: macro tile width = %u, macro tile height = %u, "
+	       "pitch elements = %u, height = %u, slice tile max = %u\n",
+	       macro_tile_width, macro_tile_height, pitch_elements, height,
+	       rtex->cmask_slice_tile_max);
+#endif
+}
+
+static struct r600_texture *
 r600_texture_create_object(struct pipe_screen *screen,
 			   const struct pipe_resource *base,
-			   unsigned array_mode,
 			   unsigned pitch_in_bytes_override,
-			   unsigned max_buffer_size,
 			   struct pb_buffer *buf,
-			   boolean alloc_bo,
 			   struct radeon_surface *surface)
 {
-	struct r600_resource_texture *rtex;
+	struct r600_texture *rtex;
 	struct r600_resource *resource;
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
 	int r;
 
-	rtex = CALLOC_STRUCT(r600_resource_texture);
+	rtex = CALLOC_STRUCT(r600_texture);
 	if (rtex == NULL)
 		return NULL;
 
@@ -279,31 +453,142 @@ r600_texture_create_object(struct pipe_screen *screen,
 	pipe_reference_init(&resource->b.b.reference, 1);
 	resource->b.b.screen = screen;
 	rtex->pitch_override = pitch_in_bytes_override;
-	rtex->real_format = base->format;
 
 	/* don't include stencil-only formats which we don't support for rendering */
 	rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
 
 	rtex->surface = *surface;
-	r = r600_setup_surface(screen, rtex, array_mode,
+	r = r600_setup_surface(screen, rtex,
 			       pitch_in_bytes_override);
 	if (r) {
 		FREE(rtex);
 		return NULL;
 	}
 
+	if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
+		r600_texture_allocate_fmask(rscreen, rtex);
+		r600_texture_allocate_cmask(rscreen, rtex);
+	}
+
+	if (!rtex->is_depth && base->nr_samples > 1 &&
+	    (!rtex->fmask_size || !rtex->cmask_size)) {
+		FREE(rtex);
+		return NULL;
+	}
+
+	/* Tiled depth textures utilize the non-displayable tile order. */
+	rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
+
+	/* only enable hyperz for PIPE_TEXTURE_2D not for PIPE_TEXTURE_2D_ARRAY
+	 * Thought it might still be interessting to use hyperz for texture
+	 * array without using fast clear features
+	 */
+	rtex->htile = NULL;
+	if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
+	    util_format_is_depth_or_stencil(base->format) &&
+	    rscreen->info.drm_minor >= 26 &&
+	    !(rscreen->debug_flags & DBG_NO_HYPERZ) &&
+	    base->target == PIPE_TEXTURE_2D &&
+	    rtex->surface.level[0].nblk_x >= 32 &&
+	    rtex->surface.level[0].nblk_y >= 32) {
+		unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
+		unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
+		unsigned htile_size;
+		unsigned npipes = rscreen->info.r600_num_tile_pipes;
+
+		/* this alignment and htile size only apply to linear htile buffer */
+		sw = align(sw, 16 << 3);
+		sh = align(sh, npipes << 3);
+		htile_size = (sw >> 3) * (sh >> 3) * 4;
+		/* must be aligned with 2K * npipes */
+		htile_size = align(htile_size, (2 << 10) * npipes);
+
+		rtex->htile = (struct r600_resource*)pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
+									PIPE_USAGE_STATIC, htile_size);
+		if (rtex->htile == NULL) {
+			/* this is not a fatal error as we can still keep rendering
+			 * without htile buffer
+			 */
+			R600_ERR("r600: failed to create bo for htile buffers\n");
+		} else {
+			r600_screen_clear_buffer(rscreen, &rtex->htile->b.b, 0, htile_size, 0);
+		}
+	}
+
 	/* Now create the backing buffer. */
-	if (!buf && alloc_bo) {
+	if (!buf) {
 		unsigned base_align = rtex->surface.bo_alignment;
+		unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
 
-		if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
+		if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
 			FREE(rtex);
 			return NULL;
 		}
-	} else if (buf) {
+	} else {
+		/* This is usually the window framebuffer. We want it in VRAM, always. */
 		resource->buf = buf;
 		resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
-		resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
+		resource->domains = RADEON_DOMAIN_VRAM;
+	}
+
+	if (rtex->cmask_size) {
+		/* Initialize the cmask to 0xCC (= compressed state). */
+		r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
+					 rtex->cmask_offset, rtex->cmask_size, 0xCC);
+	}
+
+	if (rscreen->debug_flags & DBG_VM) {
+		fprintf(stderr, "VM start=0x%llX  end=0x%llX | Texture %ix%ix%i, %i levels, %i samples, %s\n",
+			r600_resource_va(screen, &rtex->resource.b.b),
+			r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
+			base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
+			base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
+	}
+
+	if (rscreen->debug_flags & DBG_TEX_DEPTH && rtex->is_depth && rtex->non_disp_tiling) {
+		printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
+		       "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
+		       "bpe=%u, nsamples=%u, flags=%u\n",
+		       rtex->surface.npix_x, rtex->surface.npix_y,
+		       rtex->surface.npix_z, rtex->surface.blk_w,
+		       rtex->surface.blk_h, rtex->surface.blk_d,
+		       rtex->surface.array_size, rtex->surface.last_level,
+		       rtex->surface.bpe, rtex->surface.nsamples,
+		       rtex->surface.flags);
+		if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
+			for (int i = 0; i <= rtex->surface.last_level; i++) {
+				printf("  Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
+				       "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
+				       "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+				       i, (unsigned long long)rtex->surface.level[i].offset,
+				       (unsigned long long)rtex->surface.level[i].slice_size,
+				       u_minify(rtex->resource.b.b.width0, i),
+				       u_minify(rtex->resource.b.b.height0, i),
+				       u_minify(rtex->resource.b.b.depth0, i),
+				       rtex->surface.level[i].nblk_x,
+				       rtex->surface.level[i].nblk_y,
+				       rtex->surface.level[i].nblk_z,
+				       rtex->surface.level[i].pitch_bytes,
+				       rtex->surface.level[i].mode);
+			}
+		}
+		if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+			for (int i = 0; i <= rtex->surface.last_level; i++) {
+				printf("  S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
+				       "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
+				       "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+				       i, (unsigned long long)rtex->surface.stencil_level[i].offset,
+				       (unsigned long long)rtex->surface.stencil_level[i].slice_size,
+                                       u_minify(rtex->resource.b.b.width0, i),
+				       u_minify(rtex->resource.b.b.height0, i),
+				       u_minify(rtex->resource.b.b.depth0, i),
+				       rtex->surface.stencil_level[i].nblk_x,
+				       rtex->surface.stencil_level[i].nblk_y,
+				       rtex->surface.stencil_level[i].nblk_z,
+				       rtex->surface.stencil_level[i].pitch_bytes,
+				       rtex->surface.stencil_level[i].mode);
+			}
+		}
 	}
 	return rtex;
 }
@@ -313,13 +598,26 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 {
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
 	struct radeon_surface surface;
-	unsigned array_mode = 0;
+	const struct util_format_description *desc = util_format_description(templ->format);
+	unsigned array_mode;
 	int r;
 
-	if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
-		if (!(templ->bind & PIPE_BIND_SCANOUT) &&
-		    templ->usage != PIPE_USAGE_STAGING &&
-		    templ->usage != PIPE_USAGE_STREAM) {
+	/* Default tiling mode for staging textures. */
+	array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
+
+	/* Tiling doesn't work with the 422 (SUBSAMPLED) formats. That's not an issue,
+	 * because 422 formats are used for videos, which prefer linear buffers
+	 * for fast uploads anyway. */
+	if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
+	    desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
+		if (templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) {
+			array_mode = V_038000_ARRAY_2D_TILED_THIN1;
+		} else if (!(templ->bind & PIPE_BIND_SCANOUT) &&
+			   templ->usage != PIPE_USAGE_STAGING &&
+			   templ->usage != PIPE_USAGE_STREAM &&
+			   templ->target != PIPE_TEXTURE_1D &&
+			   templ->target != PIPE_TEXTURE_1D_ARRAY &&
+			   templ->height0 > 3) {
 			array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 		} else if (util_format_is_compressed(templ->format)) {
 			array_mode = V_038000_ARRAY_1D_TILED_THIN1;
@@ -327,7 +625,6 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 	}
 
 	r = r600_init_surface(rscreen, &surface, templ, array_mode,
-			      templ->flags & R600_RESOURCE_FLAG_TRANSFER,
 			      templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
 	if (r) {
 		return NULL;
@@ -336,17 +633,19 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 	if (r) {
 		return NULL;
 	}
-	return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
-								  0, 0, NULL, TRUE, &surface);
+	return (struct pipe_resource *)r600_texture_create_object(screen, templ,
+								  0, NULL, &surface);
 }
 
-static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
+struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 						struct pipe_resource *texture,
-						const struct pipe_surface *templ)
+						const struct pipe_surface *templ,
+						unsigned width, unsigned height)
 {
 	struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
-	unsigned level = templ->u.tex.level;
 
+        assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
+        assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
 	assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
 	if (surface == NULL)
 		return NULL;
@@ -354,16 +653,29 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 	pipe_resource_reference(&surface->base.texture, texture);
 	surface->base.context = pipe;
 	surface->base.format = templ->format;
-	surface->base.width = u_minify(texture->width0, level);
-	surface->base.height = u_minify(texture->height0, level);
-	surface->base.usage = templ->usage;
+	surface->base.width = width;
+	surface->base.height = height;
 	surface->base.u = templ->u;
 	return &surface->base;
 }
 
+static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
+						struct pipe_resource *tex,
+						const struct pipe_surface *templ)
+{
+	unsigned level = templ->u.tex.level;
+
+	return r600_create_surface_custom(pipe, tex, templ,
+                                          u_minify(tex->width0, level),
+					  u_minify(tex->height0, level));
+}
+
 static void r600_surface_destroy(struct pipe_context *pipe,
 				 struct pipe_surface *surface)
 {
+	struct r600_surface *surf = (struct r600_surface*)surface;
+	pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
+	pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
 	pipe_resource_reference(&surface->texture, NULL);
 	FREE(surface);
 }
@@ -400,23 +712,23 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 	else if (micro == RADEON_LAYOUT_TILED)
 		array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
 	else
-		array_mode = 0;
+		array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
 
-	r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
+	r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
 	if (r) {
 		return NULL;
 	}
-	return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
-								  stride, 0, buf, FALSE, &surface);
+	return (struct pipe_resource *)r600_texture_create_object(screen, templ,
+								  stride, buf, &surface);
 }
 
 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 				     struct pipe_resource *texture,
-				     struct r600_resource_texture **staging)
+				     struct r600_texture **staging)
 {
-	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+	struct r600_texture *rtex = (struct r600_texture*)texture;
 	struct pipe_resource resource;
-	struct r600_resource_texture **flushed_depth_texture = staging ?
+	struct r600_texture **flushed_depth_texture = staging ?
 			staging : &rtex->flushed_depth_texture;
 
 	if (!staging && rtex->flushed_depth_texture)
@@ -430,41 +742,80 @@ bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 	resource.array_size = texture->array_size;
 	resource.last_level = texture->last_level;
 	resource.nr_samples = texture->nr_samples;
-	resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT;
+	resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
 	resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
 	resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
 
 	if (staging)
 		resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
 
-	*flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
+	*flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 	if (*flushed_depth_texture == NULL) {
 		R600_ERR("failed to create temporary texture to hold flushed depth\n");
 		return false;
 	}
 
 	(*flushed_depth_texture)->is_flushing_texture = TRUE;
+	(*flushed_depth_texture)->non_disp_tiling = false;
 	return true;
 }
 
-/* Needs adjustment for pixelformat:
+/**
+ * Initialize the pipe_resource descriptor to be of the same size as the box,
+ * which is supposed to hold a subregion of the texture "orig" at the given
+ * mipmap level.
  */
-static INLINE unsigned u_box_volume( const struct pipe_box *box )
+static void r600_init_temp_resource_from_box(struct pipe_resource *res,
+					     struct pipe_resource *orig,
+					     const struct pipe_box *box,
+					     unsigned level, unsigned flags)
 {
-	return box->width * box->depth * box->height;
+	memset(res, 0, sizeof(*res));
+	res->format = orig->format;
+	res->width0 = box->width;
+	res->height0 = box->height;
+	res->depth0 = 1;
+	res->array_size = 1;
+	res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
+	res->flags = flags;
+
+	/* We must set the correct texture target and dimensions for a 3D box. */
+	if (box->depth > 1 && util_max_layer(orig, level) > 0)
+		res->target = orig->target;
+	else
+		res->target = PIPE_TEXTURE_2D;
+
+	switch (res->target) {
+	case PIPE_TEXTURE_1D_ARRAY:
+	case PIPE_TEXTURE_2D_ARRAY:
+	case PIPE_TEXTURE_CUBE_ARRAY:
+		res->array_size = box->depth;
+		break;
+	case PIPE_TEXTURE_3D:
+		res->depth0 = box->depth;
+		break;
+	default:;
+	}
 }
 
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
-						struct pipe_resource *texture,
-						unsigned level,
-						unsigned usage,
-						const struct pipe_box *box)
+static void *r600_texture_transfer_map(struct pipe_context *ctx,
+				       struct pipe_resource *texture,
+				       unsigned level,
+				       unsigned usage,
+				       const struct pipe_box *box,
+				       struct pipe_transfer **ptransfer)
 {
 	struct r600_context *rctx = (struct r600_context*)ctx;
-	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
-	struct pipe_resource resource;
+	struct r600_texture *rtex = (struct r600_texture*)texture;
 	struct r600_transfer *trans;
 	boolean use_staging_texture = FALSE;
+	struct r600_resource *buf;
+	unsigned offset = 0;
+	char *map;
+
+	if ((texture->bind & PIPE_BIND_GLOBAL) && texture->target == PIPE_BUFFER) {
+		return r600_compute_global_transfer_map(ctx, texture, level, usage, box, ptransfer);
+	}
 
 	/* We cannot map a tiled texture directly because the data is
 	 * in a different order, therefore we do detiling using a blit.
@@ -477,12 +828,9 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 		use_staging_texture = TRUE;
 	}
 
-	if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
-		use_staging_texture = TRUE;
-
 	/* Use a staging texture for uploads if the underlying BO is busy. */
 	if (!(usage & PIPE_TRANSFER_READ) &&
-	    (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
+	    (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
 	     rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
 		use_staging_texture = TRUE;
 	}
@@ -498,143 +846,115 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	trans = CALLOC_STRUCT(r600_transfer);
 	if (trans == NULL)
 		return NULL;
-	pipe_resource_reference(&trans->transfer.resource, texture);
+	trans->transfer.resource = texture;
 	trans->transfer.level = level;
 	trans->transfer.usage = usage;
 	trans->transfer.box = *box;
+
 	if (rtex->is_depth) {
-		/* XXX: only readback the rectangle which is being mapped?
-		*/
-		/* XXX: when discard is true, no need to read back from depth texture
-		*/
-		struct r600_resource_texture *staging_depth;
+		struct r600_texture *staging_depth;
+
+		if (rtex->resource.b.b.nr_samples > 1) {
+			/* MSAA depth buffers need to be converted to single sample buffers.
+			 *
+			 * Mapping MSAA depth buffers can occur if ReadPixels is called
+			 * with a multisample GLX visual.
+			 *
+			 * First downsample the depth buffer to a temporary texture,
+			 * then decompress the temporary one to staging.
+			 *
+			 * Only the region being mapped is transfered.
+			 */
+			struct pipe_resource resource;
+
+			r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
+
+			if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
+				R600_ERR("failed to create temporary texture to hold untiled copy\n");
+				FREE(trans);
+				return NULL;
+			}
 
-		if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
-			R600_ERR("failed to create temporary texture to hold untiled copy\n");
-			pipe_resource_reference(&trans->transfer.resource, NULL);
-			FREE(trans);
-			return NULL;
+			if (usage & PIPE_TRANSFER_READ) {
+				struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
+
+				r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
+				r600_blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
+							   0, 0, 0, box->depth, 0, 0);
+				pipe_resource_reference((struct pipe_resource**)&temp, NULL);
+			}
 		}
+		else {
+			/* XXX: only readback the rectangle which is being mapped? */
+			/* XXX: when discard is true, no need to read back from depth texture */
+			if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
+				R600_ERR("failed to create temporary texture to hold untiled copy\n");
+				FREE(trans);
+				return NULL;
+			}
 
-		r600_blit_uncompress_depth(ctx, rtex, staging_depth,
-					   level, level,
-					   box->z, box->z + box->depth - 1);
+			r600_blit_decompress_depth(ctx, rtex, staging_depth,
+						   level, level,
+						   box->z, box->z + box->depth - 1,
+						   0, 0);
 
-		trans->transfer.stride = staging_depth->pitch_in_bytes[level];
-		trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
+			offset = r600_texture_get_offset(staging_depth, level, box);
+		}
+
+		trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
+                trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
 		trans->staging = (struct r600_resource*)staging_depth;
-		return &trans->transfer;
 	} else if (use_staging_texture) {
-		resource.target = PIPE_TEXTURE_2D;
-		resource.format = texture->format;
-		resource.width0 = box->width;
-		resource.height0 = box->height;
-		resource.depth0 = 1;
-		resource.array_size = 1;
-		resource.last_level = 0;
-		resource.nr_samples = 0;
-		resource.usage = PIPE_USAGE_STAGING;
-		resource.bind = 0;
-		resource.flags = R600_RESOURCE_FLAG_TRANSFER;
-		/* For texture reading, the temporary (detiled) texture is used as
-		 * a render target when blitting from a tiled texture. */
-		if (usage & PIPE_TRANSFER_READ) {
-			resource.bind |= PIPE_BIND_RENDER_TARGET;
-		}
-		/* For texture writing, the temporary texture is used as a sampler
-		 * when blitting into a tiled texture. */
-		if (usage & PIPE_TRANSFER_WRITE) {
-			resource.bind |= PIPE_BIND_SAMPLER_VIEW;
-		}
+		struct pipe_resource resource;
+		struct r600_texture *staging;
+
+		r600_init_temp_resource_from_box(&resource, texture, box, level,
+						 R600_RESOURCE_FLAG_TRANSFER);
+
 		/* Create the temporary texture. */
-		trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource);
-		if (trans->staging == NULL) {
+		staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
+		if (staging == NULL) {
 			R600_ERR("failed to create temporary texture to hold untiled copy\n");
-			pipe_resource_reference(&trans->transfer.resource, NULL);
 			FREE(trans);
 			return NULL;
 		}
-
-		trans->transfer.stride =
-			((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
+		trans->staging = &staging->resource;
+		trans->transfer.stride = staging->surface.level[0].pitch_bytes;
+		trans->transfer.layer_stride = staging->surface.level[0].slice_size;
 		if (usage & PIPE_TRANSFER_READ) {
 			r600_copy_to_staging_texture(ctx, trans);
-			/* Always referenced in the blit. */
-			r600_flush(ctx, NULL, 0);
-		}
-		return &trans->transfer;
-	}
-	trans->transfer.stride = rtex->pitch_in_bytes[level];
-	trans->transfer.layer_stride = rtex->layer_size[level];
-	trans->offset = r600_texture_get_offset(rtex, level, box->z);
-	return &trans->transfer;
-}
-
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
-				   struct pipe_transfer *transfer)
-{
-	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-	struct pipe_resource *texture = transfer->resource;
-	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
-
-	if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
-		if (rtex->is_depth) {
-			ctx->resource_copy_region(ctx, texture, transfer->level,
-						  transfer->box.x, transfer->box.y, transfer->box.z,
-						  &rtransfer->staging->b.b, transfer->level,
-						  &transfer->box);
-		} else {
-			r600_copy_from_staging_texture(ctx, rtransfer);
 		}
+	} else {
+		/* the resource is mapped directly */
+		trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
+		trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
+		offset = r600_texture_get_offset(rtex, level, box);
 	}
 
-	if (rtransfer->staging)
-		pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
-
-	pipe_resource_reference(&transfer->resource, NULL);
-	FREE(transfer);
-}
-
-void* r600_texture_transfer_map(struct pipe_context *ctx,
-				struct pipe_transfer* transfer)
-{
-	struct r600_context *rctx = (struct r600_context *)ctx;
-	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-	struct radeon_winsys_cs_handle *buf;
-	struct r600_resource_texture *rtex =
-			(struct r600_resource_texture*)transfer->resource;
-	enum pipe_format format = transfer->resource->format;
-	unsigned offset = 0;
-	char *map;
-
-	if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
-		return r600_compute_global_transfer_map(ctx, transfer);
-	}
-
-	if (rtransfer->staging) {
-		buf = ((struct r600_resource *)rtransfer->staging)->cs_buf;
+	if (trans->staging) {
+		buf = trans->staging;
 	} else {
-		buf = ((struct r600_resource *)transfer->resource)->cs_buf;
+		buf = &rtex->resource;
 	}
 
-	if (rtex->is_depth || !rtransfer->staging)
-		offset = rtransfer->offset +
-			transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
-			transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
-
-	if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
+	if (!(map = r600_buffer_mmap_sync_with_rings(rctx, buf, usage))) {
+		pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
+		FREE(trans);
 		return NULL;
 	}
 
+	*ptransfer = &trans->transfer;
 	return map + offset;
 }
 
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
-				 struct pipe_transfer* transfer)
+static void r600_texture_transfer_unmap(struct pipe_context *ctx,
+					struct pipe_transfer* transfer)
 {
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 	struct r600_context *rctx = (struct r600_context*)ctx;
 	struct radeon_winsys_cs_handle *buf;
+	struct pipe_resource *texture = transfer->resource;
+	struct r600_texture *rtex = (struct r600_texture*)texture;
 
 	if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) {
 		return r600_compute_global_transfer_unmap(ctx, transfer);
@@ -646,6 +966,22 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 		buf = ((struct r600_resource *)transfer->resource)->cs_buf;
 	}
 	rctx->ws->buffer_unmap(buf);
+
+	if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
+		if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
+			ctx->resource_copy_region(ctx, texture, transfer->level,
+						  transfer->box.x, transfer->box.y, transfer->box.z,
+						  &rtransfer->staging->b.b, transfer->level,
+						  &transfer->box);
+		} else {
+			r600_copy_from_staging_texture(ctx, rtransfer);
+		}
+	}
+
+	if (rtransfer->staging)
+		pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
+
+	FREE(transfer);
 }
 
 void r600_init_surface_functions(struct r600_context *r600)
@@ -654,18 +990,26 @@ void r600_init_surface_functions(struct r600_context *r600)
 	r600->context.surface_destroy = r600_surface_destroy;
 }
 
-static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
-		const unsigned char *swizzle_view)
+unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
+				   const unsigned char *swizzle_view,
+				   boolean vtx)
 {
 	unsigned i;
 	unsigned char swizzle[4];
 	unsigned result = 0;
-	const uint32_t swizzle_shift[4] = {
+	const uint32_t tex_swizzle_shift[4] = {
 		16, 19, 22, 25,
 	};
+	const uint32_t vtx_swizzle_shift[4] = {
+		3, 6, 9, 12,
+	};
 	const uint32_t swizzle_bit[4] = {
 		0, 1, 2, 3,
 	};
+	const uint32_t *swizzle_shift = tex_swizzle_shift;
+
+	if (vtx)
+		swizzle_shift = vtx_swizzle_shift;
 
 	if (swizzle_view) {
 		util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
@@ -704,11 +1048,14 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
 				  const unsigned char *swizzle_view,
 				  uint32_t *word4_p, uint32_t *yuv_format_p)
 {
+	struct r600_screen *rscreen = (struct r600_screen *)screen;
 	uint32_t result = 0, word4 = 0, yuv_format = 0;
 	const struct util_format_description *desc;
 	boolean uniform = TRUE;
-	static int r600_enable_s3tc = -1;
+	bool enable_s3tc = rscreen->info.drm_minor >= 9;
 	bool is_srgb_valid = FALSE;
+	const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
+	const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
 
 	int i;
 	const uint32_t sign_bit[4] = {
@@ -719,38 +1066,62 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
 	};
 	desc = util_format_description(format);
 
-	word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
+	/* Depth and stencil swizzling is handled separately. */
+	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
+		word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
+	}
 
 	/* Colorspace (return non-RGB formats directly). */
 	switch (desc->colorspace) {
-		/* Depth stencil formats */
+	/* Depth stencil formats */
 	case UTIL_FORMAT_COLORSPACE_ZS:
 		switch (format) {
+		/* Depth sampler formats. */
 		case PIPE_FORMAT_Z16_UNORM:
+			word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
 			result = FMT_16;
 			goto out_word4;
-		case PIPE_FORMAT_X24S8_UINT:
-			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 		case PIPE_FORMAT_Z24X8_UNORM:
 		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+			word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
 			result = FMT_8_24;
 			goto out_word4;
-		case PIPE_FORMAT_S8X24_UINT:
-			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 		case PIPE_FORMAT_X8Z24_UNORM:
 		case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+			if (rscreen->chip_class < EVERGREEN)
+				goto out_unknown;
+			word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
 			result = FMT_24_8;
 			goto out_word4;
+		case PIPE_FORMAT_Z32_FLOAT:
+			word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
+			result = FMT_32_FLOAT;
+			goto out_word4;
+		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+			word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
+			result = FMT_X24_8_32_FLOAT;
+			goto out_word4;
+		/* Stencil sampler formats. */
 		case PIPE_FORMAT_S8_UINT:
+			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
+			word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
 			result = FMT_8;
+			goto out_word4;
+		case PIPE_FORMAT_X24S8_UINT:
 			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
+			word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
+			result = FMT_8_24;
 			goto out_word4;
-		case PIPE_FORMAT_Z32_FLOAT:
-			result = FMT_32_FLOAT;
+		case PIPE_FORMAT_S8X24_UINT:
+			if (rscreen->chip_class < EVERGREEN)
+				goto out_unknown;
+			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
+			word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
+			result = FMT_24_8;
 			goto out_word4;
 		case PIPE_FORMAT_X32_S8X24_UINT:
 			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
-		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+			word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
 			result = FMT_X24_8_32_FLOAT;
 			goto out_word4;
 		default:
@@ -775,16 +1146,8 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
 		break;
 	}
 
-	if (r600_enable_s3tc == -1) {
-		struct r600_screen *rscreen = (struct r600_screen *)screen;
-		if (rscreen->info.drm_minor >= 9)
-			r600_enable_s3tc = 1;
-		else
-			r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
-	}
-
 	if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
-		if (!r600_enable_s3tc)
+		if (!enable_s3tc)
 			goto out_unknown;
 
 		switch (format) {
@@ -809,7 +1172,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
 
 	if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 
-		if (!r600_enable_s3tc)
+		if (!enable_s3tc)
 			goto out_unknown;
 
 		if (!util_format_s3tc_enabled) {
@@ -1031,3 +1394,13 @@ out_unknown:
 	/* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
 	return ~0;
 }
+
+static const struct u_resource_vtbl r600_texture_vtbl =
+{
+	r600_texture_get_handle,	/* get_handle */
+	r600_texture_destroy,		/* resource_destroy */
+	r600_texture_transfer_map,	/* transfer_map */
+	NULL,				/* transfer_flush_region */
+	r600_texture_transfer_unmap,	/* transfer_unmap */
+	NULL				/* transfer_inline_write */
+};