X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_texture.c;h=a590858c85287c7d936c5de457e9915a9c369521;hb=6baad55f157387d0bb44144680a96bc32280109f;hp=b36f8236081bbd8d75d34e01f1060de003ab0663;hpb=ea5aab85fd195074189832c2d6870dd78f0f8966;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index b36f8236081..a590858c852 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -31,6 +31,7 @@ #include #include #include "state_tracker/drm_driver.h" +#include "pipebuffer/pb_buffer.h" #include "r600_pipe.h" #include "r600_resource.h" #include "r600_state_inlines.h" @@ -39,8 +40,8 @@ extern struct u_resource_vtbl r600_texture_vtbl; -/* Copy from a tiled texture to a detiled one. */ -static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) +/* Copy from a full GPU texture to a transfer's staging one. */ +static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) { struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; struct pipe_resource *texture = transfer->resource; @@ -48,15 +49,15 @@ static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_t subdst.face = 0; subdst.level = 0; - ctx->resource_copy_region(ctx, rtransfer->linear_texture, + ctx->resource_copy_region(ctx, rtransfer->staging_texture, subdst, 0, 0, 0, texture, transfer->sr, transfer->box.x, transfer->box.y, transfer->box.z, transfer->box.width, transfer->box.height); } -/* Copy from a detiled texture to a tiled one. */ -static void r600_copy_into_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) +/* Copy from a transfer's staging texture to a full GPU one. */ +static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) { struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; struct pipe_resource *texture = transfer->resource; @@ -66,7 +67,7 @@ static void r600_copy_into_tiled_texture(struct pipe_context *ctx, struct r600_t subsrc.level = 0; ctx->resource_copy_region(ctx, texture, transfer->sr, transfer->box.x, transfer->box.y, transfer->box.z, - rtransfer->linear_texture, subsrc, + rtransfer->staging_texture, subsrc, 0, 0, 0, transfer->box.width, transfer->box.height); @@ -92,6 +93,52 @@ static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, } } +static unsigned r600_get_pixel_alignment(struct pipe_screen *screen, + enum pipe_format format, + unsigned array_mode) +{ + struct r600_screen* rscreen = (struct r600_screen *)screen; + unsigned pixsize = util_format_get_blocksize(format); + int p_align; + + switch(array_mode) { + case V_038000_ARRAY_1D_TILED_THIN1: + p_align = MAX2(8, + ((rscreen->tiling_info->group_bytes / 8 / pixsize))); + break; + case V_038000_ARRAY_2D_TILED_THIN1: + p_align = MAX2(rscreen->tiling_info->num_banks, + (((rscreen->tiling_info->group_bytes / 8 / pixsize)) * + rscreen->tiling_info->num_banks)); + break; + case 0: + default: + p_align = 64; + break; + } + return p_align; +} + +static unsigned r600_get_height_alignment(struct pipe_screen *screen, + unsigned array_mode) +{ + struct r600_screen* rscreen = (struct r600_screen *)screen; + int h_align; + + switch (array_mode) { + case V_038000_ARRAY_2D_TILED_THIN1: + h_align = rscreen->tiling_info->num_channels * 8; + break; + case V_038000_ARRAY_1D_TILED_THIN1: + h_align = 8; + break; + default: + h_align = 1; + break; + } + return h_align; +} + static unsigned mip_minify(unsigned size, unsigned level) { unsigned val; @@ -108,18 +155,20 @@ static unsigned r600_texture_get_stride(struct pipe_screen *screen, struct pipe_resource *ptex = &rtex->resource.base.b; struct radeon *radeon = (struct radeon *)screen->winsys; enum chip_class chipc = r600_get_family_class(radeon); - unsigned width, stride; + unsigned width, stride, tile_width; if (rtex->pitch_override) return rtex->pitch_override; width = mip_minify(ptex->width0, level); - - stride = util_format_get_stride(ptex->format, align(width, 64)); + if (util_format_is_plain(ptex->format)) { + tile_width = r600_get_pixel_alignment(screen, ptex->format, + rtex->array_mode[level]); + width = align(width, tile_width); + } + stride = util_format_get_stride(ptex->format, width); if (chipc == EVERGREEN) stride = align(stride, 512); - else - stride = align(stride, 256); return stride; } @@ -128,9 +177,14 @@ static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen, unsigned level) { struct pipe_resource *ptex = &rtex->resource.base.b; - unsigned height; + unsigned height, tile_height; height = mip_minify(ptex->height0, level); + if (util_format_is_plain(ptex->format)) { + tile_height = r600_get_height_alignment(screen, + rtex->array_mode[level]); + height = align(height, tile_height); + } return util_format_get_nblocksy(ptex->format, height); } @@ -146,7 +200,31 @@ static void r600_texture_set_array_mode(struct pipe_screen *screen, struct r600_resource_texture *rtex, unsigned level, unsigned array_mode) { - rtex->array_mode[level] = array_mode; + struct pipe_resource *ptex = &rtex->resource.base.b; + + switch (array_mode) { + case V_0280A0_ARRAY_LINEAR_GENERAL: + case V_0280A0_ARRAY_LINEAR_ALIGNED: + case V_0280A0_ARRAY_1D_TILED_THIN1: + default: + rtex->array_mode[level] = array_mode; + break; + case V_0280A0_ARRAY_2D_TILED_THIN1: + { + unsigned w, h, tile_height, tile_width; + + tile_height = r600_get_height_alignment(screen, array_mode); + tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode); + + w = mip_minify(ptex->width0, level); + h = mip_minify(ptex->height0, level); + if (w < tile_width || h < tile_height) + rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1; + else + rtex->array_mode[level] = array_mode; + } + break; + } } static void r600_setup_miptree(struct pipe_screen *screen, @@ -206,7 +284,6 @@ r600_texture_create_object(struct pipe_screen *screen, pipe_reference_init(&resource->base.b.reference, 1); resource->base.b.screen = screen; resource->bo = bo; - resource->domain = r600_domain_from_usage(resource->base.b.bind); rtex->pitch_override = pitch_in_bytes_override; if (array_mode) @@ -216,7 +293,7 @@ r600_texture_create_object(struct pipe_screen *screen, resource->size = rtex->size; if (!resource->bo) { - resource->bo = r600_bo(radeon, rtex->size, 4096, 0); + resource->bo = r600_bo(radeon, rtex->size, 4096, base->bind, base->usage); if (!resource->bo) { FREE(rtex); return NULL; @@ -229,6 +306,19 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen, const struct pipe_resource *templ) { unsigned array_mode = 0; + static int force_tiling = -1; + + /* Would like some magic "get_bool_option_once" routine. + */ + if (force_tiling == -1) + force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE); + + if (force_tiling) { + if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && + !(templ->bind & PIPE_BIND_SCANOUT)) { + array_mode = V_038000_ARRAY_2D_TILED_THIN1; + } + } return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 0, 0, NULL); @@ -251,30 +341,45 @@ static void r600_texture_destroy(struct pipe_screen *screen, FREE(rtex); } +static boolean r600_texture_get_handle(struct pipe_screen* screen, + struct pipe_resource *ptex, + struct winsys_handle *whandle) +{ + struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; + struct r600_resource *resource = &rtex->resource; + struct radeon *radeon = (struct radeon *)screen->winsys; + + return r600_bo_get_winsys_handle(radeon, resource->bo, + rtex->pitch_in_bytes[0], whandle); +} + static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen, struct pipe_resource *texture, unsigned face, unsigned level, unsigned zslice, unsigned flags) { struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; - struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface); - unsigned offset; + struct r600_surface *surface = CALLOC_STRUCT(r600_surface); + unsigned offset, tile_height; if (surface == NULL) return NULL; offset = r600_texture_get_offset(rtex, level, zslice, face); - pipe_reference_init(&surface->reference, 1); - pipe_resource_reference(&surface->texture, texture); - surface->format = texture->format; - surface->width = mip_minify(texture->width0, level); - surface->height = mip_minify(texture->height0, level); - surface->offset = offset; - surface->usage = flags; - surface->zslice = zslice; - surface->texture = texture; - surface->face = face; - surface->level = level; - return surface; + pipe_reference_init(&surface->base.reference, 1); + pipe_resource_reference(&surface->base.texture, texture); + surface->base.format = texture->format; + surface->base.width = mip_minify(texture->width0, level); + surface->base.height = mip_minify(texture->height0, level); + surface->base.offset = offset; + surface->base.usage = flags; + surface->base.zslice = zslice; + surface->base.texture = texture; + surface->base.face = face; + surface->base.level = level; + + tile_height = r600_get_height_alignment(screen, rtex->array_mode[level]); + surface->aligned_height = align(surface->base.height, tile_height); + return &surface->base; } static void r600_tex_surface_destroy(struct pipe_surface *surface) @@ -336,7 +441,7 @@ int r600_texture_depth_flush(struct pipe_context *ctx, resource.nr_samples = 0; resource.usage = PIPE_USAGE_DYNAMIC; resource.bind = 0; - resource.flags = 0; + resource.flags = R600_RESOURCE_FLAG_TRANSFER; resource.bind |= PIPE_BIND_DEPTH_STENCIL; @@ -347,10 +452,50 @@ int r600_texture_depth_flush(struct pipe_context *ctx, } out: + /* XXX: only do this if the depth texture has actually changed: + */ r600_blit_uncompress_depth_ptr(ctx, rtex); return 0; } +/* Needs adjustment for pixelformat: + */ +static INLINE unsigned u_box_volume( const struct pipe_box *box ) +{ + return box->width * box->depth * box->height; +}; + + +/* Figure out whether u_blitter will fallback to a transfer operation. + * If so, don't use a staging resource. + */ +static boolean permit_hardware_blit(struct pipe_screen *screen, + struct pipe_resource *res) +{ + unsigned bind; + + if (util_format_is_depth_or_stencil(res->format)) + bind = PIPE_BIND_DEPTH_STENCIL; + else + bind = PIPE_BIND_RENDER_TARGET; + + if (!screen->is_format_supported(screen, + res->format, + res->target, + res->nr_samples, + bind, 0)) + return FALSE; + + if (!screen->is_format_supported(screen, + res->format, + res->target, + res->nr_samples, + PIPE_BIND_SAMPLER_VIEW, 0)) + return FALSE; + + return TRUE; +} + struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, struct pipe_resource *texture, struct pipe_subresource sr, @@ -361,6 +506,36 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, struct pipe_resource resource; struct r600_transfer *trans; int r; + boolean use_staging_texture = FALSE; + + /* We cannot map a tiled texture directly because the data is + * in a different order, therefore we do detiling using a blit. + * + * Also, use a temporary in GTT memory for read transfers, as + * the CPU is much happier reading out of cached system memory + * than uncached VRAM. + */ + if (rtex->tiled) + use_staging_texture = TRUE; + + if ((usage & PIPE_TRANSFER_READ) && + u_box_volume(box) > 1024) + use_staging_texture = TRUE; + + /* XXX: Use a staging texture for uploads if the underlying BO + * is busy. No interface for checking that currently? so do + * it eagerly whenever the transfer doesn't require a readback + * and might block. + */ + if ((usage & PIPE_TRANSFER_WRITE) && + !(usage & (PIPE_TRANSFER_READ | + PIPE_TRANSFER_DONTBLOCK | + PIPE_TRANSFER_UNSYNCHRONIZED))) + use_staging_texture = TRUE; + + if (!permit_hardware_blit(ctx->screen, texture) || + (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) + use_staging_texture = FALSE; trans = CALLOC_STRUCT(r600_transfer); if (trans == NULL) @@ -370,6 +545,10 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, trans->transfer.usage = usage; trans->transfer.box = *box; if (rtex->depth) { + /* XXX: only readback the rectangle which is being mapped? + */ + /* XXX: when discard is true, no need to read back from depth texture + */ r = r600_texture_depth_flush(ctx, texture); if (r < 0) { R600_ERR("failed to create temporary texture to hold untiled copy\n"); @@ -377,7 +556,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, FREE(trans); return NULL; } - } else if (rtex->tiled) { + } else if (use_staging_texture) { resource.target = PIPE_TEXTURE_2D; resource.format = texture->format; resource.width0 = box->width; @@ -385,9 +564,9 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, resource.depth0 = 1; resource.last_level = 0; resource.nr_samples = 0; - resource.usage = PIPE_USAGE_DYNAMIC; + resource.usage = PIPE_USAGE_STAGING; resource.bind = 0; - resource.flags = 0; + resource.flags = R600_RESOURCE_FLAG_TRANSFER; /* For texture reading, the temporary (detiled) texture is used as * a render target when blitting from a tiled texture. */ if (usage & PIPE_TRANSFER_READ) { @@ -399,8 +578,8 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, resource.bind |= PIPE_BIND_SAMPLER_VIEW; } /* Create the temporary texture. */ - trans->linear_texture = ctx->screen->resource_create(ctx->screen, &resource); - if (trans->linear_texture == NULL) { + trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource); + if (trans->staging_texture == NULL) { R600_ERR("failed to create temporary texture to hold untiled copy\n"); pipe_resource_reference(&trans->transfer.resource, NULL); FREE(trans); @@ -408,11 +587,9 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, } trans->transfer.stride = - ((struct r600_resource_texture *)trans->linear_texture)->pitch_in_bytes[0]; + ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0]; if (usage & PIPE_TRANSFER_READ) { - /* We cannot map a tiled texture directly because the data is - * in a different order, therefore we do detiling using a blit. */ - r600_copy_from_tiled_texture(ctx, trans); + r600_copy_to_staging_texture(ctx, trans); /* Always referenced in the blit. */ ctx->flush(ctx, 0, NULL); } @@ -429,11 +606,11 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx, struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; - if (rtransfer->linear_texture) { + if (rtransfer->staging_texture) { if (transfer->usage & PIPE_TRANSFER_WRITE) { - r600_copy_into_tiled_texture(ctx, rtransfer); + r600_copy_from_staging_texture(ctx, rtransfer); } - pipe_resource_reference(&rtransfer->linear_texture, NULL); + pipe_resource_reference(&rtransfer->staging_texture, NULL); } if (rtex->flushed_depth_texture) { pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); @@ -450,10 +627,11 @@ void* r600_texture_transfer_map(struct pipe_context *ctx, enum pipe_format format = transfer->resource->format; struct radeon *radeon = (struct radeon *)ctx->screen->winsys; unsigned offset = 0; + unsigned usage = 0; char *map; - if (rtransfer->linear_texture) { - bo = ((struct r600_resource *)rtransfer->linear_texture)->bo; + if (rtransfer->staging_texture) { + bo = ((struct r600_resource *)rtransfer->staging_texture)->bo; } else { struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; @@ -466,7 +644,30 @@ void* r600_texture_transfer_map(struct pipe_context *ctx, transfer->box.y / util_format_get_blockheight(format) * transfer->stride + transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); } - map = r600_bo_map(radeon, bo, 0, ctx); + + if (transfer->usage & PIPE_TRANSFER_WRITE) { + usage |= PB_USAGE_CPU_WRITE; + + if (transfer->usage & PIPE_TRANSFER_DISCARD) { + } + + if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) { + } + } + + if (transfer->usage & PIPE_TRANSFER_READ) { + usage |= PB_USAGE_CPU_READ; + } + + if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) { + usage |= PB_USAGE_DONTBLOCK; + } + + if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) { + usage |= PB_USAGE_UNSYNCHRONIZED; + } + + map = r600_bo_map(radeon, bo, usage, ctx); if (!map) { return NULL; } @@ -481,8 +682,8 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx, struct radeon *radeon = (struct radeon *)ctx->screen->winsys; struct r600_bo *bo; - if (rtransfer->linear_texture) { - bo = ((struct r600_resource *)rtransfer->linear_texture)->bo; + if (rtransfer->staging_texture) { + bo = ((struct r600_resource *)rtransfer->staging_texture)->bo; } else { struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; @@ -497,7 +698,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx, struct u_resource_vtbl r600_texture_vtbl = { - u_default_resource_get_handle, /* get_handle */ + r600_texture_get_handle, /* get_handle */ r600_texture_destroy, /* resource_destroy */ r600_texture_is_referenced, /* is_resource_referenced */ r600_texture_get_transfer, /* get_transfer */ @@ -602,7 +803,7 @@ uint32_t r600_translate_texformat(enum pipe_format format, result = FMT_24_8; goto out_word4; case PIPE_FORMAT_S8_USCALED: - result = V_0280A0_COLOR_8; + result = FMT_8; word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); goto out_word4; default: @@ -631,7 +832,29 @@ uint32_t r600_translate_texformat(enum pipe_format format, /* S3TC formats. TODO */ if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { - goto out_unknown; + static int r600_enable_s3tc = -1; + + if (r600_enable_s3tc == -1) + r600_enable_s3tc = + debug_get_bool_option("R600_ENABLE_S3TC", FALSE); + + if (!r600_enable_s3tc) + goto out_unknown; + + switch (format) { + case PIPE_FORMAT_DXT1_RGB: + case PIPE_FORMAT_DXT1_RGBA: + result = FMT_BC1; + goto out_word4; + case PIPE_FORMAT_DXT3_RGBA: + result = FMT_BC2; + goto out_word4; + case PIPE_FORMAT_DXT5_RGBA: + result = FMT_BC3; + goto out_word4; + default: + goto out_unknown; + } }