X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600d.h;h=bce8b4ea065ca3e20597b4e737dc600378a6b80c;hb=1f4bb3826464e2ce1d3f47183c96e6e7fde9a1d7;hp=933d99e1a4bba5d3efe35acd3606e9f42b1e3efa;hpb=428146c14fed5b41e3da9e72488396f214b23b0d;p=mesa.git diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h index 933d99e1a4b..bce8b4ea065 100644 --- a/src/gallium/drivers/r600/r600d.h +++ b/src/gallium/drivers/r600/r600d.h @@ -52,12 +52,18 @@ #define PKT3_NOP 0x10 +#define EG_PKT3_SET_BASE 0x11 /* >= evergreen */ +#define EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE 1 /* DX11 Draw_Index_Indirect Patch Table Base */ +#define EG_PKT3_INDEX_BUFFER_SIZE 0x13 #define PKT3_INDIRECT_BUFFER_END 0x17 #define PKT3_SET_PREDICATION 0x20 #define PKT3_REG_RMW 0x21 #define PKT3_COND_EXEC 0x22 #define PKT3_PRED_EXEC 0x23 -#define PKT3_START_3D_CMDBUF 0x24 +#define PKT3_START_3D_CMDBUF 0x24 /* removed on evergreen */ +#define EG_PKT3_DRAW_INDIRECT 0x24 /* >= evergreen */ +#define EG_PKT3_DRAW_INDEX_INDIRECT 0x25 +#define EG_PKT3_INDEX_BASE 0x26 #define PKT3_DRAW_INDEX_2 0x27 #define PKT3_CONTEXT_CONTROL 0x28 #define PKT3_DRAW_INDEX_IMMD_BE 0x29 @@ -106,17 +112,25 @@ #define PKT3_SET_RESOURCE 0x6D #define PKT3_SET_SAMPLER 0x6E #define PKT3_SET_CTL_CONST 0x6F +#define PKT3_STRMOUT_BASE_UPDATE 0x72 #define PKT3_SURFACE_BASE_UPDATE 0x73 #define SURFACE_BASE_UPDATE_DEPTH (1 << 0) #define SURFACE_BASE_UPDATE_COLOR(x) (2 << (x)) +#define SURFACE_BASE_UPDATE_COLOR_NUM(x) (((1 << x) - 1) << 1) #define SURFACE_BASE_UPDATE_STRMOUT(x) (0x200 << (x)) #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 #define EVENT_TYPE_ZPASS_DONE 0x15 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 +#define EVENT_TYPE_PIPELINESTAT_START 25 +#define EVENT_TYPE_PIPELINESTAT_STOP 26 +#define EVENT_TYPE_SAMPLE_PIPELINESTAT 30 #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f #define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20 +#define EVENT_TYPE_FLUSH_AND_INV_DB_META 0x2c /* supported on r700+ */ +#define EVENT_TYPE_VGT_FLUSH 0x24 +#define EVENT_TYPE_FLUSH_AND_INV_CB_META 46 /* supported on r700+ */ #define EVENT_TYPE(x) ((x) << 0) #define EVENT_INDEX(x) ((x) << 8) /* 0 - any non-TS event @@ -156,13 +170,64 @@ #define PKT3_PRED_S(x) (((x) >> 0) & 0x1) #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) +#define PKT3_CP_DMA 0x41 +/* 1. header + * 2. SRC_ADDR_LO [31:0] + * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] + * 4. DST_ADDR_LO [31:0] + * 5. DST_ADDR_HI [7:0] + * 6. COMMAND [29:22] | BYTE_COUNT [20:0] + */ +#define PKT3_CP_DMA_CP_SYNC (1 << 31) +/* COMMAND */ +#define PKT3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) +/* 0 - none + * 1 - 8 in 16 + * 2 - 8 in 32 + * 3 - 8 in 64 + */ +#define PKT3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) +/* 0 - none + * 1 - 8 in 16 + * 2 - 8 in 32 + * 3 - 8 in 64 + */ +#define PKT3_CP_DMA_CMD_SAS (1 << 26) +/* 0 - memory + * 1 - register + */ +#define PKT3_CP_DMA_CMD_DAS (1 << 27) +/* 0 - memory + * 1 - register + */ +#define PKT3_CP_DMA_CMD_SAIC (1 << 28) +#define PKT3_CP_DMA_CMD_DAIC (1 << 29) + + /* Registers */ #define R_008490_CP_STRMOUT_CNTL 0x008490 #define S_008490_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0) +#define R_008C40_SQ_ESGS_RING_BASE 0x008C40 +#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 +#define R_008C48_SQ_GSVS_RING_BASE 0x008C48 +#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C +#define R_008C50_SQ_ESTMP_RING_BASE 0x008C50 +#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 +#define R_008C50_SQ_GSTMP_RING_BASE 0x008C58 +#define R_008C54_SQ_GSTMP_RING_SIZE 0x008C5C + +#define R_0088C8_VGT_GS_PER_ES 0x0088C8 +#define R_0088CC_VGT_ES_PER_GS 0x0088CC +#define R_0088E8_VGT_GS_PER_VS 0x0088E8 + #define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 /* read-only */ #define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 /* read-only */ #define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 /* read-only */ #define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C /* read-only */ +#define R_008B40_PA_SC_AA_SAMPLE_LOCS_2S 0x008B40 +#define R_008B44_PA_SC_AA_SAMPLE_LOCS_4S 0x008B44 +#define R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x008B48 +#define R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x008B4C #define R_008C00_SQ_CONFIG 0x00008C00 #define S_008C00_VC_ENABLE(x) (((x) & 0x1) << 0) #define G_008C00_VC_ENABLE(x) (((x) >> 0) & 0x1) @@ -302,6 +367,9 @@ #define V_0280A0_SWAP_STD_REV 0x00000002 #define V_0280A0_SWAP_ALT_REV 0x00000003 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) +#define V_0280A0_TILE_DISABLE 0 +#define V_0280A0_CLEAR_ENABLE 1 +#define V_0280A0_FRAG_ENABLE 2 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) #define C_0280A0_TILE_MODE 0xFFF3FFFF #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) @@ -417,8 +485,18 @@ #define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1) #define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) +#define V_028808_NORMAL 0 +#define V_028808_DISABLE 1 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) #define C_028808_SPECIAL_OP 0xFFFFFF8F +#define V_028808_SPECIAL_NORMAL 0x00 +#define V_028808_SPECIAL_DISABLE 0x01 +#define V_028808_SPECIAL_FAST_CLEAR 0x02 +#define V_028808_SPECIAL_FORCE_CLEAR 0x03 +#define V_028808_SPECIAL_EXPAND_COLOR 0x04 +#define V_028808_SPECIAL_EXPAND_TEXTURE 0x05 +#define V_028808_SPECIAL_EXPAND_SAMPLES 0x06 +#define V_028808_SPECIAL_RESOLVE_BOX 0x07 #define S_028808_PER_MRT_BLEND(x) (((x) & 0x1) << 7) #define G_028808_PER_MRT_BLEND(x) (((x) >> 7) & 0x1) #define C_028808_PER_MRT_BLEND 0xFFFFFF7F @@ -471,6 +549,9 @@ #define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21) #define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1) #define C_028810_VTX_KILL_OR 0xFFDFFFFF +#define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22) /* R700 only? */ +#define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1) +#define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF #define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24) #define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1) #define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF @@ -510,6 +591,7 @@ #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF +#define R_028014_DB_HTILE_DATA_BASE 0x00028014 #define R_028414_CB_BLEND_RED 0x028414 #define S_028414_BLEND_RED(x) (((x) & 0xFFFFFFFF) << 0) #define G_028414_BLEND_RED(x) (((x) >> 0) & 0xFFFFFFFF) @@ -745,6 +827,9 @@ #define S_028D10_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) #define G_028D10_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) #define C_028D10_IGNORE_SC_ZRANGE 0xFFFDFFFF +#define S_028D10_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21) +#define G_028D10_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F) +#define C_028D10_MAX_TILES_IN_DTT 0xFC1FFFFF #define R_02880C_DB_SHADER_CONTROL 0x02880C #define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0) #define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1) @@ -762,6 +847,9 @@ #define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6) #define G_02880C_KILL_ENABLE(x) (((x) >> 6) & 0x1) #define C_02880C_KILL_ENABLE 0xFFFFFFBF +#define S_02880C_MASK_EXPORT_ENABLE(x) (((x) & 0x1) << 8) +#define G_02880C_MASK_EXPORT_ENABLE(x) (((x) >> 8) & 0x1) +#define C_02880C_MASK_EXPORT_ENABLE 0xFFFFFEFF #define S_02880C_DUAL_EXPORT_ENABLE(x) (((x) & 0x1) << 9) #define G_02880C_DUAL_EXPORT_ENABLE(x) (((x) >> 9) & 0x1) #define C_02880C_DUAL_EXPORT_ENABLE 0xFFFFFDFF @@ -810,6 +898,7 @@ #define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3) #define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3) #define C_028A40_CUT_MODE 0xFFFFFFE7 +#define R_028A50_VGT_ENHANCE 0x028A50 #define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C #define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0) #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0 @@ -968,6 +1057,7 @@ #define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x3) #define C_0287F0_SOURCE_SELECT 0xFFFFFFFC #define V_0287F0_DI_SRC_SEL_DMA 0 +#define V_0287F0_DI_SRC_SEL_IMMEDIATE 1 #define V_0287F0_DI_SRC_SEL_AUTO_INDEX 2 #define S_0287F0_MAJOR_MODE(x) (((x) & 0x3) << 2) #define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x3) @@ -1479,6 +1569,8 @@ #define R_0280B4_CB_COLOR5_INFO 0x0280B4 #define R_0280B8_CB_COLOR6_INFO 0x0280B8 #define R_0280BC_CB_COLOR7_INFO 0x0280BC +#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C +#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX 0x028C20 #define R_028C30_CB_CLRCMP_CONTROL 0x028C30 #define S_028C30_CLRCMP_FCN_SRC(x) (((x) & 0x7) << 0) #define G_028C30_CLRCMP_FCN_SRC(x) (((x) >> 0) & 0x7) @@ -1762,12 +1854,20 @@ #define S_028A40_MODE(x) (((x) & 0x3) << 0) #define G_028A40_MODE(x) (((x) >> 0) & 0x3) #define C_028A40_MODE 0xFFFFFFFC +#define V_028A40_GS_OFF 0 +#define V_028A40_GS_SCENARIO_A 1 +#define V_028A40_GS_SCENARIO_B 2 +#define V_028A40_GS_SCENARIO_G 3 #define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2) #define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1) #define C_028A40_ES_PASSTHRU 0xFFFFFFFB #define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3) #define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3) #define C_028A40_CUT_MODE 0xFFFFFFE7 +#define V_028A40_GS_CUT_1024 0 +#define V_028A40_GS_CUT_512 1 +#define V_028A40_GS_CUT_256 2 +#define V_028A40_GS_CUT_128 3 #define R_008DFC_SQ_CF_WORD0 0x008DFC #define S_008DFC_ADDR(x) (((x) & 0xFFFFFFFF) << 0) #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) @@ -2163,6 +2263,9 @@ #define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 #define R_028A48_PA_SC_MPASS_PS_CNTL 0x028A48 #define R_028C00_PA_SC_LINE_CNTL 0x028C00 +#define S_028C00_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9) +#define G_028C00_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1) +#define C_028C00_EXPAND_LINE_WIDTH 0xFFFFFDFF #define S_028C00_LAST_PIXEL(x) (((x) & 0x1) << 10) #define G_028C00_LAST_PIXEL(x) (((x) >> 10) & 0x1) #define C_028C00_LAST_PIXEL 0xFFFFFBFF @@ -2171,6 +2274,15 @@ #define S_028C08_PIX_CENTER_HALF(x) (((x) & 0x1) << 0) #define G_028C08_PIX_CENTER_HALF(x) (((x) >> 0) & 0x1) #define C_028C08_PIX_CENTER_HALF 0xFFFFFFFE +#define S_028C08_QUANT_MODE(x) (((x) & 0x7) << 3) +#define G_028C08_QUANT_MODE(x) (((x) >> 3) & 0x7) +#define C_028C08_QUANT_MODE 0xFFFFFFC7 +#define V_028C08_X_1_16TH 0x00 +#define V_028C08_X_1_8TH 0x01 +#define V_028C08_X_1_4TH 0x02 +#define V_028C08_X_1_2 0x03 +#define V_028C08_X_1 0x04 +#define V_028C08_X_1_256TH 0x05 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C #define R_028C48_PA_SC_AA_MASK 0x028C48 #define R_028810_PA_CL_CLIP_CNTL 0x028810 @@ -2219,6 +2331,12 @@ #define S_028818_VPORT_Z_OFFSET_ENA(x) (((x) & 0x1) << 5) #define G_028818_VPORT_Z_OFFSET_ENA(x) (((x) >> 5 & 0x1) #define C_028818_VPORT_Z_OFFSET_ENA 0xFFFFFFDF +#define S_028818_VTX_XY_FMT(x) (((x) & 0x1) << 8) +#define G_028818_VTX_XY_FMT(x) (((x) >> 8) & 0x1) +#define C_028818_VTX_XY_FMT 0xFFFFFEFF +#define S_028818_VTX_Z_FMT(x) (((x) & 0x1) << 9) +#define G_028818_VTX_Z_FMT(x) (((x) >> 9) & 0x1) +#define C_028818_VTX_Z_FMT 0xFFFFFDFF #define S_028818_VTX_W0_FMT(x) (((x) & 0x1) << 10) #define G_028818_VTX_W0_FMT(x) (((x) >> 10) & 0x1) #define C_028818_VTX_W0_FMT 0xFFFFFBFF @@ -2247,10 +2365,37 @@ #define R_02880C_DB_SHADER_CONTROL 0x02880C #define R_028D0C_DB_RENDER_CONTROL 0x028D0C #define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define R_028D28_DB_SRESULTS_COMPARE_STATE0 0x028D28 #define R_028D2C_DB_SRESULTS_COMPARE_STATE1 0x028D2C #define R_028D30_DB_PRELOAD_CONTROL 0x028D30 #define R_028D44_DB_ALPHA_TO_MASK 0x028D44 +#define S_028D44_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0) +#define S_028D44_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x3) << 8) +#define S_028D44_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x3) << 10) +#define S_028D44_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x3) << 12) +#define S_028D44_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x3) << 14) +#define S_028D44_OFFSET_ROUND(x) (((x) & 0x1) << 16) #define R_028868_SQ_PGM_RESOURCES_VS 0x028868 +#define R_028890_SQ_PGM_RESOURCES_ES 0x028890 +#define S_028890_NUM_GPRS(x) (((x) & 0xFF) << 0) +#define G_028890_NUM_GPRS(x) (((x) >> 0) & 0xFF) +#define C_028890_NUM_GPRS 0xFFFFFF00 +#define S_028890_STACK_SIZE(x) (((x) & 0xFF) << 8) +#define G_028890_STACK_SIZE(x) (((x) >> 8) & 0xFF) +#define C_028890_STACK_SIZE 0xFFFF00FF +#define S_028890_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_028890_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_028890_DX10_CLAMP 0xFFDFFFFF +#define R_02887C_SQ_PGM_RESOURCES_GS 0x02887C +#define S_02887C_NUM_GPRS(x) (((x) & 0xFF) << 0) +#define G_02887C_NUM_GPRS(x) (((x) >> 0) & 0xFF) +#define C_02887C_NUM_GPRS 0xFFFFFF00 +#define S_02887C_STACK_SIZE(x) (((x) & 0xFF) << 8) +#define G_02887C_STACK_SIZE(x) (((x) >> 8) & 0xFF) +#define C_02887C_STACK_SIZE 0xFFFF00FF +#define S_02887C_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_02887C_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_02887C_DX10_CLAMP 0xFFDFFFFF #define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC #define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 @@ -2340,11 +2485,15 @@ #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF #define R_0288CC_SQ_PGM_CF_OFFSET_PS 0x0288CC -#define R_0288DC_SQ_PGM_CF_OFFSET_FS 0x0288DC #define R_0288D0_SQ_PGM_CF_OFFSET_VS 0x0288D0 +#define R_0288D4_SQ_PGM_CF_OFFSET_GS 0x0288D4 +#define R_0288D8_SQ_PGM_CF_OFFSET_ES 0x0288D8 +#define R_0288DC_SQ_PGM_CF_OFFSET_FS 0x0288DC #define R_028840_SQ_PGM_START_PS 0x028840 #define R_028894_SQ_PGM_START_FS 0x028894 #define R_028858_SQ_PGM_START_VS 0x028858 +#define R_02886C_SQ_PGM_START_GS 0x02886C +#define R_028880_SQ_PGM_START_ES 0x028880 #define R_028080_CB_COLOR0_VIEW 0x028080 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) @@ -2782,6 +2931,8 @@ #define R_0283F4_SQ_VTX_SEMANTIC_29 0x0283F4 #define R_0283F8_SQ_VTX_SEMANTIC_30 0x0283F8 #define R_0283FC_SQ_VTX_SEMANTIC_31 0x0283FC +#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 +#define R_0288E0_SQ_VTX_SEMANTIC_CLEAR 0x0288E0 #define R_028400_VGT_MAX_VTX_INDX 0x028400 #define S_028400_MAX_INDX(x) (((x) & 0xFFFFFFFF) << 0) #define G_028400_MAX_INDX(x) (((x) >> 0) & 0xFFFFFFFF) @@ -3205,6 +3356,8 @@ #define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x028B28 #define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x028B2C #define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x028B30 +#define R_028B38_VGT_GS_MAX_VERT_OUT 0x028B38 /* r7xx */ +#define S_028B38_MAX_VERT_OUT(x) (((x) & 0x7FF) << 0) #define R_028B44_VGT_STRMOUT_BASE_OFFSET_HI_0 0x028B44 #define R_028B48_VGT_STRMOUT_BASE_OFFSET_HI_1 0x028B48 #define R_028B4C_VGT_STRMOUT_BASE_OFFSET_HI_2 0x028B4C @@ -3303,9 +3456,25 @@ #define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) #define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) #define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF +/* r600 only start */ #define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15) #define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1) #define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF +/* r600 only end */ +/* evergreen only start */ +#define S_0085F0_CB8_DEST_BASE_ENA(x) (((x) & 0x1) << 15) +#define G_0085F0_CB8_DEST_BASE_ENA(x) (((x) >> 15) & 0x1) +#define S_0085F0_CB9_DEST_BASE_ENA(x) (((x) & 0x1) << 16) +#define G_0085F0_CB9_DEST_BASE_ENA(x) (((x) >> 16) & 0x1) +#define S_0085F0_CB10_DEST_BASE_ENA(x) (((x) & 0x1) << 17) +#define G_0085F0_CB10_DEST_BASE_ENA(x) (((x) >> 17) & 0x1) +#define S_0085F0_CB11_DEST_BASE_ENA(x) (((x) & 0x1) << 18) +#define G_0085F0_CB11_DEST_BASE_ENA(x) (((x) >> 18) & 0x1) +/* evergreen only end */ +/* evergreen and r7xx only */ +#define S_0085F0_FULL_CACHE_ENA(x) (((x) & 0x1) << 20) +#define G_0085F0_FULL_CACHE_ENA(x) (((x) >> 20) & 0x1) +/* evergreen and r7xx only end */ #define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) #define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) #define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF @@ -3546,10 +3715,12 @@ #define R_028144_ALU_CONST_BUFFER_SIZE_PS_1 0x00028144 #define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180 #define R_028184_ALU_CONST_BUFFER_SIZE_VS_1 0x00028184 +#define R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0 0x000281C0 #define R_028940_ALU_CONST_CACHE_PS_0 0x00028940 #define R_028944_ALU_CONST_CACHE_PS_1 0x00028944 #define R_028980_ALU_CONST_CACHE_VS_0 0x00028980 #define R_028984_ALU_CONST_CACHE_VS_1 0x00028984 +#define R_0289C0_ALU_CONST_CACHE_GS_0 0x000289C0 #define R_03CFF0_SQ_VTX_BASE_VTX_LOC 0x03CFF0 #define R_03CFF4_SQ_VTX_START_INST_LOC 0x03CFF4 @@ -3586,4 +3757,31 @@ #define SQ_TEX_INST_SAMPLE_C_G_LB 0x1E #define SQ_TEX_INST_SAMPLE_C_G_LZ 0x1F +#define CM_R_028AA8_IA_MULTI_VGT_PARAM 0x028AA8 +#define S_028AA8_PRIMGROUP_SIZE(x) (((x) & 0xFFFF) << 0) +#define G_028AA8_PRIMGROUP_SIZE(x) (((x) >> 0) & 0xFFFF) +#define C_028AA8_PRIMGROUP_SIZE 0xFFFF0000 +#define S_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) & 0x1) << 16) +#define G_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) >> 16) & 0x1) +#define C_028AA8_PARTIAL_VS_WAVE_ON 0xFFFEFFFF +#define S_028AA8_SWITCH_ON_EOP(x) (((x) & 0x1) << 17) +#define G_028AA8_SWITCH_ON_EOP(x) (((x) >> 17) & 0x1) +#define C_028AA8_SWITCH_ON_EOP 0xFFFDFFFF + +/* async DMA packets */ +#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ + (((t) & 0x1) << 23) | \ + (((s) & 0x1) << 22) | \ + (((n) & 0xFFFF) << 0)) +/* async DMA Packet types */ +#define DMA_PACKET_WRITE 0x2 +#define DMA_PACKET_COPY 0x3 +#define R600_DMA_COPY_MAX_SIZE_DW 0xffff +#define DMA_PACKET_INDIRECT_BUFFER 0x4 +#define DMA_PACKET_SEMAPHORE 0x5 +#define DMA_PACKET_FENCE 0x6 +#define DMA_PACKET_TRAP 0x7 +#define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ +#define DMA_PACKET_NOP 0xf + #endif