X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeon%2FR600Instructions.td;h=da5f364839f58fb1dd6183c01f9257426a120841;hb=a31b2f71076b9d3fe9bc5f2bae3228f1e7b99ee2;hp=978ccecd3398fec54c889d708d41686f5deb1713;hpb=5523502ff917803166051c8947f5dd3b23c6fcf8;p=mesa.git diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index 978ccecd339..da5f364839f 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -18,8 +18,9 @@ class InstR600 inst, dag outs, dag ins, string asm, list pattern, : AMDGPUInst { field bits<32> Inst; - bit Trig = 0; + bit Trig = 0; bit Op3 = 0; + bit isVector = 0; let Inst = inst; let Namespace = "AMDIL"; @@ -31,6 +32,10 @@ class InstR600 inst, dag outs, dag ins, string asm, list pattern, let TSFlags{4} = Trig; let TSFlags{5} = Op3; + + // Vector instructions are instructions that must fill all slots in an + // instruction group + let TSFlags{6} = isVector; } class InstR600ISA pattern> : @@ -41,11 +46,17 @@ class InstR600ISA pattern> : let Namespace = "AMDIL"; } -def MEMri : Operand { +def MEMxi : Operand { + let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); +} + +def MEMrr : Operand { let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); } def ADDRParam : ComplexPattern; +def ADDRDWord : ComplexPattern; +def ADDRVTX_READ : ComplexPattern; class R600_ALU { @@ -119,16 +130,6 @@ def TEX_SHADOW : PatLeaf< }] >; -def FP_ZERO : PatLeaf < - (fpimm), - [{return N->getValueAPF().isZero();}] ->; - -def FP_ONE : PatLeaf < - (fpimm), - [{return N->isExactlyValue(1.0);}] ->; - def COND_EQ : PatLeaf < (cond), [{switch(N->get()){{default: return false; @@ -170,13 +171,12 @@ def COND_LE : PatLeaf < case ISD::SETLE: return true;}}}] >; -class EG_CF_RAT cf_inst, bits <6> rat_inst, dag outs, dag ins, - string asm> : - InstR600ISA +class EG_CF_RAT cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs, + dag ins, string asm, list pattern> : + InstR600ISA { bits<7> RW_GPR; bits<7> INDEX_GPR; - bits<4> RAT_ID; bits<2> RIM; bits<2> TYPE; @@ -192,7 +192,7 @@ class EG_CF_RAT cf_inst, bits <6> rat_inst, dag outs, dag ins, bits<1> BARRIER; /* CF_ALLOC_EXPORT_WORD0_RAT */ - let Inst{3-0} = RAT_ID; + let Inst{3-0} = rat_id; let Inst{9-4} = rat_inst; let Inst{10} = 0; /* Reserved */ let Inst{12-11} = RIM; @@ -231,7 +231,6 @@ def store_global : PatFrag<(ops node:$value, node:$ptr), def load_param : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return true; const Value *Src = cast(N)->getSrcValue(); if (Src) { PointerType * PT = dyn_cast(Src->getType()); @@ -272,6 +271,10 @@ def load_param : PatFrag<(ops node:$ptr), */ def isR600 : Predicate<"Subtarget.device()" "->getGeneration() == AMDILDeviceInfo::HD4XXX">; +def isR700 : Predicate<"Subtarget.device()" + "->getGeneration() == AMDILDeviceInfo::HD4XXX &&" + "Subtarget.device()->getDeviceFlag()" + ">= OCL_DEVICE_RV710">; def isEG : Predicate<"Subtarget.device()" "->getGeneration() >= AMDILDeviceInfo::HD5XXX && " "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">; @@ -291,8 +294,6 @@ let Predicates = [isR600toCayman] in { /* ------------------------------------------- */ /* Common Instructions R600, R700, Evergreen, Cayman */ /* ------------------------------------------- */ -let Gen = AMDGPUGen.R600_CAYMAN in { - def ADD : R600_2OP < 0x0, "ADD", [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))] @@ -330,7 +331,6 @@ def SETE : R600_2OP < (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_EQ))] >; -//let AMDILOp = AMDILInst.FEQ; def SGT : R600_2OP < 0x09, "SETGT", @@ -345,7 +345,6 @@ def SGE : R600_2OP < (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_GE))] >; -//let AMDILOp = AMDILInst.FGE; def SNE : R600_2OP < 0xB, "SETNE", @@ -354,13 +353,10 @@ def SNE : R600_2OP < COND_NE))] >; -// let AMDILOp = AMDILInst.FNE; - def FRACT : R600_1OP < 0x10, "FRACT", - []> { - let AMDILOp = AMDILInst.FRAC_f32; -} + [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))] +>; def TRUNC : R600_1OP < 0x11, "TRUNC", @@ -369,15 +365,13 @@ def TRUNC : R600_1OP < def CEIL : R600_1OP < 0x12, "CEIL", - [(set R600_Reg32:$dst, (int_AMDIL_round_posinf R600_Reg32:$src))]> { - let AMDILOp = AMDILInst.ROUND_POSINF_f32; -} + [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))] +>; def RNDNE : R600_1OP < 0x13, "RNDNE", - [(set R600_Reg32:$dst, (int_AMDIL_round_nearest R600_Reg32:$src))]> { - let AMDILOp = AMDILInst.ROUND_NEAREST_f32; -} + [(set R600_Reg32:$dst, (frint R600_Reg32:$src))] +>; def FLOOR : R600_1OP < 0x14, "FLOOR", @@ -386,6 +380,25 @@ def FLOOR : R600_1OP < def MOV : R600_1OP <0x19, "MOV", []>; +class MOV_IMM : InstR600 <0x19, + (outs R600_Reg32:$dst), + (ins R600_Reg32:$alu_literal, immType:$imm), + "MOV_IMM $dst, $imm", + [], AnyALU +>; + +def MOV_IMM_I32 : MOV_IMM; +def : Pat < + (imm:$val), + (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val) +>; + +def MOV_IMM_F32 : MOV_IMM; +def : Pat < + (fpimm:$val), + (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val) +>; + def KILLGT : R600_2OP < 0x2D, "KILLGT", [] @@ -393,32 +406,28 @@ def KILLGT : R600_2OP < def AND_INT : R600_2OP < 0x30, "AND_INT", - []> { - let AMDILOp = AMDILInst.AND_i32; -} + [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))] +>; def OR_INT : R600_2OP < 0x31, "OR_INT", - []>{ - let AMDILOp = AMDILInst.BINARY_OR_i32; -} + [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))] +>; def XOR_INT : R600_2OP < 0x32, "XOR_INT", - [] + [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))] >; def NOT_INT : R600_1OP < 0x33, "NOT_INT", - []>{ - let AMDILOp = AMDILInst.BINARY_NOT_i32; -} + [(set R600_Reg32:$dst, (not R600_Reg32:$src))] +>; def ADD_INT : R600_2OP < 0x34, "ADD_INT", - []>{ - let AMDILOp = AMDILInst.ADD_i32; -} + [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))] +>; def SUB_INT : R600_2OP < 0x35, "SUB_INT", @@ -449,8 +458,6 @@ def SETE_INT : R600_2OP < (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))] >; -// let AMDILOp = AMDILInst.IEQ; - def SETGT_INT : R600_2OP < 0x3B, "SGT_INT", [(set (i32 R600_Reg32:$dst), @@ -462,16 +469,12 @@ def SETGE_INT : R600_2OP < [(set (i32 R600_Reg32:$dst), (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))] >; -// let AMDILOp = AMDILInst.IGE; - def SETNE_INT : R600_2OP < 0x3D, "SETNE_INT", [(set (i32 R600_Reg32:$dst), (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))] >; -//let AMDILOp = AMDILInst.INE; - def SETGT_UINT : R600_2OP < 0x3E, "SETGT_UINT", @@ -479,14 +482,11 @@ def SETGT_UINT : R600_2OP < (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))] >; -// let AMDILOp = AMDILInst.UGT; - def SETGE_UINT : R600_2OP < 0x3F, "SETGE_UINT", [(set (i32 R600_Reg32:$dst), (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))] >; -// let AMDILOp = AMDILInst.UGE; def CNDE_INT : R600_3OP < 0x1C, "CNDE_INT", @@ -570,18 +570,6 @@ def TEX_SAMPLE_C_G : R600_TEX < [] >; -} // End Gen R600_CAYMAN - -def KILP : Pat < - (int_AMDGPU_kilp), - (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) ->; - -def KIL : Pat < - (int_AMDGPU_kill R600_Reg32:$src0), - (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0))) ->; - /* Helper classes for common instructions */ class MUL_LIT_Common inst> : R600_3OP < @@ -629,19 +617,28 @@ class CUBE_Common inst> : InstR600 < class EXP_IEEE_Common inst> : R600_1OP < inst, "EXP_IEEE", - []> { - let AMDILOp = AMDILInst.EXP_f32; -} + [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))] +>; class FLT_TO_INT_Common inst> : R600_1OP < - inst, "FLT_TO_INT", []> { - let AMDILOp = AMDILInst.FTOI; -} + inst, "FLT_TO_INT", + [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))] +>; class INT_TO_FLT_Common inst> : R600_1OP < - inst, "INT_TO_FLT", []> { - let AMDILOp = AMDILInst.ITOF; -} + inst, "INT_TO_FLT", + [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))] +>; + +class FLT_TO_UINT_Common inst> : R600_1OP < + inst, "FLT_TO_UINT", + [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))] +>; + +class UINT_TO_FLT_Common inst> : R600_1OP < + inst, "UINT_TO_FLT", + [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))] +>; class LOG_CLAMPED_Common inst> : R600_1OP < inst, "LOG_CLAMPED", @@ -650,44 +647,38 @@ class LOG_CLAMPED_Common inst> : R600_1OP < class LOG_IEEE_Common inst> : R600_1OP < inst, "LOG_IEEE", - []> { - let AMDILOp = AMDILInst.LOG_f32; -} + [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))] +>; class LSHL_Common inst> : R600_2OP < inst, "LSHL $dst, $src0, $src1", - [] >{ - let AMDILOp = AMDILInst.SHL_i32; -} + [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))] +>; class LSHR_Common inst> : R600_2OP < inst, "LSHR $dst, $src0, $src1", - [] >{ - let AMDILOp = AMDILInst.USHR_i32; -} + [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))] +>; class ASHR_Common inst> : R600_2OP < inst, "ASHR $dst, $src0, $src1", - [] >{ - let AMDILOp = AMDILInst.SHR_i32; -} + [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))] +>; class MULHI_INT_Common inst> : R600_2OP < inst, "MULHI_INT $dst, $src0, $src1", - [] >{ - let AMDILOp = AMDILInst.SMULHI_i32; -} + [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))] +>; class MULHI_UINT_Common inst> : R600_2OP < - inst, "MULHI $dst, $src0, $src1", - [] + inst, "MULHI $dst, $src0, $src1", + [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))] >; class MULLO_INT_Common inst> : R600_2OP < inst, "MULLO_INT $dst, $src0, $src1", - [] >{ - let AMDILOp = AMDILInst.SMUL_i32; -} + [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))] +>; class MULLO_UINT_Common inst> : R600_2OP < inst, "MULLO_UINT $dst, $src0, $src1", @@ -701,13 +692,12 @@ class RECIP_CLAMPED_Common inst> : R600_1OP < class RECIP_IEEE_Common inst> : R600_1OP < inst, "RECIP_IEEE", - [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> { - let AMDILOp = AMDILInst.RSQ_f32; -} + [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))] +>; class RECIP_UINT_Common inst> : R600_1OP < inst, "RECIP_INT $dst, $src", - [] + [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))] >; class RECIPSQRT_CLAMPED_Common inst> : R600_1OP < @@ -721,16 +711,12 @@ class RECIPSQRT_IEEE_Common inst> : R600_1OP < >; class SIN_Common inst> : R600_1OP < - inst, "SIN", - []>{ - let AMDILOp = AMDILInst.SIN_f32; + inst, "SIN", []>{ let Trig = 1; } class COS_Common inst> : R600_1OP < - inst, "COS", - []> { - let AMDILOp = AMDILInst.COS_f32; + inst, "COS", []> { let Trig = 1; } @@ -758,8 +744,6 @@ class TGSI_LIT_Z_Common ; def MULADD_r600 : MULADD_Common<0x10>; def CNDE_r600 : CNDE_Common<0x18>; @@ -776,6 +760,8 @@ let Gen = AMDGPUGen.R600 in { def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; + def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; + def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; def SIN_r600 : SIN_Common<0x6E>; def COS_r600 : COS_Common<0x6F>; def ASHR_r600 : ASHR_Common<0x70>; @@ -785,9 +771,7 @@ let Gen = AMDGPUGen.R600 in { def MULHI_INT_r600 : MULHI_INT_Common<0x74>; def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; - def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>; - -} // End AMDGPUGen.R600 + def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; def DIV_r600 : DIV_Common; def POW_r600 : POW_Common; @@ -796,29 +780,130 @@ let Gen = AMDGPUGen.R600 in { } -/* ----------------- */ -/* R700+ Trig helper */ -/* ----------------- */ - -/* -class TRIG_HELPER_r700 : Pat < - (trig_inst R600_Reg32:$src), - (trig_inst (fmul R600_Reg32:$src, (PI)))) +// Helper pattern for normalizing inputs to triginomic instructions for R700+ +// cards. +class TRIG_eg : Pat< + (intr R600_Reg32:$src), + (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src)) >; -*/ -/* ---------------------- */ -/* Evergreen Instructions */ -/* ---------------------- */ +//===----------------------------------------------------------------------===// +// R700 Only instructions +//===----------------------------------------------------------------------===// + +let Predicates = [isR700] in { + def SIN_r700 : SIN_Common<0x6E>; + def COS_r700 : COS_Common<0x6F>; + // R700 normalizes inputs to SIN/COS the same as EG + def : TRIG_eg ; + def : TRIG_eg ; +} + +//===----------------------------------------------------------------------===// +// Evergreen Only instructions +//===----------------------------------------------------------------------===// let Predicates = [isEG] in { + +def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; + +def MULLO_INT_eg : MULLO_INT_Common<0x8F>; +def MULHI_INT_eg : MULHI_INT_Common<0x90>; +def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; +def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; +def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; + +} // End Predicates = [isEG] + +/* ------------------------------- */ +/* Evergreen / Cayman Instructions */ +/* ------------------------------- */ + +let Predicates = [isEGorCayman] in { + + // BFE_UINT - bit_extract, an optimization for mask and shift + // Src0 = Input + // Src1 = Offset + // Src2 = Width + // + // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) + // + // Example Usage: + // (Offset, Width) + // + // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 + // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 + // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 + // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 + def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", + [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0, + R600_Reg32:$src1, + R600_Reg32:$src2))], + VecALU + >; -let Gen = AMDGPUGen.EG in { + def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", + [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1, + R600_Reg32:$src2))], + VecALU + >; -def RAT_WRITE_CACHELESS_eg : - EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr, - R600_TReg32_X:$index_gpr, i32imm:$rat_id), ""> + def MULADD_eg : MULADD_Common<0x14>; + def ASHR_eg : ASHR_Common<0x15>; + def LSHR_eg : LSHR_Common<0x16>; + def LSHL_eg : LSHL_Common<0x17>; + def CNDE_eg : CNDE_Common<0x19>; + def CNDGT_eg : CNDGT_Common<0x1A>; + def CNDGE_eg : CNDGE_Common<0x1B>; + def MUL_LIT_eg : MUL_LIT_Common<0x1F>; + def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; + def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; + def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; + def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; + def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; + def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; + def SIN_eg : SIN_Common<0x8D>; + def COS_eg : COS_Common<0x8E>; + def DOT4_eg : DOT4_Common<0xBE>; + def CUBE_eg : CUBE_Common<0xC0>; + + def DIV_eg : DIV_Common; + def POW_eg : POW_Common; + def SSG_eg : SSG_Common; + def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common; + + def : TRIG_eg ; + def : TRIG_eg ; + + def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { + let Pattern = []; + } + + def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; + + def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { + let Pattern = []; + } + + def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; + + def : Pat<(fp_to_sint R600_Reg32:$src), + (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>; + + def : Pat<(fp_to_uint R600_Reg32:$src), + (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>; + +//===----------------------------------------------------------------------===// +// Memory read/write instructions +//===----------------------------------------------------------------------===// + +let usesCustomInserter = 1 in { + +def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs), + (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr), + "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr", + [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]> { let RIM = 0; /* XXX: Have a separate instruction for non-indexed writes. */ @@ -835,43 +920,57 @@ def RAT_WRITE_CACHELESS_eg : let BARRIER = 1; } -def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst), - (ins R600_TReg32_X:$src, i32imm:$buffer_id), - "VTX_READ_eg $dst, $src", []> -{ -/* - bits<7> DST_GPR; - bits<7> SRC_GPR; - bits<8> BUFFER_ID; -*/ - /* If any of these field below need to be calculated at compile time, and - * a ins operand for them and move them to the list of operands above. */ +} // End usesCustomInserter = 1 - /* XXX: This instruction is manual encoded, so none of these values are used. - */ -/* - bits<5> VC_INST = 0; //VC_INST_FETCH - bits<2> FETCH_TYPE = 2; - bits<1> FETCH_WHOLE_QUAD = 1; - bits<1> SRC_REL = 0; - bits<2> SRC_SEL_X = 0; - bits<6> MEGA_FETCH_COUNT = 4; -*/ -/* +// Floating point global_store +def : Pat < + (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr), + (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr) +>; - bits<1> DST_REL = 0; - bits<3> DST_SEL_X = 0; - bits<3> DST_SEL_Y = 7; //Masked - bits<3> DST_SEL_Z = 7; //Masked - bits<3> DST_SEL_W = 7; //Masked - bits<1> USE_CONST_FIELDS = 1; //Masked - bits<6> DATA_FORMAT = 0; - bits<2> NUM_FORMAT_ALL = 0; - bits<1> FORMAT_COMP_ALL = 0; - bits<1> SRF_MODE_ALL = 0; -*/ +class VTX_READ_eg buffer_id, dag outs, list pattern> + : InstR600ISA { -/* + // Operands + bits<7> DST_GPR; + bits<7> SRC_GPR; + + // Static fields + bits<5> VC_INST = 0; + bits<2> FETCH_TYPE = 2; + bits<1> FETCH_WHOLE_QUAD = 0; + bits<8> BUFFER_ID = buffer_id; + bits<1> SRC_REL = 0; + // XXX: We can infer this field based on the SRC_GPR. This would allow us + // to store vertex addresses in any channel, not just X. + bits<2> SRC_SEL_X = 0; + bits<6> MEGA_FETCH_COUNT; + bits<1> DST_REL = 0; + bits<3> DST_SEL_X; + bits<3> DST_SEL_Y; + bits<3> DST_SEL_Z; + bits<3> DST_SEL_W; + // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, + // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, + // however, based on my testing if USE_CONST_FIELDS is set, then all + // these fields need to be set to 0. + bits<1> USE_CONST_FIELDS = 0; + bits<6> DATA_FORMAT; + bits<2> NUM_FORMAT_ALL = 1; + bits<1> FORMAT_COMP_ALL = 0; + bits<1> SRF_MODE_ALL = 0; + + // LLVM can only encode 64-bit instructions, so these fields are manually + // encoded in R600CodeEmitter + // + // bits<16> OFFSET; + // bits<2> ENDIAN_SWAP = 0; + // bits<1> CONST_BUF_NO_STRIDE = 0; + // bits<1> MEGA_FETCH = 0; + // bits<1> ALT_CONST = 0; + // bits<2> BUFFER_INDEX_MODE = 0; + + // VTX_WORD0 let Inst{4-0} = VC_INST; let Inst{6-5} = FETCH_TYPE; let Inst{7} = FETCH_WHOLE_QUAD; @@ -880,18 +979,11 @@ def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst), let Inst{23} = SRC_REL; let Inst{25-24} = SRC_SEL_X; let Inst{31-26} = MEGA_FETCH_COUNT; -*/ - /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you - * from statically setting bits > 31. This field will be set by - * getMachineValueOp which can set bits > 31. - */ -// let Inst{32-38} = DST_GPR; - /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */ - -/* + // VTX_WORD1_GPR + let Inst{38-32} = DST_GPR; let Inst{39} = DST_REL; - let Inst{40} = 0; //Reserved + let Inst{40} = 0; // Reserved let Inst{43-41} = DST_SEL_X; let Inst{46-44} = DST_SEL_Y; let Inst{49-47} = DST_SEL_Z; @@ -901,90 +993,78 @@ def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst), let Inst{61-60} = NUM_FORMAT_ALL; let Inst{62} = FORMAT_COMP_ALL; let Inst{63} = SRF_MODE_ALL; -*/ -} - - - -} // End AMDGPUGen.EG -/* XXX: Need to convert PTR to rat_id */ -/* -def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr), - (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), - (f32 R600_Reg32:$value), - sel_x), - (f32 ZERO), 0, R600_Reg32:$ptr)>; -*/ -class VTX_Param_Read_Pattern : Pat < - (vt (load_param ADDRParam:$mem)), - (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>; - -def : VTX_Param_Read_Pattern ; -def : VTX_Param_Read_Pattern ; + // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding + // is done in R600CodeEmitter + // + // Inst{79-64} = OFFSET; + // Inst{81-80} = ENDIAN_SWAP; + // Inst{82} = CONST_BUF_NO_STRIDE; + // Inst{83} = MEGA_FETCH; + // Inst{84} = ALT_CONST; + // Inst{86-85} = BUFFER_INDEX_MODE; + // Inst{95-86} = 0; Reserved + + // VTX_WORD3 (Padding) + // + // Inst{127-96} = 0; +} -} // End isEG Predicate +class VTX_READ_32_eg buffer_id, list pattern> + : VTX_READ_eg { -/* ------------------------------- */ -/* Evergreen / Cayman Instructions */ -/* ------------------------------- */ + let MEGA_FETCH_COUNT = 4; + let DST_SEL_X = 0; + let DST_SEL_Y = 7; // Masked + let DST_SEL_Z = 7; // Masked + let DST_SEL_W = 7; // Masked + let DATA_FORMAT = 0xD; // COLOR_32 +} -let Predicates = [isEGorCayman] in { - -class TRIG_eg : Pat< - (intr R600_Reg32:$src), - (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src)) +def VTX_READ_PARAM_eg : VTX_READ_32_eg <0, + [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))] >; -let Gen = AMDGPUGen.EG_CAYMAN in { - - def MULADD_eg : MULADD_Common<0x14>; - def ASHR_eg : ASHR_Common<0x15>; - def LSHR_eg : LSHR_Common<0x16>; - def LSHL_eg : LSHL_Common<0x17>; - def CNDE_eg : CNDE_Common<0x19>; - def CNDGT_eg : CNDGT_Common<0x1A>; - def CNDGE_eg : CNDGE_Common<0x1B>; - def MUL_LIT_eg : MUL_LIT_Common<0x1F>; - def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>; - def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; - def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; - def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; - def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; - def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; - def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; - def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; - def SIN_eg : SIN_Common<0x8D>; - def COS_eg : COS_Common<0x8E>; - def MULLO_INT_eg : MULLO_INT_Common<0x8F>; - def MULHI_INT_eg : MULHI_INT_Common<0x90>; - def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; - def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; - def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; - def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; - def DOT4_eg : DOT4_Common<0xBE>; - def CUBE_eg : CUBE_Common<0xC0>; +def VTX_READ_GLOBAL_eg : VTX_READ_32_eg <1, + [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))] +>; -} // End AMDGPUGen.EG_CAYMAN +class VTX_READ_128_eg buffer_id, list pattern> + : VTX_READ_eg { - def DIV_eg : DIV_Common; - def POW_eg : POW_Common; - def SSG_eg : SSG_Common; - def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common; + let MEGA_FETCH_COUNT = 16; + let DST_SEL_X = 0; + let DST_SEL_Y = 1; + let DST_SEL_Z = 2; + let DST_SEL_W = 3; + let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 +} - def : TRIG_eg ; - def : TRIG_eg ; +def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1, + [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))] +>; } let Predicates = [isCayman] in { -let Gen = AMDGPUGen.CAYMAN in { +let isVector = 1 in { + +def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; - /* XXX: I'm not sure if this opcode is correct. */ - def RECIP_UINT_cm : RECIP_UINT_Common<0x77>; +def MULLO_INT_cm : MULLO_INT_Common<0x8F>; +def MULHI_INT_cm : MULHI_INT_Common<0x90>; +def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; +def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; -} // End AMDGPUGen.CAYMAN +} // End isVector = 1 + +// RECIP_UINT emulation for Cayman +def : Pat < + (AMDGPUurecip R600_Reg32:$src0), + (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)), + (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000))) +>; } // End isCayman @@ -1102,24 +1182,36 @@ def TXD_SHADOW: AMDGPUShaderInst < } // End isCodeGenOnly = 1 +def CLAMP_R600 : CLAMP ; +def FABS_R600 : FABS; +def FNEG_R600 : FNEG; +let usesCustomInserter = 1 in { -let isPseudo = 1 in { - -def LOAD_VTX : AMDGPUShaderInst < - (outs R600_Reg32:$dst), - (ins MEMri:$mem), - "LOAD_VTX", - [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))] +def MASK_WRITE : AMDGPUShaderInst < + (outs), + (ins R600_Reg32:$src), + "MASK_WRITE $src", + [] >; - -} //End isPseudo +} // End usesCustomInserter = 1 //===----------------------------------------------------------------------===// // ISel Patterns //===----------------------------------------------------------------------===// +// KIL Patterns +def KILP : Pat < + (int_AMDGPU_kilp), + (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) +>; + +def KIL : Pat < + (int_AMDGPU_kill R600_Reg32:$src0), + (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0))) +>; + // SGT Reverse args def : Pat < (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT), @@ -1196,4 +1288,13 @@ def : Insert_Element ; def : Insert_Element ; def : Insert_Element ; +def : Vector_Build ; +def : Vector_Build ; + +// bitconvert patterns + +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + } // End isR600toCayman Predicate