X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeon%2Fr600_pipe_common.h;h=f40f8faefc2288d9fd2c24a91cbbf539e406d223;hb=4c5efc40f4980eb0faa7c0ad73413c51c43c1911;hp=0982d1d1b3d51f801ba6d2fda76f2c80c7b2eb27;hpb=092756f23fee2ea2a98a230d020132a45a6e1e94;p=mesa.git diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 0982d1d1b3d..f40f8faefc2 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -1,5 +1,6 @@ /* * Copyright 2013 Advanced Micro Devices, Inc. + * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -45,26 +46,16 @@ #include "util/u_threaded_context.h" struct u_log_context; - -#define ATI_VENDOR_ID 0x1002 +struct si_screen; +struct si_context; #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0) #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1) #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2) #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4) - -#define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0) -/* Pipeline & streamout query controls. */ -#define R600_CONTEXT_START_PIPELINE_STATS (1u << 1) -#define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2) -#define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3) -#define R600_CONTEXT_PRIVATE_FLAG (1u << 4) - -/* special primitive types */ -#define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX - -#define R600_NOT_QUERY 0xffffffff +#define R600_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5) +#define R600_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6) /* Debug flags. */ enum { @@ -87,7 +78,6 @@ enum { /* Shader compiler options (with no effect on the shader cache): */ DBG_CHECK_IR, - DBG_PRECOMPILE, DBG_NIR, DBG_MONOLITHIC_SHADERS, DBG_NO_OPT_VARIANT, @@ -121,6 +111,7 @@ enum { DBG_NO_DCC_FB, DBG_NO_DCC_MSAA, DBG_DCC_MSAA, + DBG_NO_FMASK, /* Tests: */ DBG_TEST_DMA, @@ -136,26 +127,11 @@ enum { #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024 -enum r600_coherency { - R600_COHERENCY_NONE, /* no cache flushes needed */ - R600_COHERENCY_SHADER, - R600_COHERENCY_CB_META, -}; - -#ifdef PIPE_ARCH_BIG_ENDIAN -#define R600_BIG_ENDIAN 1 -#else -#define R600_BIG_ENDIAN 0 -#endif - struct r600_common_context; struct r600_perfcounters; struct tgsi_shader_info; struct r600_qbo_state; -void si_radeon_shader_binary_init(struct ac_shader_binary *b); -void si_radeon_shader_binary_clean(struct ac_shader_binary *b); - /* Only 32-bit buffer allocations are supported, gallium doesn't support more * at the moment. */ @@ -386,104 +362,13 @@ struct r600_memory_object { uint32_t offset; }; -struct r600_common_screen { - struct pipe_screen b; - struct radeon_winsys *ws; - enum radeon_family family; - enum chip_class chip_class; - struct radeon_info info; - uint64_t debug_flags; - bool has_rbplus; /* if RB+ registers exist */ - bool rbplus_allowed; /* if RB+ is allowed */ - bool dcc_msaa_allowed; - - struct disk_cache *disk_shader_cache; - - struct slab_parent_pool pool_transfers; - - /* Texture filter settings. */ - int force_aniso; /* -1 = disabled */ - - /* Auxiliary context. Mainly used to initialize resources. - * It must be locked prior to using and flushed before unlocking. */ - struct pipe_context *aux_context; - mtx_t aux_context_lock; - - /* This must be in the screen, because UE4 uses one context for - * compilation and another one for rendering. - */ - unsigned num_compilations; - /* Along with ST_DEBUG=precompile, this should show if applications - * are loading shaders on demand. This is a monotonic counter. - */ - unsigned num_shaders_created; - unsigned num_shader_cache_hits; - - /* GPU load thread. */ - mtx_t gpu_load_mutex; - thrd_t gpu_load_thread; - union r600_mmio_counters mmio_counters; - volatile unsigned gpu_load_stop_thread; /* bool */ - - char renderer_string[100]; - - /* Performance counters. */ - struct r600_perfcounters *perfcounters; - - /* If pipe_screen wants to recompute and re-emit the framebuffer, - * sampler, and image states of all contexts, it should atomically - * increment this. - * - * Each context will compare this with its own last known value of - * the counter before drawing and re-emit the states accordingly. - */ - unsigned dirty_tex_counter; - - /* Atomically increment this counter when an existing texture's - * metadata is enabled or disabled in a way that requires changing - * contexts' compressed texture binding masks. - */ - unsigned compressed_colortex_counter; - - struct { - /* Context flags to set so that all writes from earlier jobs - * in the CP are seen by L2 clients. - */ - unsigned cp_to_L2; - - /* Context flags to set so that all writes from earlier jobs - * that end in L2 are seen by CP. - */ - unsigned L2_to_cp; - - /* Context flags to set so that all writes from earlier - * compute jobs are seen by L2 clients. - */ - unsigned compute_to_L2; - } barrier_flags; - - void (*query_opaque_metadata)(struct r600_common_screen *rscreen, - struct r600_texture *rtex, - struct radeon_bo_metadata *md); - - void (*apply_opaque_metadata)(struct r600_common_screen *rscreen, - struct r600_texture *rtex, - struct radeon_bo_metadata *md); -}; - /* This encapsulates a state or an operation which can emitted into the GPU * command stream. */ struct r600_atom { - void (*emit)(struct r600_common_context *ctx, struct r600_atom *state); + void (*emit)(struct si_context *ctx, struct r600_atom *state); unsigned short id; }; -struct r600_ring { - struct radeon_winsys_cs *cs; - void (*flush)(void *ctx, unsigned flags, - struct pipe_fence_handle **fence); -}; - /* Saved CS data for debugging features. */ struct radeon_saved_cs { uint32_t *ib; @@ -496,16 +381,17 @@ struct radeon_saved_cs { struct r600_common_context { struct pipe_context b; /* base class */ - struct r600_common_screen *screen; + struct si_screen *screen; struct radeon_winsys *ws; struct radeon_winsys_ctx *ctx; enum radeon_family family; enum chip_class chip_class; - struct r600_ring gfx; - struct r600_ring dma; + struct radeon_winsys_cs *gfx_cs; + struct radeon_winsys_cs *dma_cs; struct pipe_fence_handle *last_gfx_fence; struct pipe_fence_handle *last_sdma_fence; struct r600_resource *eop_bug_scratch; + struct u_upload_mgr *cached_gtt_allocator; unsigned num_gfx_cs_flushes; unsigned initial_gfx_cs_size; unsigned gpu_reset_counter; @@ -594,147 +480,76 @@ struct r600_common_context { void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst, uint64_t offset, uint64_t size, unsigned value); - - void (*blit_decompress_depth)(struct pipe_context *ctx, - struct r600_texture *texture, - struct r600_texture *staging, - unsigned first_level, unsigned last_level, - unsigned first_layer, unsigned last_layer, - unsigned first_sample, unsigned last_sample); - - void (*decompress_dcc)(struct pipe_context *ctx, - struct r600_texture *rtex); - - /* Reallocate the buffer and update all resource bindings where - * the buffer is bound, including all resource descriptors. */ - void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf); - - /* Update all resource bindings where the buffer is bound, including - * all resource descriptors. This is invalidate_buffer without - * the invalidation. */ - void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf, - uint64_t old_gpu_address); - - /* Enable or disable occlusion queries. */ - void (*set_occlusion_query_state)(struct pipe_context *ctx, - bool old_enable, - bool old_perfect_enable); - - void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st); - - /* This ensures there is enough space in the command stream. */ - void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw, - bool include_draw_vbo); - - void (*set_atom_dirty)(struct r600_common_context *ctx, - struct r600_atom *atom, bool dirty); - - void (*check_vm_faults)(struct r600_common_context *ctx, - struct radeon_saved_cs *saved, - enum ring_type ring); }; /* r600_buffer_common.c */ -bool si_rings_is_buffer_referenced(struct r600_common_context *ctx, +bool si_rings_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf, enum radeon_bo_usage usage); -void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx, +void *si_buffer_map_sync_with_rings(struct si_context *sctx, struct r600_resource *resource, unsigned usage); -void si_buffer_subdata(struct pipe_context *ctx, - struct pipe_resource *buffer, - unsigned usage, unsigned offset, - unsigned size, const void *data); -void si_init_resource_fields(struct r600_common_screen *rscreen, +void si_init_resource_fields(struct si_screen *sscreen, struct r600_resource *res, uint64_t size, unsigned alignment); -bool si_alloc_resource(struct r600_common_screen *rscreen, +bool si_alloc_resource(struct si_screen *sscreen, struct r600_resource *res); -struct pipe_resource *si_buffer_create(struct pipe_screen *screen, - const struct pipe_resource *templ, - unsigned alignment); struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags, unsigned usage, unsigned size, unsigned alignment); -struct pipe_resource * -si_buffer_from_user_memory(struct pipe_screen *screen, - const struct pipe_resource *templ, - void *user_memory); -void si_invalidate_resource(struct pipe_context *ctx, - struct pipe_resource *resource); void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst, struct pipe_resource *src); +void si_init_screen_buffer_functions(struct si_screen *sscreen); +void si_init_buffer_functions(struct si_context *sctx); /* r600_common_pipe.c */ -void si_gfx_write_event_eop(struct r600_common_context *ctx, - unsigned event, unsigned event_flags, - unsigned data_sel, - struct r600_resource *buf, uint64_t va, - uint32_t new_fence, unsigned query_type); -unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen); -void si_gfx_wait_fence(struct r600_common_context *ctx, - uint64_t va, uint32_t ref, uint32_t mask); -bool si_common_screen_init(struct r600_common_screen *rscreen, - struct radeon_winsys *ws); -void si_destroy_common_screen(struct r600_common_screen *rscreen); -void si_preflush_suspend_features(struct r600_common_context *ctx); -void si_postflush_resume_features(struct r600_common_context *ctx); bool si_common_context_init(struct r600_common_context *rctx, - struct r600_common_screen *rscreen, + struct si_screen *sscreen, unsigned context_flags); void si_common_context_cleanup(struct r600_common_context *rctx); -bool si_can_dump_shader(struct r600_common_screen *rscreen, - unsigned processor); -bool si_extra_shader_checks(struct r600_common_screen *rscreen, - unsigned processor); -void si_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value); -struct pipe_resource *si_resource_create_common(struct pipe_screen *screen, - const struct pipe_resource *templ); -void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw, - struct r600_resource *dst, struct r600_resource *src); -void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, - struct radeon_saved_cs *saved, bool get_buffer_list); -void si_clear_saved_cs(struct radeon_saved_cs *saved); bool si_check_device_reset(struct r600_common_context *rctx); /* r600_gpu_load.c */ -void si_gpu_load_kill_thread(struct r600_common_screen *rscreen); -uint64_t si_begin_counter(struct r600_common_screen *rscreen, unsigned type); -unsigned si_end_counter(struct r600_common_screen *rscreen, unsigned type, +void si_gpu_load_kill_thread(struct si_screen *sscreen); +uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type); +unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin); /* r600_perfcounters.c */ -void si_perfcounters_destroy(struct r600_common_screen *rscreen); +void si_perfcounters_destroy(struct si_screen *sscreen); /* r600_query.c */ -void si_init_screen_query_functions(struct r600_common_screen *rscreen); -void si_init_query_functions(struct r600_common_context *rctx); -void si_suspend_queries(struct r600_common_context *ctx); -void si_resume_queries(struct r600_common_context *ctx); +void si_init_screen_query_functions(struct si_screen *sscreen); +void si_init_query_functions(struct si_context *sctx); +void si_suspend_queries(struct si_context *sctx); +void si_resume_queries(struct si_context *sctx); /* r600_texture.c */ -bool si_prepare_for_dma_blit(struct r600_common_context *rctx, +bool si_prepare_for_dma_blit(struct si_context *sctx, struct r600_texture *rdst, unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz, struct r600_texture *rsrc, unsigned src_level, const struct pipe_box *src_box); -void si_texture_get_fmask_info(struct r600_common_screen *rscreen, +void si_texture_get_fmask_info(struct si_screen *sscreen, struct r600_texture *rtex, unsigned nr_samples, struct r600_fmask_info *out); -void si_texture_get_cmask_info(struct r600_common_screen *rscreen, +void si_texture_get_cmask_info(struct si_screen *sscreen, struct r600_texture *rtex, struct r600_cmask_info *out); +void si_eliminate_fast_color_clear(struct si_context *sctx, + struct r600_texture *rtex); +void si_texture_discard_cmask(struct si_screen *sscreen, + struct r600_texture *rtex); bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture, struct r600_texture **staging); -void si_print_texture_info(struct r600_common_screen *rscreen, +void si_print_texture_info(struct si_screen *sscreen, struct r600_texture *rtex, struct u_log_context *log); struct pipe_resource *si_texture_create(struct pipe_screen *screen, const struct pipe_resource *templ); @@ -743,7 +558,7 @@ bool vi_dcc_formats_compatible(enum pipe_format format1, bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level, enum pipe_format view_format); -void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx, +void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex, unsigned level, enum pipe_format view_format); @@ -753,7 +568,7 @@ struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe, unsigned width0, unsigned height0, unsigned width, unsigned height); unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap); -void vi_separate_dcc_try_enable(struct r600_common_context *rctx, +void vi_separate_dcc_try_enable(struct si_context *sctx, struct r600_texture *tex); void vi_separate_dcc_start_query(struct pipe_context *ctx, struct r600_texture *tex); @@ -761,10 +576,10 @@ void vi_separate_dcc_stop_query(struct pipe_context *ctx, struct r600_texture *tex); void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx, struct r600_texture *tex); -bool si_texture_disable_dcc(struct r600_common_context *rctx, +bool si_texture_disable_dcc(struct si_context *sctx, struct r600_texture *rtex); -void si_init_screen_texture_functions(struct r600_common_screen *rscreen); -void si_init_context_texture_functions(struct r600_common_context *rctx); +void si_init_screen_texture_functions(struct si_screen *sscreen); +void si_init_context_texture_functions(struct si_context *sctx); /* Inline helpers. */ @@ -787,96 +602,13 @@ r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res) pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b); } -static inline void -r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r) -{ - struct r600_common_context *rctx = (struct r600_common_context *)ctx; - struct r600_resource *res = (struct r600_resource *)r; - - if (res) { - /* Add memory usage for need_gfx_cs_space */ - rctx->vram += res->vram_usage; - rctx->gtt += res->gart_usage; - } -} - -#define SQ_TEX_XY_FILTER_POINT 0x00 -#define SQ_TEX_XY_FILTER_BILINEAR 0x01 -#define SQ_TEX_XY_FILTER_ANISO_POINT 0x02 -#define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03 - -static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso) -{ - if (filter == PIPE_TEX_FILTER_LINEAR) - return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR - : SQ_TEX_XY_FILTER_BILINEAR; - else - return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT - : SQ_TEX_XY_FILTER_POINT; -} - -static inline unsigned r600_tex_aniso_filter(unsigned filter) -{ - if (filter < 2) - return 0; - if (filter < 4) - return 1; - if (filter < 8) - return 2; - if (filter < 16) - return 3; - return 4; -} - -static inline enum radeon_bo_priority -r600_get_sampler_view_priority(struct r600_resource *res) -{ - if (res->b.b.target == PIPE_BUFFER) - return RADEON_PRIO_SAMPLER_BUFFER; - - if (res->b.b.nr_samples > 1) - return RADEON_PRIO_SAMPLER_TEXTURE_MSAA; - - return RADEON_PRIO_SAMPLER_TEXTURE; -} - -static inline bool -r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler) -{ - return (stencil_sampler && tex->can_sample_s) || - (!stencil_sampler && tex->can_sample_z); -} - static inline bool vi_dcc_enabled(struct r600_texture *tex, unsigned level) { return tex->dcc_offset && level < tex->surface.num_dcc_levels; } -static inline bool -r600_htile_enabled(struct r600_texture *tex, unsigned level) -{ - return tex->htile_offset && level == 0; -} - -static inline bool -vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level) -{ - assert(!tex->tc_compatible_htile || tex->htile_offset); - return tex->tc_compatible_htile && level == 0; -} - -#define COMPUTE_DBG(rscreen, fmt, args...) \ - do { \ - if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \ - } while (0); - #define R600_ERR(fmt, args...) \ fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args) -static inline int S_FIXED(float value, unsigned frac_bits) -{ - return value * (1 << frac_bits); -} - #endif