X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeon%2Fradeon_video.c;h=bb1173e8005df33f9c482f62d2bca6e7bc281686;hb=5c2c1f0a2d5cec771b6cbfadf43f44a632ff57fc;hp=17e9a59d81d768d4a22e8570998cb141d9e6d093;hpb=07c65b85eada8dd34019763b6e82ed4257a9b4a6;p=mesa.git diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index 17e9a59d81d..bb1173e8005 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -25,12 +25,6 @@ * **************************************************************************/ -/* - * Authors: - * Christian König - * - */ - #include #include "util/u_memory.h" @@ -39,13 +33,12 @@ #include "vl/vl_defines.h" #include "vl/vl_video_buffer.h" -#include "../../winsys/radeon/drm/radeon_winsys.h" -#include "r600_pipe_common.h" +#include "radeonsi/si_pipe.h" #include "radeon_video.h" #include "radeon_vce.h" /* generate an stream handle */ -unsigned rvid_alloc_stream_handle() +unsigned si_vid_alloc_stream_handle() { static unsigned counter = 0; unsigned stream_handle = 0; @@ -60,48 +53,48 @@ unsigned rvid_alloc_stream_handle() } /* create a buffer in the winsys */ -bool rvid_create_buffer(struct radeon_winsys *ws, struct rvid_buffer *buffer, - unsigned size, enum radeon_bo_domain domain, - enum radeon_bo_flag flags) +bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer, + unsigned size, unsigned usage) { - buffer->domain = domain; - buffer->flags = flags; + memset(buffer, 0, sizeof(*buffer)); + buffer->usage = usage; - buffer->buf = ws->buffer_create(ws, size, 4096, false, domain, flags); - if (!buffer->buf) - return false; + /* Hardware buffer placement restrictions require the kernel to be + * able to move buffers around individually, so request a + * non-sub-allocated buffer. + */ + buffer->res = r600_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED, + usage, size)); - buffer->cs_handle = ws->buffer_get_cs_handle(buffer->buf); - if (!buffer->cs_handle) - return false; - - return true; + return buffer->res != NULL; } /* destroy a buffer */ -void rvid_destroy_buffer(struct rvid_buffer *buffer) +void si_vid_destroy_buffer(struct rvid_buffer *buffer) { - pb_reference(&buffer->buf, NULL); - buffer->cs_handle = NULL; + r600_resource_reference(&buffer->res, NULL); } /* reallocate a buffer, preserving its content */ -bool rvid_resize_buffer(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, - struct rvid_buffer *new_buf, unsigned new_size) +bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs, + struct rvid_buffer *new_buf, unsigned new_size) { - unsigned bytes = MIN2(new_buf->buf->size, new_size); + struct si_screen *sscreen = (struct si_screen *)screen; + struct radeon_winsys* ws = sscreen->ws; + unsigned bytes = MIN2(new_buf->res->buf->size, new_size); struct rvid_buffer old_buf = *new_buf; void *src = NULL, *dst = NULL; - if (!rvid_create_buffer(ws, new_buf, new_size, new_buf->domain, - new_buf->flags)) + if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage)) goto error; - src = ws->buffer_map(old_buf.cs_handle, cs, PIPE_TRANSFER_READ); + src = ws->buffer_map(old_buf.res->buf, cs, + PIPE_TRANSFER_READ | RADEON_TRANSFER_TEMPORARY); if (!src) goto error; - dst = ws->buffer_map(new_buf->cs_handle, cs, PIPE_TRANSFER_WRITE); + dst = ws->buffer_map(new_buf->res->buf, cs, + PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY); if (!dst) goto error; @@ -111,38 +104,37 @@ bool rvid_resize_buffer(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, dst += bytes; memset(dst, 0, new_size); } - ws->buffer_unmap(new_buf->cs_handle); - ws->buffer_unmap(old_buf.cs_handle); - rvid_destroy_buffer(&old_buf); + ws->buffer_unmap(new_buf->res->buf); + ws->buffer_unmap(old_buf.res->buf); + si_vid_destroy_buffer(&old_buf); return true; error: if (src) - ws->buffer_unmap(old_buf.cs_handle); - rvid_destroy_buffer(new_buf); + ws->buffer_unmap(old_buf.res->buf); + si_vid_destroy_buffer(new_buf); *new_buf = old_buf; return false; } /* clear the buffer with zeros */ -void rvid_clear_buffer(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, struct rvid_buffer* buffer) +void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer) { - void *ptr = ws->buffer_map(buffer->cs_handle, cs, PIPE_TRANSFER_WRITE); - if (!ptr) - return; + struct si_context *sctx = (struct si_context*)context; - memset(ptr, 0, buffer->buf->size); - ws->buffer_unmap(buffer->cs_handle); + si_sdma_clear_buffer(sctx, &buffer->res->b.b, 0, buffer->res->buf->size, 0); + context->flush(context, NULL, 0); } /** * join surfaces into the same buffer with identical tiling params * sumup their sizes and replace the backend buffers with a single bo */ -void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind, - struct pb_buffer** buffers[VL_NUM_COMPONENTS], - struct radeon_surface *surfaces[VL_NUM_COMPONENTS]) +void si_vid_join_surfaces(struct si_context *sctx, + struct pb_buffer** buffers[VL_NUM_COMPONENTS], + struct radeon_surf *surfaces[VL_NUM_COMPONENTS]) { + struct radeon_winsys *ws = sctx->ws;; unsigned best_tiling, best_wh, off; unsigned size, alignment; struct pb_buffer *pb; @@ -154,11 +146,13 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind, if (!surfaces[i]) continue; - /* choose the smallest bank w/h for now */ - wh = surfaces[i]->bankw * surfaces[i]->bankh; - if (wh < best_wh) { - best_wh = wh; - best_tiling = i; + if (sctx->chip_class < GFX9) { + /* choose the smallest bank w/h for now */ + wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh; + if (wh < best_wh) { + best_wh = wh; + best_tiling = i; + } } } @@ -166,17 +160,25 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind, if (!surfaces[i]) continue; - /* copy the tiling parameters */ - surfaces[i]->bankw = surfaces[best_tiling]->bankw; - surfaces[i]->bankh = surfaces[best_tiling]->bankh; - surfaces[i]->mtilea = surfaces[best_tiling]->mtilea; - surfaces[i]->tile_split = surfaces[best_tiling]->tile_split; - /* adjust the texture layer offsets */ - off = align(off, surfaces[i]->bo_alignment); - for (j = 0; j < Elements(surfaces[i]->level); ++j) - surfaces[i]->level[j].offset += off; - off += surfaces[i]->bo_size; + off = align(off, surfaces[i]->surf_alignment); + + if (sctx->chip_class < GFX9) { + /* copy the tiling parameters */ + surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw; + surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh; + surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea; + surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split; + + for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j) + surfaces[i]->u.legacy.level[j].offset += off; + } else { + surfaces[i]->u.gfx9.surf_offset += off; + for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j) + surfaces[i]->u.gfx9.offset[j] += off; + } + + off += surfaces[i]->surf_size; } for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) { @@ -194,7 +196,8 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind, /* TODO: 2D tiling workaround */ alignment *= 2; - pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM, 0); + pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, + RADEON_FLAG_GTT_WC); if (!pb) return; @@ -207,122 +210,3 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind, pb_reference(&pb, NULL); } - -int rvid_get_video_param(struct pipe_screen *screen, - enum pipe_video_profile profile, - enum pipe_video_entrypoint entrypoint, - enum pipe_video_cap param) -{ - struct r600_common_screen *rscreen = (struct r600_common_screen *)screen; - - if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) { - switch (param) { - case PIPE_VIDEO_CAP_SUPPORTED: - return u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC && - rvce_is_fw_version_supported(rscreen); - case PIPE_VIDEO_CAP_NPOT_TEXTURES: - return 1; - case PIPE_VIDEO_CAP_MAX_WIDTH: - return 2048; - case PIPE_VIDEO_CAP_MAX_HEIGHT: - return 1152; - case PIPE_VIDEO_CAP_PREFERED_FORMAT: - return PIPE_FORMAT_NV12; - case PIPE_VIDEO_CAP_PREFERS_INTERLACED: - return false; - case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: - return false; - case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: - return true; - default: - return 0; - } - } - - /* UVD 2.x limits */ - if (rscreen->family < CHIP_PALM) { - enum pipe_video_format codec = u_reduce_video_profile(profile); - switch (param) { - case PIPE_VIDEO_CAP_SUPPORTED: - /* no support for MPEG4 */ - return codec != PIPE_VIDEO_FORMAT_MPEG4 && - /* FIXME: VC-1 simple/main profile is broken */ - profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE && - profile != PIPE_VIDEO_PROFILE_VC1_MAIN; - case PIPE_VIDEO_CAP_PREFERS_INTERLACED: - case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: - /* and MPEG2 only with shaders */ - return codec != PIPE_VIDEO_FORMAT_MPEG12; - default: - break; - } - } - - switch (param) { - case PIPE_VIDEO_CAP_SUPPORTED: - switch (u_reduce_video_profile(profile)) { - case PIPE_VIDEO_FORMAT_MPEG12: - case PIPE_VIDEO_FORMAT_MPEG4: - case PIPE_VIDEO_FORMAT_MPEG4_AVC: - return entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE; - case PIPE_VIDEO_FORMAT_VC1: - /* FIXME: VC-1 simple/main profile is broken */ - return profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED && - entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE; - default: - return false; - } - case PIPE_VIDEO_CAP_NPOT_TEXTURES: - return 1; - case PIPE_VIDEO_CAP_MAX_WIDTH: - return 2048; - case PIPE_VIDEO_CAP_MAX_HEIGHT: - return 1152; - case PIPE_VIDEO_CAP_PREFERED_FORMAT: - return PIPE_FORMAT_NV12; - case PIPE_VIDEO_CAP_PREFERS_INTERLACED: - return true; - case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: - return true; - case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: - return true; - case PIPE_VIDEO_CAP_MAX_LEVEL: - switch (profile) { - case PIPE_VIDEO_PROFILE_MPEG1: - return 0; - case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE: - case PIPE_VIDEO_PROFILE_MPEG2_MAIN: - return 3; - case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE: - return 3; - case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE: - return 5; - case PIPE_VIDEO_PROFILE_VC1_SIMPLE: - return 1; - case PIPE_VIDEO_PROFILE_VC1_MAIN: - return 2; - case PIPE_VIDEO_PROFILE_VC1_ADVANCED: - return 4; - case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE: - case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN: - case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH: - return 41; - default: - return 0; - } - default: - return 0; - } -} - -boolean rvid_is_format_supported(struct pipe_screen *screen, - enum pipe_format format, - enum pipe_video_profile profile, - enum pipe_video_entrypoint entrypoint) -{ - /* we can only handle this one with UVD */ - if (profile != PIPE_VIDEO_PROFILE_UNKNOWN) - return format == PIPE_FORMAT_NV12; - - return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint); -}