X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeon%2Fradeon_video.c;h=d80410d51b3fa4ffab54226cb950381d58906352;hb=0447e8e59e9cbce196138d46dc0be07b7ed392a0;hp=de8e11cd8e28195581fb497025b75df2ae853757;hpb=13cb41f666212ed50a7939a37a373b4431a84033;p=mesa.git diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index de8e11cd8e2..d80410d51b3 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -25,12 +25,6 @@ * **************************************************************************/ -/* - * Authors: - * Christian König - * - */ - #include #include "util/u_memory.h" @@ -39,14 +33,12 @@ #include "vl/vl_defines.h" #include "vl/vl_video_buffer.h" -#include "r600_pipe_common.h" +#include "radeonsi/si_pipe.h" #include "radeon_video.h" #include "radeon_vce.h" -#define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) - /* generate an stream handle */ -unsigned rvid_alloc_stream_handle() +unsigned si_vid_alloc_stream_handle() { static unsigned counter = 0; unsigned stream_handle = 0; @@ -61,8 +53,8 @@ unsigned rvid_alloc_stream_handle() } /* create a buffer in the winsys */ -bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer, - unsigned size, unsigned usage) +bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer, + unsigned size, unsigned usage) { memset(buffer, 0, sizeof(*buffer)); buffer->usage = usage; @@ -72,29 +64,29 @@ bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer, * non-sub-allocated buffer. */ buffer->res = (struct r600_resource *) - pipe_buffer_create(screen, PIPE_BIND_CUSTOM | PIPE_BIND_SHARED, + pipe_buffer_create(screen, PIPE_BIND_SHARED, usage, size); return buffer->res != NULL; } /* destroy a buffer */ -void rvid_destroy_buffer(struct rvid_buffer *buffer) +void si_vid_destroy_buffer(struct rvid_buffer *buffer) { r600_resource_reference(&buffer->res, NULL); } /* reallocate a buffer, preserving its content */ -bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs, - struct rvid_buffer *new_buf, unsigned new_size) +bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs, + struct rvid_buffer *new_buf, unsigned new_size) { - struct r600_common_screen *rscreen = (struct r600_common_screen *)screen; - struct radeon_winsys* ws = rscreen->ws; + struct si_screen *sscreen = (struct si_screen *)screen; + struct radeon_winsys* ws = sscreen->ws; unsigned bytes = MIN2(new_buf->res->buf->size, new_size); struct rvid_buffer old_buf = *new_buf; void *src = NULL, *dst = NULL; - if (!rvid_create_buffer(screen, new_buf, new_size, new_buf->usage)) + if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage)) goto error; src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ); @@ -113,24 +105,24 @@ bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs, } ws->buffer_unmap(new_buf->res->buf); ws->buffer_unmap(old_buf.res->buf); - rvid_destroy_buffer(&old_buf); + si_vid_destroy_buffer(&old_buf); return true; error: if (src) ws->buffer_unmap(old_buf.res->buf); - rvid_destroy_buffer(new_buf); + si_vid_destroy_buffer(new_buf); *new_buf = old_buf; return false; } /* clear the buffer with zeros */ -void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer) +void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer) { struct r600_common_context *rctx = (struct r600_common_context*)context; - rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size, - 0, R600_COHERENCY_NONE); + rctx->dma_clear_buffer(context, &buffer->res->b.b, 0, + buffer->res->buf->size, 0); context->flush(context, NULL, 0); } @@ -138,26 +130,31 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer) * join surfaces into the same buffer with identical tiling params * sumup their sizes and replace the backend buffers with a single bo */ -void rvid_join_surfaces(struct radeon_winsys* ws, - struct pb_buffer** buffers[VL_NUM_COMPONENTS], - struct radeon_surf *surfaces[VL_NUM_COMPONENTS]) +void si_vid_join_surfaces(struct r600_common_context *rctx, + struct pb_buffer** buffers[VL_NUM_COMPONENTS], + struct radeon_surf *surfaces[VL_NUM_COMPONENTS]) { + struct radeon_winsys* ws; unsigned best_tiling, best_wh, off; unsigned size, alignment; struct pb_buffer *pb; unsigned i, j; + ws = rctx->ws; + for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) { unsigned wh; if (!surfaces[i]) continue; - /* choose the smallest bank w/h for now */ - wh = surfaces[i]->bankw * surfaces[i]->bankh; - if (wh < best_wh) { - best_wh = wh; - best_tiling = i; + if (rctx->chip_class < GFX9) { + /* choose the smallest bank w/h for now */ + wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh; + if (wh < best_wh) { + best_wh = wh; + best_tiling = i; + } } } @@ -165,17 +162,25 @@ void rvid_join_surfaces(struct radeon_winsys* ws, if (!surfaces[i]) continue; - /* copy the tiling parameters */ - surfaces[i]->bankw = surfaces[best_tiling]->bankw; - surfaces[i]->bankh = surfaces[best_tiling]->bankh; - surfaces[i]->mtilea = surfaces[best_tiling]->mtilea; - surfaces[i]->tile_split = surfaces[best_tiling]->tile_split; - /* adjust the texture layer offsets */ - off = align(off, surfaces[i]->bo_alignment); - for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j) - surfaces[i]->level[j].offset += off; - off += surfaces[i]->bo_size; + off = align(off, surfaces[i]->surf_alignment); + + if (rctx->chip_class < GFX9) { + /* copy the tiling parameters */ + surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw; + surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh; + surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea; + surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split; + + for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j) + surfaces[i]->u.legacy.level[j].offset += off; + } else { + surfaces[i]->u.gfx9.surf_offset += off; + for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j) + surfaces[i]->u.gfx9.offset[j] += off; + } + + off += surfaces[i]->surf_size; } for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) { @@ -193,7 +198,8 @@ void rvid_join_surfaces(struct radeon_winsys* ws, /* TODO: 2D tiling workaround */ alignment *= 2; - pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0); + pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, + RADEON_FLAG_GTT_WC); if (!pb) return; @@ -206,134 +212,3 @@ void rvid_join_surfaces(struct radeon_winsys* ws, pb_reference(&pb, NULL); } - -int rvid_get_video_param(struct pipe_screen *screen, - enum pipe_video_profile profile, - enum pipe_video_entrypoint entrypoint, - enum pipe_video_cap param) -{ - struct r600_common_screen *rscreen = (struct r600_common_screen *)screen; - enum pipe_video_format codec = u_reduce_video_profile(profile); - struct radeon_info info; - - rscreen->ws->query_info(rscreen->ws, &info); - - if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) { - switch (param) { - case PIPE_VIDEO_CAP_SUPPORTED: - return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC && - rvce_is_fw_version_supported(rscreen); - case PIPE_VIDEO_CAP_NPOT_TEXTURES: - return 1; - case PIPE_VIDEO_CAP_MAX_WIDTH: - return (rscreen->family < CHIP_TONGA) ? 2048 : 4096; - case PIPE_VIDEO_CAP_MAX_HEIGHT: - return (rscreen->family < CHIP_TONGA) ? 1152 : 2304; - case PIPE_VIDEO_CAP_PREFERED_FORMAT: - return PIPE_FORMAT_NV12; - case PIPE_VIDEO_CAP_PREFERS_INTERLACED: - return false; - case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: - return false; - case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: - return true; - case PIPE_VIDEO_CAP_STACKED_FRAMES: - return (rscreen->family < CHIP_TONGA) ? 1 : 2; - default: - return 0; - } - } - - switch (param) { - case PIPE_VIDEO_CAP_SUPPORTED: - switch (codec) { - case PIPE_VIDEO_FORMAT_MPEG12: - return profile != PIPE_VIDEO_PROFILE_MPEG1; - case PIPE_VIDEO_FORMAT_MPEG4: - /* no support for MPEG4 on older hw */ - return rscreen->family >= CHIP_PALM; - case PIPE_VIDEO_FORMAT_MPEG4_AVC: - if ((rscreen->family == CHIP_POLARIS10 || - rscreen->family == CHIP_POLARIS11) && - info.uvd_fw_version < UVD_FW_1_66_16 ) { - RVID_ERR("POLARIS10/11 firmware version need to be updated.\n"); - return false; - } - return true; - case PIPE_VIDEO_FORMAT_VC1: - return true; - case PIPE_VIDEO_FORMAT_HEVC: - /* Carrizo only supports HEVC Main */ - if (rscreen->family >= CHIP_STONEY) - return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN || - profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10); - else if (rscreen->family >= CHIP_CARRIZO) - return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN; - default: - return false; - } - case PIPE_VIDEO_CAP_NPOT_TEXTURES: - return 1; - case PIPE_VIDEO_CAP_MAX_WIDTH: - return (rscreen->family < CHIP_TONGA) ? 2048 : 4096; - case PIPE_VIDEO_CAP_MAX_HEIGHT: - return (rscreen->family < CHIP_TONGA) ? 1152 : 4096; - case PIPE_VIDEO_CAP_PREFERED_FORMAT: - return PIPE_FORMAT_NV12; - case PIPE_VIDEO_CAP_PREFERS_INTERLACED: - case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: - if (rscreen->family < CHIP_PALM) { - /* MPEG2 only with shaders and no support for - interlacing on R6xx style UVD */ - return codec != PIPE_VIDEO_FORMAT_MPEG12 && - rscreen->family > CHIP_RV770; - } else { - if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC) - return false; //The firmware doesn't support interlaced HEVC. - return true; - } - case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: - return true; - case PIPE_VIDEO_CAP_MAX_LEVEL: - switch (profile) { - case PIPE_VIDEO_PROFILE_MPEG1: - return 0; - case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE: - case PIPE_VIDEO_PROFILE_MPEG2_MAIN: - return 3; - case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE: - return 3; - case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE: - return 5; - case PIPE_VIDEO_PROFILE_VC1_SIMPLE: - return 1; - case PIPE_VIDEO_PROFILE_VC1_MAIN: - return 2; - case PIPE_VIDEO_PROFILE_VC1_ADVANCED: - return 4; - case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE: - case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN: - case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH: - return (rscreen->family < CHIP_TONGA) ? 41 : 52; - case PIPE_VIDEO_PROFILE_HEVC_MAIN: - case PIPE_VIDEO_PROFILE_HEVC_MAIN_10: - return 186; - default: - return 0; - } - default: - return 0; - } -} - -boolean rvid_is_format_supported(struct pipe_screen *screen, - enum pipe_format format, - enum pipe_video_profile profile, - enum pipe_video_entrypoint entrypoint) -{ - /* we can only handle this one with UVD */ - if (profile != PIPE_VIDEO_PROFILE_UNKNOWN) - return format == PIPE_FORMAT_NV12; - - return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint); -}