X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fcik_sdma.c;h=99285a6de17687786be5aacb4444d45a87d1424f;hb=36f21017237ab536db74c84e0f778d3a58271c75;hp=698f8f6bbb2894747dc38df2aff6483999f973a5;hpb=d4c0ad4de8c4eeec1cc0478b12ce542e9a7faa0f;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c index 698f8f6bbb2..99285a6de17 100644 --- a/src/gallium/drivers/radeonsi/cik_sdma.c +++ b/src/gallium/drivers/radeonsi/cik_sdma.c @@ -28,20 +28,26 @@ #include "sid.h" #include "si_pipe.h" -static void cik_sdma_do_copy_buffer(struct si_context *ctx, - struct pipe_resource *dst, - struct pipe_resource *src, - uint64_t dst_offset, - uint64_t src_offset, - uint64_t size) +static void cik_sdma_copy_buffer(struct si_context *ctx, + struct pipe_resource *dst, + struct pipe_resource *src, + uint64_t dst_offset, + uint64_t src_offset, + uint64_t size) { struct radeon_winsys_cs *cs = ctx->b.dma.cs; unsigned i, ncopy, csize; - struct r600_resource *rdst = (struct r600_resource*)dst; - struct r600_resource *rsrc = (struct r600_resource*)src; + struct r600_resource *rdst = r600_resource(dst); + struct r600_resource *rsrc = r600_resource(src); + + /* Mark the buffer range of destination as valid (initialized), + * so that transfer_map knows it should wait for the GPU when mapping + * that range. */ + util_range_add(&rdst->valid_buffer_range, dst_offset, + dst_offset + size); - dst_offset += r600_resource(dst)->gpu_address; - src_offset += r600_resource(src)->gpu_address; + dst_offset += rdst->gpu_address; + src_offset += rsrc->gpu_address; ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE); r600_need_dma_space(&ctx->b, ncopy * 7, rdst, rsrc); @@ -51,7 +57,7 @@ static void cik_sdma_do_copy_buffer(struct si_context *ctx, radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, CIK_SDMA_COPY_SUB_OPCODE_LINEAR, 0)); - radeon_emit(cs, csize); + radeon_emit(cs, ctx->b.chip_class >= GFX9 ? csize - 1 : csize); radeon_emit(cs, 0); /* src/dst endian swap */ radeon_emit(cs, src_offset); radeon_emit(cs, src_offset >> 32); @@ -63,25 +69,6 @@ static void cik_sdma_do_copy_buffer(struct si_context *ctx, } } -static void cik_sdma_copy_buffer(struct si_context *ctx, - struct pipe_resource *dst, - struct pipe_resource *src, - uint64_t dst_offset, - uint64_t src_offset, - uint64_t size) -{ - struct r600_resource *rdst = (struct r600_resource*)dst; - - /* Mark the buffer range of destination as valid (initialized), - * so that transfer_map knows it should wait for the GPU when mapping - * that range. */ - util_range_add(&rdst->valid_buffer_range, dst_offset, - dst_offset + size); - - cik_sdma_do_copy_buffer(ctx, dst, src, dst_offset, src_offset, size); - r600_dma_emit_wait_idle(&ctx->b); -} - static void cik_sdma_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst, uint64_t offset, @@ -93,7 +80,8 @@ static void cik_sdma_clear_buffer(struct pipe_context *ctx, unsigned i, ncopy, csize; struct r600_resource *rdst = r600_resource(dst); - if (!cs || offset % 4 != 0 || size % 4 != 0) { + if (!cs || offset % 4 != 0 || size % 4 != 0 || + dst->flags & PIPE_RESOURCE_FLAG_SPARSE) { ctx->clear_buffer(ctx, dst, offset, size, &clear_value, 4); return; } @@ -116,11 +104,10 @@ static void cik_sdma_clear_buffer(struct pipe_context *ctx, radeon_emit(cs, offset); radeon_emit(cs, offset >> 32); radeon_emit(cs, clear_value); - radeon_emit(cs, csize); + radeon_emit(cs, sctx->b.chip_class >= GFX9 ? csize - 1 : csize); offset += csize; size -= csize; } - r600_dma_emit_wait_idle(&sctx->b); } static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w) @@ -134,8 +121,8 @@ static unsigned encode_tile_info(struct si_context *sctx, bool set_bpp) { struct radeon_info *info = &sctx->screen->b.info; - unsigned tile_index = tex->surface.tiling_index[level]; - unsigned macro_tile_index = tex->surface.macro_tile_index; + unsigned tile_index = tex->surface.u.legacy.tiling_index[level]; + unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index; unsigned tile_mode = info->si_tile_mode_array[tile_index]; unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index]; @@ -143,7 +130,7 @@ static unsigned encode_tile_info(struct si_context *sctx, (G_009910_ARRAY_MODE(tile_mode) << 3) | (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) | /* Non-depth modes don't have TILE_SPLIT set. */ - ((util_logbase2(tex->surface.tile_split >> 6)) << 11) | + ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) | (G_009990_BANK_WIDTH(macro_tile_mode) << 15) | (G_009990_BANK_HEIGHT(macro_tile_mode) << 18) | (G_009990_NUM_BANKS(macro_tile_mode) << 21) | @@ -164,21 +151,21 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, struct r600_texture *rdst = (struct r600_texture*)dst; unsigned bpp = rdst->surface.bpe; uint64_t dst_address = rdst->resource.gpu_address + - rdst->surface.level[dst_level].offset; + rdst->surface.u.legacy.level[dst_level].offset; uint64_t src_address = rsrc->resource.gpu_address + - rsrc->surface.level[src_level].offset; - unsigned dst_mode = rdst->surface.level[dst_level].mode; - unsigned src_mode = rsrc->surface.level[src_level].mode; - unsigned dst_tile_index = rdst->surface.tiling_index[dst_level]; - unsigned src_tile_index = rsrc->surface.tiling_index[src_level]; + rsrc->surface.u.legacy.level[src_level].offset; + unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode; + unsigned src_mode = rsrc->surface.u.legacy.level[src_level].mode; + unsigned dst_tile_index = rdst->surface.u.legacy.tiling_index[dst_level]; + unsigned src_tile_index = rsrc->surface.u.legacy.tiling_index[src_level]; unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index]; unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index]; unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode); unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode); - unsigned dst_pitch = rdst->surface.level[dst_level].nblk_x; - unsigned src_pitch = rsrc->surface.level[src_level].nblk_x; - uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp; - uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp; + unsigned dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x; + unsigned src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x; + uint64_t dst_slice_pitch = rdst->surface.u.legacy.level[dst_level].slice_size / bpp; + uint64_t src_slice_pitch = rsrc->surface.u.legacy.level[src_level].slice_size / bpp; unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0, dst_level, rdst->surface.blk_w); unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0, @@ -196,10 +183,10 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, assert(src_level <= src->last_level); assert(dst_level <= dst->last_level); - assert(rdst->surface.level[dst_level].offset + + assert(rdst->surface.u.legacy.level[dst_level].offset + dst_slice_pitch * bpp * (dstz + src_box->depth) <= rdst->resource.buf->size); - assert(rsrc->surface.level[src_level].offset + + assert(rsrc->surface.u.legacy.level[src_level].offset + src_slice_pitch * bpp * (srcz + src_box->depth) <= rsrc->resource.buf->size); @@ -263,8 +250,6 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16)); radeon_emit(cs, (copy_depth - 1)); } - - r600_dma_emit_wait_idle(&sctx->b); return true; } @@ -366,14 +351,14 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, * starts reading from an address preceding linear_address!!! */ start_linear_address = - linear->surface.level[linear_level].offset + + linear->surface.u.legacy.level[linear_level].offset + bpp * (linear_z * linear_slice_pitch + linear_y * linear_pitch + linear_x); start_linear_address -= (int)(bpp * (tiled_x % granularity)); end_linear_address = - linear->surface.level[linear_level].offset + + linear->surface.u.legacy.level[linear_level].offset + bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch + (linear_y + copy_height - 1) * linear_pitch + (linear_x + copy_width)); @@ -395,7 +380,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, copy_width_aligned % xalign == 0 && tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING && /* check if everything fits into the bitfields */ - tiled->surface.tile_split <= 4096 && + tiled->surface.u.legacy.tile_split <= 4096 && pitch_tile_max < (1 << 11) && slice_tile_max < (1 << 22) && linear_pitch <= (1 << 14) && @@ -429,8 +414,6 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16)); radeon_emit(cs, (copy_depth - 1)); } - - r600_dma_emit_wait_idle(&sctx->b); return true; } } @@ -441,15 +424,15 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, /* check if these fit into the bitfields */ src_address % 256 == 0 && dst_address % 256 == 0 && - rsrc->surface.tile_split <= 4096 && - rdst->surface.tile_split <= 4096 && + rsrc->surface.u.legacy.tile_split <= 4096 && + rdst->surface.u.legacy.tile_split <= 4096 && dstx % 8 == 0 && dsty % 8 == 0 && srcx % 8 == 0 && srcy % 8 == 0 && - /* this can either be equal, or display->rotated (VI only) */ + /* this can either be equal, or display->rotated (VI+ only) */ (src_micro_mode == dst_micro_mode || - (sctx->b.chip_class == VI && + (sctx->b.chip_class >= VI && src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING && dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) { assert(src_pitch % 8 == 0); @@ -527,8 +510,6 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, ((copy_height_aligned - 8) << 16)); radeon_emit(cs, (copy_depth - 1)); } - - r600_dma_emit_wait_idle(&sctx->b); return true; } } @@ -546,7 +527,9 @@ static void cik_sdma_copy(struct pipe_context *ctx, { struct si_context *sctx = (struct si_context *)ctx; - if (!sctx->b.dma.cs) + if (!sctx->b.dma.cs || + src->flags & PIPE_RESOURCE_FLAG_SPARSE || + dst->flags & PIPE_RESOURCE_FLAG_SPARSE) goto fallback; if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { @@ -554,7 +537,8 @@ static void cik_sdma_copy(struct pipe_context *ctx, return; } - if (cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz, + if ((sctx->b.chip_class == CIK || sctx->b.chip_class == VI) && + cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz, src, src_level, src_box)) return;