X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_compute.c;h=07b1293049f72bf11ea8e2223d33e293ce9eb1c2;hb=525e5dc4eda5740ba44fcf8ffb1652b0c896ffbd;hp=a08ed7d65f5ef1ed88e1c6587a7376afe79a6934;hpb=77b05cc42df29472a7852b90575a19e8991815cd;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index a08ed7d65f5..07b1293049f 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -28,6 +28,7 @@ #include "util/u_memory.h" #include "util/u_upload_mgr.h" +#include "ac_rtld.h" #include "amd_kernel_code_t.h" #include "si_build_pm4.h" #include "si_compute.h" @@ -61,8 +62,30 @@ static const amd_kernel_code_t *si_compute_get_code_object( if (!program->use_code_object_v2) { return NULL; } - return (const amd_kernel_code_t*) - (program->shader.binary.code + symbol_offset); + + struct ac_rtld_binary rtld; + if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){ + .info = &program->screen->info, + .shader_type = MESA_SHADER_COMPUTE, + .num_parts = 1, + .elf_ptrs = &program->shader.binary.elf_buffer, + .elf_sizes = &program->shader.binary.elf_size })) + return NULL; + + const amd_kernel_code_t *result = NULL; + const char *text; + size_t size; + if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size)) + goto out; + + if (symbol_offset + sizeof(amd_kernel_code_t) > size) + goto out; + + result = (const amd_kernel_code_t*)(text + symbol_offset); + +out: + ac_rtld_close(&rtld); + return result; } static void code_object_to_config(const amd_kernel_code_t *code_object, @@ -141,16 +164,15 @@ static void si_create_compute_state_async(void *job, int thread_index) si_shader_cache_load_shader(sscreen, ir_binary, shader)) { mtx_unlock(&sscreen->shader_cache_mutex); - si_shader_dump_stats_for_shader_db(shader, debug); - si_shader_dump(sscreen, shader, debug, PIPE_SHADER_COMPUTE, - stderr, true); + si_shader_dump_stats_for_shader_db(sscreen, shader, debug); + si_shader_dump(sscreen, shader, debug, stderr, true); - if (si_shader_binary_upload(sscreen, shader)) + if (!si_shader_binary_upload(sscreen, shader, 0)) program->shader.compilation_failed = true; } else { mtx_unlock(&sscreen->shader_cache_mutex); - if (si_shader_create(sscreen, compiler, &program->shader, debug)) { + if (!si_shader_create(sscreen, compiler, &program->shader, debug)) { program->shader.compilation_failed = true; if (program->ir_type == PIPE_SHADER_IR_TGSI) @@ -167,10 +189,16 @@ static void si_create_compute_state_async(void *job, int thread_index) shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) | - S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) | S_00B848_DX10_CLAMP(1) | + S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) | + S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) | S_00B848_FLOAT_MODE(shader->config.float_mode); + if (program->screen->info.chip_class < GFX10) { + shader->config.rsrc1 |= + S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8); + } + shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) | S_00B84C_SCRATCH_EN(scratch_enabled) | @@ -237,25 +265,22 @@ static void *si_create_compute_state( header = cso->prog; code = cso->prog + sizeof(struct pipe_llvm_program_header); - ac_elf_read(code, header->num_bytes, &program->shader.binary); - if (program->use_code_object_v2) { - const amd_kernel_code_t *code_object = - si_compute_get_code_object(program, 0); - code_object_to_config(code_object, &program->shader.config); - if (program->shader.binary.reloc_count != 0) { - fprintf(stderr, "Error: %d unsupported relocations\n", - program->shader.binary.reloc_count); - FREE(program); - return NULL; - } - } else { - ac_shader_binary_read_config(&program->shader.binary, - &program->shader.config, 0, false); + program->shader.binary.elf_size = header->num_bytes; + program->shader.binary.elf_buffer = malloc(header->num_bytes); + if (!program->shader.binary.elf_buffer) { + FREE(program); + return NULL; } - si_shader_dump(sctx->screen, &program->shader, &sctx->debug, - PIPE_SHADER_COMPUTE, stderr, true); - if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) { + memcpy((void *)program->shader.binary.elf_buffer, code, header->num_bytes); + + const amd_kernel_code_t *code_object = + si_compute_get_code_object(program, 0); + code_object_to_config(code_object, &program->shader.config); + + si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true); + if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) { fprintf(stderr, "LLVM failed to upload shader\n"); + free((void *)program->shader.binary.elf_buffer); FREE(program); return NULL; } @@ -322,7 +347,8 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf uint64_t bc_va; radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); - /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */ + /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1, + * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */ radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); @@ -336,6 +362,9 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf S_00B858_SH1_CU_EN(0xffff)); } + if (sctx->chip_class >= GFX10) + radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0); + /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID * and is now per pipe, so it should be handled in the * kernel if we want to use something other than the default value, @@ -390,9 +419,7 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx, if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) { uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; - si_shader_apply_scratch_relocs(shader, scratch_va); - - if (si_shader_binary_upload(sctx->screen, shader)) + if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) return false; si_resource_reference(&shader->scratch_bo, @@ -423,11 +450,7 @@ static bool si_switch_compute_shader(struct si_context *sctx, unsigned lds_blocks; config = &inline_config; - if (code_object) { - code_object_to_config(code_object, config); - } else { - ac_shader_binary_read_config(&shader->binary, config, offset, false); - } + code_object_to_config(code_object, config); lds_blocks = config->lds_size; /* XXX: We are over allocating LDS. For GFX6, the shader reports @@ -749,50 +772,26 @@ static void si_setup_tgsi_user_data(struct si_context *sctx, } } -unsigned si_get_compute_resource_limits(struct si_screen *sscreen, - unsigned waves_per_threadgroup, - unsigned max_waves_per_sh, - unsigned threadgroups_per_cu) -{ - unsigned compute_resource_limits = - S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0); - - if (sscreen->info.chip_class >= GFX7) { - unsigned num_cu_per_se = sscreen->info.num_good_compute_units / - sscreen->info.max_se; - - /* Force even distribution on all SIMDs in CU if the workgroup - * size is 64. This has shown some good improvements if # of CUs - * per SE is not a multiple of 4. - */ - if (num_cu_per_se % 4 && waves_per_threadgroup == 1) - compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1); - - assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8); - compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) | - S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1); - } else { - /* GFX6 */ - if (max_waves_per_sh) { - unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16); - compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16); - } - } - return compute_resource_limits; -} - static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info) { struct si_screen *sscreen = sctx->screen; struct radeon_cmdbuf *cs = sctx->gfx_cs; bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off; + unsigned threads_per_threadgroup = + info->block[0] * info->block[1] * info->block[2]; unsigned waves_per_threadgroup = - DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64); + DIV_ROUND_UP(threads_per_threadgroup, 64); + unsigned threadgroups_per_cu = 1; + + if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1) + threadgroups_per_cu = 2; radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, - si_get_compute_resource_limits(sscreen, waves_per_threadgroup, - sctx->cs_max_waves_per_sh, 1)); + ac_get_compute_resource_limits(&sscreen->info, + waves_per_threadgroup, + sctx->cs_max_waves_per_sh, + threadgroups_per_cu)); unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | @@ -903,7 +902,7 @@ static void si_launch_grid( /* Indirect buffers use TC L2 on GFX9, but not older hw. */ if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) { - sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + sctx->flags |= SI_CONTEXT_WB_L2; si_resource(info->indirect)->TC_L2_dirty = false; } } @@ -921,7 +920,7 @@ static void si_launch_grid( } if (sctx->flags) - si_emit_cache_flush(sctx); + sctx->emit_cache_flush(sctx); if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc))