X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_cp_dma.c;h=d1b44b894b14337d3355df2fdf80ef873a77e454;hb=50fde5b20801a82bd95f14301707c32cf5df38a2;hp=e85bb9b1acf9200f07bd440f2a90f981a54c4ed2;hpb=203ef19f48b6d983dfba383b6a8fcebfe0a02aee;p=mesa.git

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index e85bb9b1acf..d1b44b894b1 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -25,12 +25,6 @@
 #include "si_pipe.h"
 #include "sid.h"
 
-/* Recommended maximum sizes for optimal performance.
- * Fall back to compute or SDMA if the size is greater.
- */
-#define CP_DMA_COPY_PERF_THRESHOLD	(64 * 1024) /* copied from Vulkan */
-#define CP_DMA_CLEAR_PERF_THRESHOLD	(32 * 1024) /* guess (clear is much slower) */
-
 /* Set this if you want the ME to wait until CP DMA is done.
  * It should be set on the last CP DMA packet. */
 #define CP_DMA_SYNC		(1 << 0)
@@ -39,8 +33,10 @@
  * packet. It's for preventing a read-after-write (RAW) hazard between two
  * CP DMA packets. */
 #define CP_DMA_RAW_WAIT		(1 << 1)
+#define CP_DMA_DST_IS_GDS	(1 << 2)
 #define CP_DMA_CLEAR		(1 << 3)
 #define CP_DMA_PFP_SYNC_ME	(1 << 4)
+#define CP_DMA_SRC_IS_GDS	(1 << 5)
 
 /* The max number of bytes that can be copied per packet. */
 static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
@@ -58,15 +54,14 @@ static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
  * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
  * clear value.
  */
-static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
-			   uint64_t src_va, unsigned size, unsigned flags,
-			   enum si_cache_policy cache_policy)
+static void si_emit_cp_dma(struct si_context *sctx, struct radeon_cmdbuf *cs,
+			   uint64_t dst_va, uint64_t src_va, unsigned size,
+			   unsigned flags, enum si_cache_policy cache_policy)
 {
-	struct radeon_cmdbuf *cs = sctx->gfx_cs;
 	uint32_t header = 0, command = 0;
 
 	assert(size <= cp_dma_max_byte_count(sctx));
-	assert(sctx->chip_class != SI || cache_policy == L2_BYPASS);
+	assert(sctx->chip_class != GFX6 || cache_policy == L2_BYPASS);
 
 	if (sctx->chip_class >= GFX9)
 		command |= S_414_BYTE_COUNT_GFX9(size);
@@ -90,19 +85,29 @@ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
 	if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
 	    src_va == dst_va) {
 		header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
-	} else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
+	} else if (flags & CP_DMA_DST_IS_GDS) {
+		header |= S_411_DST_SEL(V_411_GDS);
+		/* GDS increments the address, not CP. */
+		command |= S_414_DAS(V_414_REGISTER) |
+			   S_414_DAIC(V_414_NO_INCREMENT);
+	} else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) {
 		header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2) |
 			  S_500_DST_CACHE_POLICY(cache_policy == L2_STREAM);
 	}
 
 	if (flags & CP_DMA_CLEAR) {
 		header |= S_411_SRC_SEL(V_411_DATA);
-	} else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS) {
+	} else if (flags & CP_DMA_SRC_IS_GDS) {
+		header |= S_411_SRC_SEL(V_411_GDS);
+		/* Both of these are required for GDS. It does increment the address. */
+		command |= S_414_SAS(V_414_REGISTER) |
+			   S_414_SAIC(V_414_NO_INCREMENT);
+	} else if (sctx->chip_class >= GFX7 && cache_policy != L2_BYPASS) {
 		header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
 			  S_500_SRC_CACHE_POLICY(cache_policy == L2_STREAM);
 	}
 
-	if (sctx->chip_class >= CIK) {
+	if (sctx->chip_class >= GFX7) {
 		radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
 		radeon_emit(cs, header);
 		radeon_emit(cs, src_va);	/* SRC_ADDR_LO [31:0] */
@@ -126,7 +131,7 @@ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
 	 * indices. If we wanted to execute CP DMA in PFP, this packet
 	 * should precede it.
 	 */
-	if (flags & CP_DMA_PFP_SYNC_ME) {
+	if (sctx->has_graphics && flags & CP_DMA_PFP_SYNC_ME) {
 		radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 		radeon_emit(cs, 0);
 	}
@@ -140,36 +145,7 @@ void si_cp_dma_wait_for_idle(struct si_context *sctx)
 	 * DMA request, however, the CP will see the sync flag and still wait
 	 * for all DMAs to complete.
 	 */
-	si_emit_cp_dma(sctx, 0, 0, 0, CP_DMA_SYNC, L2_BYPASS);
-}
-
-static unsigned get_flush_flags(struct si_context *sctx, enum si_coherency coher,
-				enum si_cache_policy cache_policy)
-{
-	switch (coher) {
-	default:
-	case SI_COHERENCY_NONE:
-		return 0;
-	case SI_COHERENCY_SHADER:
-		assert(sctx->chip_class != SI || cache_policy == L2_BYPASS);
-		return SI_CONTEXT_INV_SMEM_L1 |
-		       SI_CONTEXT_INV_VMEM_L1 |
-		       (cache_policy == L2_BYPASS ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
-	case SI_COHERENCY_CB_META:
-		assert(sctx->chip_class >= GFX9 ? cache_policy != L2_BYPASS :
-						  cache_policy == L2_BYPASS);
-		return SI_CONTEXT_FLUSH_AND_INV_CB;
-	}
-}
-
-static enum si_cache_policy get_cache_policy(struct si_context *sctx,
-					     enum si_coherency coher)
-{
-	if ((sctx->chip_class >= GFX9 && coher == SI_COHERENCY_CB_META) ||
-	    (sctx->chip_class >= CIK && coher == SI_COHERENCY_SHADER))
-		return L2_LRU;
-
-	return L2_BYPASS;
+	si_emit_cp_dma(sctx, sctx->gfx_cs, 0, 0, 0, CP_DMA_SYNC, L2_BYPASS);
 }
 
 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
@@ -186,7 +162,8 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
 
 	if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 		/* Count memory usage in so that need_cs_space can take it into account. */
-		si_context_add_resource_size(sctx, dst);
+		if (dst)
+			si_context_add_resource_size(sctx, dst);
 		if (src)
 			si_context_add_resource_size(sctx, src);
 	}
@@ -196,12 +173,13 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
 
 	/* This must be done after need_cs_space. */
 	if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
-		radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
-					  r600_resource(dst),
-					  RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
+		if (dst)
+			radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
+						  si_resource(dst),
+						  RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
 		if (src)
 			radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
-						  r600_resource(src),
+						  si_resource(src),
 						  RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
 	}
 
@@ -209,9 +187,10 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
 	 * Also wait for the previous CP DMA operations.
 	 */
 	if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->flags)
-		si_emit_cache_flush(sctx);
+		sctx->emit_cache_flush(sctx);
 
-	if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first)
+	if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first &&
+	    !(*packet_flags & CP_DMA_CLEAR))
 		*packet_flags |= CP_DMA_RAW_WAIT;
 
 	*is_first = false;
@@ -228,13 +207,13 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
 	}
 }
 
-void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
-			    uint64_t offset, uint64_t size, unsigned value,
-			    enum si_coherency coher,
-			    enum si_cache_policy cache_policy)
+void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
+			    struct pipe_resource *dst, uint64_t offset,
+			    uint64_t size, unsigned value, unsigned user_flags,
+			    enum si_coherency coher, enum si_cache_policy cache_policy)
 {
-	struct r600_resource *rdst = r600_resource(dst);
-	uint64_t va = rdst->gpu_address + offset;
+	struct si_resource *sdst = si_resource(dst);
+	uint64_t va = (sdst ? sdst->gpu_address : 0) + offset;
 	bool is_first = true;
 
 	assert(size && size % 4 == 0);
@@ -242,149 +221,40 @@ void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
 	/* Mark the buffer range of destination as valid (initialized),
 	 * so that transfer_map knows it should wait for the GPU when mapping
 	 * that range. */
-	util_range_add(&rdst->valid_buffer_range, offset, offset + size);
+	if (sdst)
+		util_range_add(&sdst->valid_buffer_range, offset, offset + size);
 
 	/* Flush the caches. */
-	sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
-		       SI_CONTEXT_CS_PARTIAL_FLUSH |
-		       get_flush_flags(sctx, coher, cache_policy);
+	if (sdst && !(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
+		sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
+			       SI_CONTEXT_CS_PARTIAL_FLUSH |
+			       si_get_flush_flags(sctx, coher, cache_policy);
+	}
 
 	while (size) {
 		unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
-		unsigned dma_flags = CP_DMA_CLEAR;
+		unsigned dma_flags = CP_DMA_CLEAR | (sdst ? 0 : CP_DMA_DST_IS_GDS);
 
-		si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, 0, coher,
-				  &is_first, &dma_flags);
+		si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, user_flags,
+				  coher, &is_first, &dma_flags);
 
 		/* Emit the clear packet. */
-		si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, cache_policy);
+		si_emit_cp_dma(sctx, cs, va, value, byte_count, dma_flags, cache_policy);
 
 		size -= byte_count;
 		va += byte_count;
 	}
 
-	if (cache_policy != L2_BYPASS)
-		rdst->TC_L2_dirty = true;
+	if (sdst && cache_policy != L2_BYPASS)
+		sdst->TC_L2_dirty = true;
 
 	/* If it's not a framebuffer fast clear... */
-	if (coher == SI_COHERENCY_SHADER)
+	if (coher == SI_COHERENCY_SHADER) {
 		sctx->num_cp_dma_calls++;
-}
-
-void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
-		     uint64_t offset, uint64_t size, unsigned value,
-		     enum si_coherency coher)
-{
-	struct radeon_winsys *ws = sctx->ws;
-	struct r600_resource *rdst = r600_resource(dst);
-	enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
-	uint64_t dma_clear_size;
-
-	if (!size)
-		return;
-
-	dma_clear_size = size & ~3ull;
-
-	/* dma_clear_buffer can use clear_buffer on failure. Make sure that
-	 * doesn't happen. We don't want an infinite recursion: */
-	if (sctx->dma_cs &&
-	    !(dst->flags & PIPE_RESOURCE_FLAG_SPARSE) &&
-	    (offset % 4 == 0) &&
-	    /* CP DMA is very slow. Always use SDMA for big clears. This
-	     * alone improves DeusEx:MD performance by 70%. */
-	    (size > CP_DMA_CLEAR_PERF_THRESHOLD ||
-	     /* Buffers not used by the GFX IB yet will be cleared by SDMA.
-	      * This happens to move most buffer clears to SDMA, including
-	      * DCC and CMASK clears, because pipe->clear clears them before
-	      * si_emit_framebuffer_state (in a draw call) adds them.
-	      * For example, DeusEx:MD has 21 buffer clears per frame and all
-	      * of them are moved to SDMA thanks to this. */
-	     !ws->cs_is_buffer_referenced(sctx->gfx_cs, rdst->buf,
-				          RADEON_USAGE_READWRITE))) {
-		si_sdma_clear_buffer(sctx, dst, offset, dma_clear_size, value);
-
-		offset += dma_clear_size;
-		size -= dma_clear_size;
-	} else if (dma_clear_size >= 4) {
-		si_cp_dma_clear_buffer(sctx, dst, offset, dma_clear_size, value,
-				       coher, cache_policy);
-
-		offset += dma_clear_size;
-		size -= dma_clear_size;
-	}
-
-	if (size) {
-		/* Handle non-dword alignment.
-		 *
-		 * This function is called for embedded texture metadata clears,
-		 * but those should always be properly aligned. */
-		assert(dst->target == PIPE_BUFFER);
-		assert(size < 4);
-
-		pipe_buffer_write(&sctx->b, dst, offset, size, &value);
+		si_prim_discard_signal_next_compute_ib_start(sctx);
 	}
 }
 
-static void si_pipe_clear_buffer(struct pipe_context *ctx,
-				 struct pipe_resource *dst,
-				 unsigned offset, unsigned size,
-				 const void *clear_value_ptr,
-				 int clear_value_size)
-{
-	struct si_context *sctx = (struct si_context*)ctx;
-	uint32_t dword_value;
-	unsigned i;
-
-	assert(offset % clear_value_size == 0);
-	assert(size % clear_value_size == 0);
-
-	if (clear_value_size > 4) {
-		const uint32_t *u32 = clear_value_ptr;
-		bool clear_dword_duplicated = true;
-
-		/* See if we can lower large fills to dword fills. */
-		for (i = 1; i < clear_value_size / 4; i++)
-			if (u32[0] != u32[i]) {
-				clear_dword_duplicated = false;
-				break;
-			}
-
-		if (!clear_dword_duplicated) {
-			/* Use transform feedback for 64-bit, 96-bit, and
-			 * 128-bit fills.
-			 */
-			union pipe_color_union clear_value;
-
-			memcpy(&clear_value, clear_value_ptr, clear_value_size);
-			si_blitter_begin(sctx, SI_DISABLE_RENDER_COND);
-			util_blitter_clear_buffer(sctx->blitter, dst, offset,
-						  size, clear_value_size / 4,
-						  &clear_value);
-			si_blitter_end(sctx);
-			return;
-		}
-	}
-
-	/* Expand the clear value to a dword. */
-	switch (clear_value_size) {
-	case 1:
-		dword_value = *(uint8_t*)clear_value_ptr;
-		dword_value |= (dword_value << 8) |
-			       (dword_value << 16) |
-			       (dword_value << 24);
-		break;
-	case 2:
-		dword_value = *(uint16_t*)clear_value_ptr;
-		dword_value |= dword_value << 16;
-		break;
-	default:
-		dword_value = *(uint32_t*)clear_value_ptr;
-	}
-
-	si_clear_buffer(sctx, dst, offset, size, dword_value,
-			SI_COHERENCY_SHADER);
-}
-
 /**
  * Realign the CP DMA engine. This must be done after a copy with an unaligned
  * size.
@@ -407,7 +277,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 	 */
 	if (!sctx->scratch_buffer ||
 	    sctx->scratch_buffer->b.b.width0 < scratch_size) {
-		r600_resource_reference(&sctx->scratch_buffer, NULL);
+		si_resource_reference(&sctx->scratch_buffer, NULL);
 		sctx->scratch_buffer =
 			si_aligned_buffer_create(&sctx->screen->b,
 						   SI_RESOURCE_FLAG_UNMAPPABLE,
@@ -424,12 +294,13 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 			  coher, is_first, &dma_flags);
 
 	va = sctx->scratch_buffer->gpu_address;
-	si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
+	si_emit_cp_dma(sctx, sctx->gfx_cs, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
 		       cache_policy);
 }
 
 /**
  * Do memcpy between buffers using CP DMA.
+ * If src or dst is NULL, it means read or write GDS, respectively.
  *
  * \param user_flags	bitmask of SI_CPDMA_*
  */
@@ -442,20 +313,26 @@ void si_cp_dma_copy_buffer(struct si_context *sctx,
 	uint64_t main_dst_offset, main_src_offset;
 	unsigned skipped_size = 0;
 	unsigned realign_size = 0;
+	unsigned gds_flags = (dst ? 0 : CP_DMA_DST_IS_GDS) |
+			     (src ? 0 : CP_DMA_SRC_IS_GDS);
 	bool is_first = true;
 
 	assert(size);
 
-	if (dst != src || dst_offset != src_offset) {
-		/* Mark the buffer range of destination as valid (initialized),
-		 * so that transfer_map knows it should wait for the GPU when mapping
-		 * that range. */
-		util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
-			       dst_offset + size);
-	}
+	if (dst) {
+		/* Skip this for the L2 prefetch. */
+		if (dst != src || dst_offset != src_offset) {
+			/* Mark the buffer range of destination as valid (initialized),
+			 * so that transfer_map knows it should wait for the GPU when mapping
+			 * that range. */
+			util_range_add(&si_resource(dst)->valid_buffer_range, dst_offset,
+				       dst_offset + size);
+		}
 
-	dst_offset += r600_resource(dst)->gpu_address;
-	src_offset += r600_resource(src)->gpu_address;
+		dst_offset += si_resource(dst)->gpu_address;
+	}
+	if (src)
+		src_offset += si_resource(src)->gpu_address;
 
 	/* The workarounds aren't needed on Fiji and beyond. */
 	if (sctx->family <= CHIP_CARRIZO ||
@@ -470,8 +347,10 @@ void si_cp_dma_copy_buffer(struct si_context *sctx,
 		/* If the copy begins unaligned, we must start copying from the next
 		 * aligned block and the skipped part should be copied after everything
 		 * else has been copied. Only the src alignment matters, not dst.
+		 *
+		 * GDS doesn't need the source address to be aligned.
 		 */
-		if (src_offset % SI_CPDMA_ALIGNMENT) {
+		if (src && src_offset % SI_CPDMA_ALIGNMENT) {
 			skipped_size = SI_CPDMA_ALIGNMENT - (src_offset % SI_CPDMA_ALIGNMENT);
 			/* The main part will be skipped if the size is too small. */
 			skipped_size = MIN2(skipped_size, size);
@@ -480,10 +359,10 @@ void si_cp_dma_copy_buffer(struct si_context *sctx,
 	}
 
 	/* Flush the caches. */
-	if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
+	if ((dst || src) && !(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
 		sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 			       SI_CONTEXT_CS_PARTIAL_FLUSH |
-			       get_flush_flags(sctx, coher, cache_policy);
+			       si_get_flush_flags(sctx, coher, cache_policy);
 	}
 
 	/* This is the main part doing the copying. Src is always aligned. */
@@ -492,13 +371,13 @@ void si_cp_dma_copy_buffer(struct si_context *sctx,
 
 	while (size) {
 		unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
-		unsigned dma_flags = 0;
+		unsigned dma_flags = gds_flags;
 
 		si_cp_dma_prepare(sctx, dst, src, byte_count,
 				  size + skipped_size + realign_size,
 				  user_flags, coher, &is_first, &dma_flags);
 
-		si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
+		si_emit_cp_dma(sctx, sctx->gfx_cs, main_dst_offset, main_src_offset,
 			       byte_count, dma_flags, cache_policy);
 
 		size -= byte_count;
@@ -508,13 +387,13 @@ void si_cp_dma_copy_buffer(struct si_context *sctx,
 
 	/* Copy the part we skipped because src wasn't aligned. */
 	if (skipped_size) {
-		unsigned dma_flags = 0;
+		unsigned dma_flags = gds_flags;
 
 		si_cp_dma_prepare(sctx, dst, src, skipped_size,
 				  skipped_size + realign_size, user_flags,
 				  coher, &is_first, &dma_flags);
 
-		si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
+		si_emit_cp_dma(sctx, sctx->gfx_cs, dst_offset, src_offset, skipped_size,
 			       dma_flags, cache_policy);
 	}
 
@@ -523,33 +402,21 @@ void si_cp_dma_copy_buffer(struct si_context *sctx,
 		si_cp_dma_realign_engine(sctx, realign_size, user_flags, coher,
 					 cache_policy, &is_first);
 	}
-}
-
-void si_copy_buffer(struct si_context *sctx,
-		    struct pipe_resource *dst, struct pipe_resource *src,
-		    uint64_t dst_offset, uint64_t src_offset, unsigned size)
-{
-	enum si_coherency coher = SI_COHERENCY_SHADER;
-	enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
-
-	if (!size)
-		return;
-
-	si_cp_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, size,
-			      0, coher, cache_policy);
 
-	if (cache_policy != L2_BYPASS)
-		r600_resource(dst)->TC_L2_dirty = true;
+	if (dst && cache_policy != L2_BYPASS)
+		si_resource(dst)->TC_L2_dirty = true;
 
-	/* If it's not a prefetch... */
-	if (dst_offset != src_offset)
+	/* If it's not a prefetch or GDS copy... */
+	if (dst && src && (dst != src || dst_offset != src_offset)) {
 		sctx->num_cp_dma_calls++;
+		si_prim_discard_signal_next_compute_ib_start(sctx);
+	}
 }
 
 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 			      uint64_t offset, unsigned size)
 {
-	assert(sctx->chip_class >= CIK);
+	assert(sctx->chip_class >= GFX7);
 
 	si_cp_dma_copy_buffer(sctx, buf, buf, offset, offset, size,
 			      SI_CPDMA_SKIP_ALL, SI_COHERENCY_SHADER, L2_LRU);
@@ -588,7 +455,7 @@ void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only)
 	/* Prefetch shaders and VBO descriptors to TC L2. */
 	if (sctx->chip_class >= GFX9) {
 		/* Choose the right spot for the VBO prefetch. */
-		if (sctx->tes_shader.cso) {
+		if (sctx->queued.named.hs) {
 			if (mask & SI_PREFETCH_HS)
 				cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
 			if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
@@ -603,7 +470,7 @@ void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only)
 				cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 			if (mask & SI_PREFETCH_VS)
 				cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
-		} else if (sctx->gs_shader.cso) {
+		} else if (sctx->queued.named.gs) {
 			if (mask & SI_PREFETCH_GS)
 				cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 			if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
@@ -628,7 +495,7 @@ void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only)
 			}
 		}
 	} else {
-		/* SI-CI-VI */
+		/* GFX6-GFX8 */
 		/* Choose the right spot for the VBO prefetch. */
 		if (sctx->tes_shader.cso) {
 			if (mask & SI_PREFETCH_LS)
@@ -683,7 +550,90 @@ void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only)
 	sctx->prefetch_L2_mask = 0;
 }
 
-void si_init_cp_dma_functions(struct si_context *sctx)
+void si_test_gds(struct si_context *sctx)
+{
+	struct pipe_context *ctx = &sctx->b;
+	struct pipe_resource *src, *dst;
+	unsigned r[4] = {};
+	unsigned offset = debug_get_num_option("OFFSET", 16);
+
+	src = pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_DEFAULT, 16);
+	dst = pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_DEFAULT, 16);
+	si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 0, 4, 0xabcdef01, 0, SI_COHERENCY_SHADER, L2_BYPASS);
+	si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 4, 4, 0x23456789, 0, SI_COHERENCY_SHADER, L2_BYPASS);
+	si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 8, 4, 0x87654321, 0, SI_COHERENCY_SHADER, L2_BYPASS);
+	si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 12, 4, 0xfedcba98, 0, SI_COHERENCY_SHADER, L2_BYPASS);
+	si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, dst, 0, 16, 0xdeadbeef, 0, SI_COHERENCY_SHADER, L2_BYPASS);
+
+	si_cp_dma_copy_buffer(sctx, NULL, src, offset, 0, 16, 0, SI_COHERENCY_NONE, L2_BYPASS);
+	si_cp_dma_copy_buffer(sctx, dst, NULL, 0, offset, 16, 0, SI_COHERENCY_NONE, L2_BYPASS);
+
+	pipe_buffer_read(ctx, dst, 0, sizeof(r), r);
+	printf("GDS copy  = %08x %08x %08x %08x -> %s\n", r[0], r[1], r[2], r[3],
+			r[0] == 0xabcdef01 && r[1] == 0x23456789 &&
+			r[2] == 0x87654321 && r[3] == 0xfedcba98 ? "pass" : "fail");
+
+	si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, NULL, offset, 16, 0xc1ea4146, 0, SI_COHERENCY_NONE, L2_BYPASS);
+	si_cp_dma_copy_buffer(sctx, dst, NULL, 0, offset, 16, 0, SI_COHERENCY_NONE, L2_BYPASS);
+
+	pipe_buffer_read(ctx, dst, 0, sizeof(r), r);
+	printf("GDS clear = %08x %08x %08x %08x -> %s\n", r[0], r[1], r[2], r[3],
+			r[0] == 0xc1ea4146 && r[1] == 0xc1ea4146 &&
+			r[2] == 0xc1ea4146 && r[3] == 0xc1ea4146 ? "pass" : "fail");
+
+	pipe_resource_reference(&src, NULL);
+	pipe_resource_reference(&dst, NULL);
+	exit(0);
+}
+
+void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
+		      unsigned offset, unsigned size, unsigned dst_sel,
+		      unsigned engine, const void *data)
+{
+	struct radeon_cmdbuf *cs = sctx->gfx_cs;
+
+	assert(offset % 4 == 0);
+	assert(size % 4 == 0);
+
+	if (sctx->chip_class == GFX6 && dst_sel == V_370_MEM)
+		dst_sel = V_370_MEM_GRBM;
+
+	radeon_add_to_buffer_list(sctx, cs, buf,
+				  RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
+	uint64_t va = buf->gpu_address + offset;
+
+	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + size/4, 0));
+	radeon_emit(cs, S_370_DST_SEL(dst_sel) |
+		    S_370_WR_CONFIRM(1) |
+		    S_370_ENGINE_SEL(engine));
+	radeon_emit(cs, va);
+	radeon_emit(cs, va >> 32);
+	radeon_emit_array(cs, (const uint32_t*)data, size/4);
+}
+
+void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
+		     unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
+		     unsigned src_sel, struct si_resource *src, unsigned src_offset)
 {
-	sctx->b.clear_buffer = si_pipe_clear_buffer;
+	/* cs can point to the compute IB, which has the buffer list in gfx_cs. */
+	if (dst) {
+		radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dst,
+					  RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
+	}
+	if (src) {
+		radeon_add_to_buffer_list(sctx, sctx->gfx_cs, src,
+					  RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
+	}
+
+	uint64_t dst_va = (dst ? dst->gpu_address : 0ull) + dst_offset;
+	uint64_t src_va = (src ? src->gpu_address : 0ull) + src_offset;
+
+	radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+	radeon_emit(cs, COPY_DATA_SRC_SEL(src_sel) |
+			COPY_DATA_DST_SEL(dst_sel) |
+			COPY_DATA_WR_CONFIRM);
+	radeon_emit(cs, src_va);
+	radeon_emit(cs, src_va >> 32);
+	radeon_emit(cs, dst_va);
+	radeon_emit(cs, dst_va >> 32);
 }