X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_debug.c;h=4a768ec5a37a6f7900716e02049cd2f1e82e060c;hb=0c6c6810bd2a1e98c0ae07d6db981b8d4f79856f;hp=9d0c0c554cf0c0a9b754b78a07ba816e848add78;hpb=a0e8b735947769ead204669dd58d6e452f72bf64;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index 9d0c0c554cf..4a768ec5a37 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drivers/radeonsi/si_debug.c @@ -1,5 +1,6 @@ /* * Copyright 2015 Advanced Micro Devices, Inc. + * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,48 +20,198 @@ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Marek Olšák */ #include "si_pipe.h" +#include "si_compute.h" #include "sid.h" -#include "gfx9d.h" #include "sid_tables.h" -#include "ddebug/dd_util.h" +#include "driver_ddebug/dd_util.h" +#include "util/u_dump.h" +#include "util/u_log.h" #include "util/u_memory.h" +#include "util/u_string.h" #include "ac_debug.h" +#include "ac_rtld.h" + +static void si_dump_bo_list(struct si_context *sctx, + const struct radeon_saved_cs *saved, FILE *f); DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL) +/** + * Store a linearized copy of all chunks of \p cs together with the buffer + * list in \p saved. + */ +void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, + struct radeon_saved_cs *saved, bool get_buffer_list) +{ + uint32_t *buf; + unsigned i; + + /* Save the IB chunks. */ + saved->num_dw = cs->prev_dw + cs->current.cdw; + saved->ib = MALLOC(4 * saved->num_dw); + if (!saved->ib) + goto oom; + + buf = saved->ib; + for (i = 0; i < cs->num_prev; ++i) { + memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4); + buf += cs->prev[i].cdw; + } + memcpy(buf, cs->current.buf, cs->current.cdw * 4); + + if (!get_buffer_list) + return; + + /* Save the buffer list. */ + saved->bo_count = ws->cs_get_buffer_list(cs, NULL); + saved->bo_list = CALLOC(saved->bo_count, + sizeof(saved->bo_list[0])); + if (!saved->bo_list) { + FREE(saved->ib); + goto oom; + } + ws->cs_get_buffer_list(cs, saved->bo_list); + + return; + +oom: + fprintf(stderr, "%s: out of memory\n", __func__); + memset(saved, 0, sizeof(*saved)); +} + +void si_clear_saved_cs(struct radeon_saved_cs *saved) +{ + FREE(saved->ib); + FREE(saved->bo_list); + + memset(saved, 0, sizeof(*saved)); +} + +void si_destroy_saved_cs(struct si_saved_cs *scs) +{ + si_clear_saved_cs(&scs->gfx); + si_resource_reference(&scs->trace_buf, NULL); + free(scs); +} + static void si_dump_shader(struct si_screen *sscreen, - struct si_shader_ctx_state *state, FILE *f) + enum pipe_shader_type processor, + struct si_shader *shader, FILE *f) +{ + if (shader->shader_log) + fwrite(shader->shader_log, shader->shader_log_size, 1, f); + else + si_shader_dump(sscreen, shader, NULL, processor, f, false); + + if (shader->bo && sscreen->options.dump_shader_binary) { + unsigned size = shader->bo->b.b.width0; + fprintf(f, "BO: VA=%"PRIx64" Size=%u\n", shader->bo->gpu_address, size); + + const char *mapped = sscreen->ws->buffer_map(shader->bo->buf, NULL, + PIPE_TRANSFER_UNSYNCHRONIZED | + PIPE_TRANSFER_READ | + RADEON_TRANSFER_TEMPORARY); + + for (unsigned i = 0; i < size; i += 4) { + fprintf(f, " %4x: %08x\n", i, *(uint32_t*)(mapped + i)); + } + + sscreen->ws->buffer_unmap(shader->bo->buf); + + fprintf(f, "\n"); + } +} + +struct si_log_chunk_shader { + /* The shader destroy code assumes a current context for unlinking of + * PM4 packets etc. + * + * While we should be able to destroy shaders without a context, doing + * so would happen only very rarely and be therefore likely to fail + * just when you're trying to debug something. Let's just remember the + * current context in the chunk. + */ + struct si_context *ctx; + struct si_shader *shader; + enum pipe_shader_type processor; + + /* For keep-alive reference counts */ + struct si_shader_selector *sel; + struct si_compute *program; +}; + +static void +si_log_chunk_shader_destroy(void *data) +{ + struct si_log_chunk_shader *chunk = data; + si_shader_selector_reference(chunk->ctx, &chunk->sel, NULL); + si_compute_reference(&chunk->program, NULL); + FREE(chunk); +} + +static void +si_log_chunk_shader_print(void *data, FILE *f) +{ + struct si_log_chunk_shader *chunk = data; + struct si_screen *sscreen = chunk->ctx->screen; + si_dump_shader(sscreen, chunk->processor, + chunk->shader, f); +} + +static struct u_log_chunk_type si_log_chunk_type_shader = { + .destroy = si_log_chunk_shader_destroy, + .print = si_log_chunk_shader_print, +}; + +static void si_dump_gfx_shader(struct si_context *ctx, + const struct si_shader_ctx_state *state, + struct u_log_context *log) { struct si_shader *current = state->current; if (!state->cso || !current) return; - if (current->shader_log) - fwrite(current->shader_log, current->shader_log_size, 1, f); - else - si_shader_dump(sscreen, state->current, NULL, - state->cso->info.processor, f, false); + struct si_log_chunk_shader *chunk = CALLOC_STRUCT(si_log_chunk_shader); + chunk->ctx = ctx; + chunk->processor = state->cso->info.processor; + chunk->shader = current; + si_shader_selector_reference(ctx, &chunk->sel, current->selector); + u_log_chunk(log, &si_log_chunk_type_shader, chunk); +} + +static void si_dump_compute_shader(struct si_context *ctx, + struct u_log_context *log) +{ + const struct si_cs_shader_state *state = &ctx->cs_shader_state; + + if (!state->program) + return; + + struct si_log_chunk_shader *chunk = CALLOC_STRUCT(si_log_chunk_shader); + chunk->ctx = ctx; + chunk->processor = PIPE_SHADER_COMPUTE; + chunk->shader = &state->program->shader; + si_compute_reference(&chunk->program, state->program); + u_log_chunk(log, &si_log_chunk_type_shader, chunk); } /** * Shader compiles can be overridden with arbitrary ELF objects by setting * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2] + * + * TODO: key this off some hash */ -bool si_replace_shader(unsigned num, struct ac_shader_binary *binary) +bool si_replace_shader(unsigned num, struct si_shader_binary *binary) { const char *p = debug_get_option_replace_shaders(); const char *semicolon; char *copy = NULL; FILE *f; long filesize, nread; - char *buf = NULL; bool replaced = false; if (!p) @@ -116,23 +267,25 @@ bool si_replace_shader(unsigned num, struct ac_shader_binary *binary) if (fseek(f, 0, SEEK_SET) != 0) goto file_error; - buf = MALLOC(filesize); - if (!buf) { + binary->elf_buffer = MALLOC(filesize); + if (!binary->elf_buffer) { fprintf(stderr, "out of memory\n"); goto out_close; } - nread = fread(buf, 1, filesize, f); - if (nread != filesize) + nread = fread((void*)binary->elf_buffer, 1, filesize, f); + if (nread != filesize) { + FREE((void*)binary->elf_buffer); + binary->elf_buffer = NULL; goto file_error; + } - ac_elf_read(buf, filesize, binary); + binary->elf_size = nread; replaced = true; out_close: fclose(f); out_free: - FREE(buf); free(copy); return replaced; @@ -153,25 +306,24 @@ file_error: static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f, unsigned offset) { - struct radeon_winsys *ws = sctx->b.ws; + struct radeon_winsys *ws = sctx->ws; uint32_t value; if (ws->read_registers(ws, offset, 1, &value)) - ac_dump_reg(f, offset, value, ~0); + ac_dump_reg(f, sctx->chip_class, offset, value, ~0); } static void si_dump_debug_registers(struct si_context *sctx, FILE *f) { - if (sctx->screen->b.info.drm_major == 2 && - sctx->screen->b.info.drm_minor < 42) - return; /* no radeon support */ + if (!sctx->screen->info.has_read_registers_query) + return; fprintf(f, "Memory-mapped registers:\n"); si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS); /* No other registers can be read on DRM < 3.1.0. */ - if (sctx->screen->b.info.drm_major < 3 || - sctx->screen->b.info.drm_minor < 1) { + if (!sctx->screen->info.is_amdgpu || + sctx->screen->info.drm_minor < 1) { fprintf(f, "\n"); return; } @@ -183,7 +335,7 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f) si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3); si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG); si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG); - if (sctx->b.chip_class <= VI) { + if (sctx->chip_class <= GFX8) { si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS); si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2); si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3); @@ -201,40 +353,201 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f) fprintf(f, "\n"); } -static void si_dump_last_ib(struct si_context *sctx, FILE *f) +struct si_log_chunk_cs { + struct si_context *ctx; + struct si_saved_cs *cs; + bool dump_bo_list; + unsigned gfx_begin, gfx_end; + unsigned compute_begin, compute_end; +}; + +static void si_log_chunk_type_cs_destroy(void *data) { + struct si_log_chunk_cs *chunk = data; + si_saved_cs_reference(&chunk->cs, NULL); + free(chunk); +} + +static void si_parse_current_ib(FILE *f, struct radeon_cmdbuf *cs, + unsigned begin, unsigned end, + int *last_trace_id, unsigned trace_id_count, + const char *name, enum chip_class chip_class) +{ + unsigned orig_end = end; + + assert(begin <= end); + + fprintf(f, "------------------ %s begin (dw = %u) ------------------\n", + name, begin); + + for (unsigned prev_idx = 0; prev_idx < cs->num_prev; ++prev_idx) { + struct radeon_cmdbuf_chunk *chunk = &cs->prev[prev_idx]; + + if (begin < chunk->cdw) { + ac_parse_ib_chunk(f, chunk->buf + begin, + MIN2(end, chunk->cdw) - begin, + last_trace_id, trace_id_count, + chip_class, NULL, NULL); + } + + if (end <= chunk->cdw) + return; + + if (begin < chunk->cdw) + fprintf(f, "\n---------- Next %s Chunk ----------\n\n", + name); + + begin -= MIN2(begin, chunk->cdw); + end -= chunk->cdw; + } + + assert(end <= cs->current.cdw); + + ac_parse_ib_chunk(f, cs->current.buf + begin, end - begin, last_trace_id, + trace_id_count, chip_class, NULL, NULL); + + fprintf(f, "------------------- %s end (dw = %u) -------------------\n\n", + name, orig_end); +} + +static void si_log_chunk_type_cs_print(void *data, FILE *f) +{ + struct si_log_chunk_cs *chunk = data; + struct si_context *ctx = chunk->ctx; + struct si_saved_cs *scs = chunk->cs; int last_trace_id = -1; + int last_compute_trace_id = -1; - if (!sctx->last_gfx.ib) - return; + /* We are expecting that the ddebug pipe has already + * waited for the context, so this buffer should be idle. + * If the GPU is hung, there is no point in waiting for it. + */ + uint32_t *map = ctx->ws->buffer_map(scs->trace_buf->buf, + NULL, + PIPE_TRANSFER_UNSYNCHRONIZED | + PIPE_TRANSFER_READ); + if (map) { + last_trace_id = map[0]; + last_compute_trace_id = map[1]; + } - if (sctx->last_trace_buf) { - /* We are expecting that the ddebug pipe has already - * waited for the context, so this buffer should be idle. - * If the GPU is hung, there is no point in waiting for it. - */ - uint32_t *map = sctx->b.ws->buffer_map(sctx->last_trace_buf->buf, - NULL, - PIPE_TRANSFER_UNSYNCHRONIZED | - PIPE_TRANSFER_READ); - if (map) - last_trace_id = *map; + if (chunk->gfx_end != chunk->gfx_begin) { + if (chunk->gfx_begin == 0) { + if (ctx->init_config) + ac_parse_ib(f, ctx->init_config->pm4, ctx->init_config->ndw, + NULL, 0, "IB2: Init config", ctx->chip_class, + NULL, NULL); + + if (ctx->init_config_gs_rings) + ac_parse_ib(f, ctx->init_config_gs_rings->pm4, + ctx->init_config_gs_rings->ndw, + NULL, 0, "IB2: Init GS rings", ctx->chip_class, + NULL, NULL); + } + + if (scs->flushed) { + ac_parse_ib(f, scs->gfx.ib + chunk->gfx_begin, + chunk->gfx_end - chunk->gfx_begin, + &last_trace_id, map ? 1 : 0, "IB", ctx->chip_class, + NULL, NULL); + } else { + si_parse_current_ib(f, ctx->gfx_cs, chunk->gfx_begin, + chunk->gfx_end, &last_trace_id, map ? 1 : 0, + "IB", ctx->chip_class); + } } - if (sctx->init_config) - ac_parse_ib(f, sctx->init_config->pm4, sctx->init_config->ndw, - -1, "IB2: Init config", sctx->b.chip_class, - NULL, NULL); + if (chunk->compute_end != chunk->compute_begin) { + assert(ctx->prim_discard_compute_cs); + + if (scs->flushed) { + ac_parse_ib(f, scs->compute.ib + chunk->compute_begin, + chunk->compute_end - chunk->compute_begin, + &last_compute_trace_id, map ? 1 : 0, "Compute IB", ctx->chip_class, + NULL, NULL); + } else { + si_parse_current_ib(f, ctx->prim_discard_compute_cs, chunk->compute_begin, + chunk->compute_end, &last_compute_trace_id, + map ? 1 : 0, "Compute IB", ctx->chip_class); + } + } - if (sctx->init_config_gs_rings) - ac_parse_ib(f, sctx->init_config_gs_rings->pm4, - sctx->init_config_gs_rings->ndw, - -1, "IB2: Init GS rings", sctx->b.chip_class, - NULL, NULL); + if (chunk->dump_bo_list) { + fprintf(f, "Flushing. Time: "); + util_dump_ns(f, scs->time_flush); + fprintf(f, "\n\n"); + si_dump_bo_list(ctx, &scs->gfx, f); + } +} - ac_parse_ib(f, sctx->last_gfx.ib, sctx->last_gfx.num_dw, - last_trace_id, "IB", sctx->b.chip_class, - NULL, NULL); +static const struct u_log_chunk_type si_log_chunk_type_cs = { + .destroy = si_log_chunk_type_cs_destroy, + .print = si_log_chunk_type_cs_print, +}; + +static void si_log_cs(struct si_context *ctx, struct u_log_context *log, + bool dump_bo_list) +{ + assert(ctx->current_saved_cs); + + struct si_saved_cs *scs = ctx->current_saved_cs; + unsigned gfx_cur = ctx->gfx_cs->prev_dw + ctx->gfx_cs->current.cdw; + unsigned compute_cur = 0; + + if (ctx->prim_discard_compute_cs) + compute_cur = ctx->prim_discard_compute_cs->prev_dw + ctx->prim_discard_compute_cs->current.cdw; + + if (!dump_bo_list && + gfx_cur == scs->gfx_last_dw && + compute_cur == scs->compute_last_dw) + return; + + struct si_log_chunk_cs *chunk = calloc(1, sizeof(*chunk)); + + chunk->ctx = ctx; + si_saved_cs_reference(&chunk->cs, scs); + chunk->dump_bo_list = dump_bo_list; + + chunk->gfx_begin = scs->gfx_last_dw; + chunk->gfx_end = gfx_cur; + scs->gfx_last_dw = gfx_cur; + + chunk->compute_begin = scs->compute_last_dw; + chunk->compute_end = compute_cur; + scs->compute_last_dw = compute_cur; + + u_log_chunk(log, &si_log_chunk_type_cs, chunk); +} + +void si_auto_log_cs(void *data, struct u_log_context *log) +{ + struct si_context *ctx = (struct si_context *)data; + si_log_cs(ctx, log, false); +} + +void si_log_hw_flush(struct si_context *sctx) +{ + if (!sctx->log) + return; + + si_log_cs(sctx, sctx->log, true); + + if (&sctx->b == sctx->screen->aux_context) { + /* The aux context isn't captured by the ddebug wrapper, + * so we dump it on a flush-by-flush basis here. + */ + FILE *f = dd_get_debug_file(false); + if (!f) { + fprintf(stderr, "radeonsi: error opening aux context dump file.\n"); + } else { + dd_write_header(f, &sctx->screen->b, 0); + + fprintf(f, "Aux context dump:\n\n"); + u_log_new_page_print(sctx->log, f); + + fclose(f); + } + } } static const char *priority_to_string(enum radeon_bo_priority priority) @@ -249,10 +562,6 @@ static const char *priority_to_string(enum radeon_bo_priority priority) ITEM(IB2), ITEM(DRAW_INDIRECT), ITEM(INDEX_BUFFER), - ITEM(VCE), - ITEM(UVD), - ITEM(SDMA_BUFFER), - ITEM(SDMA_TEXTURE), ITEM(CP_DMA), ITEM(CONST_BUFFER), ITEM(DESCRIPTORS), @@ -268,9 +577,7 @@ static const char *priority_to_string(enum radeon_bo_priority priority) ITEM(DEPTH_BUFFER), ITEM(COLOR_BUFFER_MSAA), ITEM(DEPTH_BUFFER_MSAA), - ITEM(CMASK), - ITEM(DCC), - ITEM(HTILE), + ITEM(SEPARATE_META), ITEM(SHADER_BINARY), ITEM(SHADER_RINGS), ITEM(SCRATCH_BUFFER), @@ -306,7 +613,7 @@ static void si_dump_bo_list(struct si_context *sctx, for (i = 0; i < saved->bo_count; i++) { /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */ - const unsigned page_size = sctx->b.screen->info.gart_page_size; + const unsigned page_size = sctx->screen->info.gart_page_size; uint64_t va = saved->bo_list[i].vm_address; uint64_t size = saved->bo_list[i].bo_size; bool hit = false; @@ -327,8 +634,8 @@ static void si_dump_bo_list(struct si_context *sctx, size / page_size, va / page_size, (va + size) / page_size); /* Print the usage. */ - for (j = 0; j < 64; j++) { - if (!(saved->bo_list[i].priority_usage & (1llu << j))) + for (j = 0; j < 32; j++) { + if (!(saved->bo_list[i].priority_usage & (1u << j))) continue; fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j)); @@ -340,264 +647,337 @@ static void si_dump_bo_list(struct si_context *sctx, " Other buffers can still be allocated there.\n\n"); } -static void si_dump_framebuffer(struct si_context *sctx, FILE *f) +static void si_dump_framebuffer(struct si_context *sctx, struct u_log_context *log) { struct pipe_framebuffer_state *state = &sctx->framebuffer.state; - struct r600_texture *rtex; + struct si_texture *tex; int i; for (i = 0; i < state->nr_cbufs; i++) { if (!state->cbufs[i]) continue; - rtex = (struct r600_texture*)state->cbufs[i]->texture; - fprintf(f, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i); - r600_print_texture_info(sctx->b.screen, rtex, f); - fprintf(f, "\n"); + tex = (struct si_texture*)state->cbufs[i]->texture; + u_log_printf(log, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i); + si_print_texture_info(sctx->screen, tex, log); + u_log_printf(log, "\n"); } if (state->zsbuf) { - rtex = (struct r600_texture*)state->zsbuf->texture; - fprintf(f, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n"); - r600_print_texture_info(sctx->b.screen, rtex, f); - fprintf(f, "\n"); + tex = (struct si_texture*)state->zsbuf->texture; + u_log_printf(log, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n"); + si_print_texture_info(sctx->screen, tex, log); + u_log_printf(log, "\n"); } } -static void si_dump_descriptor_list(struct si_descriptors *desc, - const char *shader_name, - const char *elem_name, - unsigned num_elements, - FILE *f) +typedef unsigned (*slot_remap_func)(unsigned); + +struct si_log_chunk_desc_list { + /** Pointer to memory map of buffer where the list is uploader */ + uint32_t *gpu_list; + /** Reference of buffer where the list is uploaded, so that gpu_list + * is kept live. */ + struct si_resource *buf; + + const char *shader_name; + const char *elem_name; + slot_remap_func slot_remap; + enum chip_class chip_class; + unsigned element_dw_size; + unsigned num_elements; + + uint32_t list[0]; +}; + +static void +si_log_chunk_desc_list_destroy(void *data) { - unsigned i, j; - uint32_t *cpu_list = desc->list; - uint32_t *gpu_list = desc->gpu_list; - const char *list_note = "GPU list"; + struct si_log_chunk_desc_list *chunk = data; + si_resource_reference(&chunk->buf, NULL); + FREE(chunk); +} - if (!gpu_list) { - gpu_list = cpu_list; - list_note = "CPU list"; - } +static void +si_log_chunk_desc_list_print(void *data, FILE *f) +{ + struct si_log_chunk_desc_list *chunk = data; + + for (unsigned i = 0; i < chunk->num_elements; i++) { + unsigned cpu_dw_offset = i * chunk->element_dw_size; + unsigned gpu_dw_offset = chunk->slot_remap(i) * chunk->element_dw_size; + const char *list_note = chunk->gpu_list ? "GPU list" : "CPU list"; + uint32_t *cpu_list = chunk->list + cpu_dw_offset; + uint32_t *gpu_list = chunk->gpu_list ? chunk->gpu_list + gpu_dw_offset : cpu_list; - for (i = 0; i < num_elements; i++) { fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n", - shader_name, elem_name, i, list_note); + chunk->shader_name, chunk->elem_name, i, list_note); - switch (desc->element_dw_size) { + switch (chunk->element_dw_size) { case 4: - for (j = 0; j < 4; j++) - ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4, + for (unsigned j = 0; j < 4; j++) + ac_dump_reg(f, chunk->chip_class, + R_008F00_SQ_BUF_RSRC_WORD0 + j*4, gpu_list[j], 0xffffffff); break; case 8: - for (j = 0; j < 8; j++) - ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4, + for (unsigned j = 0; j < 8; j++) + ac_dump_reg(f, chunk->chip_class, + R_008F10_SQ_IMG_RSRC_WORD0 + j*4, gpu_list[j], 0xffffffff); fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n"); - for (j = 0; j < 4; j++) - ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4, + for (unsigned j = 0; j < 4; j++) + ac_dump_reg(f, chunk->chip_class, + R_008F00_SQ_BUF_RSRC_WORD0 + j*4, gpu_list[4+j], 0xffffffff); break; case 16: - for (j = 0; j < 8; j++) - ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4, + for (unsigned j = 0; j < 8; j++) + ac_dump_reg(f, chunk->chip_class, + R_008F10_SQ_IMG_RSRC_WORD0 + j*4, gpu_list[j], 0xffffffff); fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n"); - for (j = 0; j < 4; j++) - ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4, + for (unsigned j = 0; j < 4; j++) + ac_dump_reg(f, chunk->chip_class, + R_008F00_SQ_BUF_RSRC_WORD0 + j*4, gpu_list[4+j], 0xffffffff); fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n"); - for (j = 0; j < 8; j++) - ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4, + for (unsigned j = 0; j < 8; j++) + ac_dump_reg(f, chunk->chip_class, + R_008F10_SQ_IMG_RSRC_WORD0 + j*4, gpu_list[8+j], 0xffffffff); fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n"); - for (j = 0; j < 4; j++) - ac_dump_reg(f, R_008F30_SQ_IMG_SAMP_WORD0 + j*4, + for (unsigned j = 0; j < 4; j++) + ac_dump_reg(f, chunk->chip_class, + R_008F30_SQ_IMG_SAMP_WORD0 + j*4, gpu_list[12+j], 0xffffffff); break; } - if (memcmp(gpu_list, cpu_list, desc->element_dw_size * 4) != 0) { + if (memcmp(gpu_list, cpu_list, chunk->element_dw_size * 4) != 0) { fprintf(f, COLOR_RED "!!!!! This slot was corrupted in GPU memory !!!!!" COLOR_RESET "\n"); } fprintf(f, "\n"); - gpu_list += desc->element_dw_size; - cpu_list += desc->element_dw_size; } + } -static void si_dump_descriptors(struct si_context *sctx, - struct si_shader_ctx_state *state, - FILE *f) +static const struct u_log_chunk_type si_log_chunk_type_descriptor_list = { + .destroy = si_log_chunk_desc_list_destroy, + .print = si_log_chunk_desc_list_print, +}; + +static void si_dump_descriptor_list(struct si_screen *screen, + struct si_descriptors *desc, + const char *shader_name, + const char *elem_name, + unsigned element_dw_size, + unsigned num_elements, + slot_remap_func slot_remap, + struct u_log_context *log) { - if (!state->cso || !state->current) + if (!desc->list) return; - unsigned type = state->cso->type; - const struct tgsi_shader_info *info = &state->cso->info; - struct si_descriptors *descs = - &sctx->descriptors[SI_DESCS_FIRST_SHADER + - type * SI_NUM_SHADER_DESCS]; - static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"}; + /* In some cases, the caller doesn't know how many elements are really + * uploaded. Reduce num_elements to fit in the range of active slots. */ + unsigned active_range_dw_begin = + desc->first_active_slot * desc->element_dw_size; + unsigned active_range_dw_end = + active_range_dw_begin + desc->num_active_slots * desc->element_dw_size; - static const char *elem_name[] = { - " - Constant buffer", - " - Shader buffer", - " - Sampler", - " - Image", - }; - unsigned num_elements[] = { - util_last_bit(info->const_buffers_declared), - util_last_bit(info->shader_buffers_declared), - util_last_bit(info->samplers_declared), - util_last_bit(info->images_declared), - }; + while (num_elements > 0) { + int i = slot_remap(num_elements - 1); + unsigned dw_begin = i * element_dw_size; + unsigned dw_end = dw_begin + element_dw_size; - if (type == PIPE_SHADER_VERTEX) { - si_dump_descriptor_list(&sctx->vertex_buffers, shader_name[type], - " - Vertex buffer", info->num_inputs, f); + if (dw_begin >= active_range_dw_begin && dw_end <= active_range_dw_end) + break; + + num_elements--; } - for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs) - si_dump_descriptor_list(descs, shader_name[type], elem_name[i], - num_elements[i], f); -} + struct si_log_chunk_desc_list *chunk = + CALLOC_VARIANT_LENGTH_STRUCT(si_log_chunk_desc_list, + 4 * element_dw_size * num_elements); + chunk->shader_name = shader_name; + chunk->elem_name = elem_name; + chunk->element_dw_size = element_dw_size; + chunk->num_elements = num_elements; + chunk->slot_remap = slot_remap; + chunk->chip_class = screen->info.chip_class; + + si_resource_reference(&chunk->buf, desc->buffer); + chunk->gpu_list = desc->gpu_list; + + for (unsigned i = 0; i < num_elements; ++i) { + memcpy(&chunk->list[i * element_dw_size], + &desc->list[slot_remap(i) * element_dw_size], + 4 * element_dw_size); + } -struct si_shader_inst { - char text[160]; /* one disasm line */ - unsigned offset; /* instruction offset */ - unsigned size; /* instruction size = 4 or 8 */ -}; + u_log_chunk(log, &si_log_chunk_type_descriptor_list, chunk); +} -/* Split a disassembly string into lines and add them to the array pointed - * to by "instructions". */ -static void si_add_split_disasm(const char *disasm, - uint64_t start_addr, - unsigned *num, - struct si_shader_inst *instructions) +static unsigned si_identity(unsigned slot) { - struct si_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL; - char *next; + return slot; +} - while ((next = strchr(disasm, '\n'))) { - struct si_shader_inst *inst = &instructions[*num]; - unsigned len = next - disasm; +static void si_dump_descriptors(struct si_context *sctx, + enum pipe_shader_type processor, + const struct tgsi_shader_info *info, + struct u_log_context *log) +{ + struct si_descriptors *descs = + &sctx->descriptors[SI_DESCS_FIRST_SHADER + + processor * SI_NUM_SHADER_DESCS]; + static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"}; + const char *name = shader_name[processor]; + unsigned enabled_constbuf, enabled_shaderbuf, enabled_samplers; + unsigned enabled_images; + + if (info) { + enabled_constbuf = info->const_buffers_declared; + enabled_shaderbuf = info->shader_buffers_declared; + enabled_samplers = info->samplers_declared; + enabled_images = info->images_declared; + } else { + enabled_constbuf = sctx->const_and_shader_buffers[processor].enabled_mask >> + SI_NUM_SHADER_BUFFERS; + enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask & + u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS); + enabled_shaderbuf = util_bitreverse(enabled_shaderbuf) >> + (32 - SI_NUM_SHADER_BUFFERS); + enabled_samplers = sctx->samplers[processor].enabled_mask; + enabled_images = sctx->images[processor].enabled_mask; + } - assert(len < ARRAY_SIZE(inst->text)); - memcpy(inst->text, disasm, len); - inst->text[len] = 0; - inst->offset = last_inst ? last_inst->offset + last_inst->size : 0; + if (processor == PIPE_SHADER_VERTEX && + sctx->vb_descriptors_buffer && + sctx->vb_descriptors_gpu_list && + sctx->vertex_elements) { + assert(info); /* only CS may not have an info struct */ + struct si_descriptors desc = {}; + + desc.buffer = sctx->vb_descriptors_buffer; + desc.list = sctx->vb_descriptors_gpu_list; + desc.gpu_list = sctx->vb_descriptors_gpu_list; + desc.element_dw_size = 4; + desc.num_active_slots = sctx->vertex_elements->desc_list_byte_size / 16; + + si_dump_descriptor_list(sctx->screen, &desc, name, + " - Vertex buffer", 4, info->num_inputs, + si_identity, log); + } - const char *semicolon = strchr(disasm, ';'); - assert(semicolon); - /* More than 16 chars after ";" means the instruction is 8 bytes long. */ - inst->size = next - semicolon > 16 ? 8 : 4; + si_dump_descriptor_list(sctx->screen, + &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS], + name, " - Constant buffer", 4, + util_last_bit(enabled_constbuf), + si_get_constbuf_slot, log); + si_dump_descriptor_list(sctx->screen, + &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS], + name, " - Shader buffer", 4, + util_last_bit(enabled_shaderbuf), + si_get_shaderbuf_slot, log); + si_dump_descriptor_list(sctx->screen, + &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES], + name, " - Sampler", 16, + util_last_bit(enabled_samplers), + si_get_sampler_slot, log); + si_dump_descriptor_list(sctx->screen, + &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES], + name, " - Image", 8, + util_last_bit(enabled_images), + si_get_image_slot, log); +} - snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len, - " [PC=0x%"PRIx64", off=%u, size=%u]", - start_addr + inst->offset, inst->offset, inst->size); +static void si_dump_gfx_descriptors(struct si_context *sctx, + const struct si_shader_ctx_state *state, + struct u_log_context *log) +{ + if (!state->cso || !state->current) + return; - last_inst = inst; - (*num)++; - disasm = next + 1; - } + si_dump_descriptors(sctx, state->cso->type, &state->cso->info, log); } -#define MAX_WAVES_PER_CHIP (64 * 40) +static void si_dump_compute_descriptors(struct si_context *sctx, + struct u_log_context *log) +{ + if (!sctx->cs_shader_state.program) + return; + + si_dump_descriptors(sctx, PIPE_SHADER_COMPUTE, NULL, log); +} -struct si_wave_info { - unsigned se; /* shader engine */ - unsigned sh; /* shader array */ - unsigned cu; /* compute unit */ - unsigned simd; - unsigned wave; - uint32_t status; - uint64_t pc; /* program counter */ - uint32_t inst_dw0; - uint32_t inst_dw1; - uint64_t exec; - bool matched; /* whether the wave is used by a currently-bound shader */ +struct si_shader_inst { + const char *text; /* start of disassembly for this instruction */ + unsigned textlen; + unsigned size; /* instruction size = 4 or 8 */ + uint64_t addr; /* instruction address */ }; -static int compare_wave(const void *p1, const void *p2) -{ - struct si_wave_info *w1 = (struct si_wave_info *)p1; - struct si_wave_info *w2 = (struct si_wave_info *)p2; - - /* Sort waves according to PC and then SE, SH, CU, etc. */ - if (w1->pc < w2->pc) - return -1; - if (w1->pc > w2->pc) - return 1; - if (w1->se < w2->se) - return -1; - if (w1->se > w2->se) - return 1; - if (w1->sh < w2->sh) - return -1; - if (w1->sh > w2->sh) - return 1; - if (w1->cu < w2->cu) - return -1; - if (w1->cu > w2->cu) - return 1; - if (w1->simd < w2->simd) - return -1; - if (w1->simd > w2->simd) - return 1; - if (w1->wave < w2->wave) - return -1; - if (w1->wave > w2->wave) - return 1; - - return 0; -} - -/* Return wave information. "waves" should be a large enough array. */ -static unsigned si_get_wave_info(struct si_wave_info waves[MAX_WAVES_PER_CHIP]) +/** + * Open the given \p binary as \p rtld_binary and split the contained + * disassembly string into instructions and add them to the array + * pointed to by \p instructions, which must be sufficiently large. + * + * Labels are considered to be part of the following instruction. + * + * The caller must keep \p rtld_binary alive as long as \p instructions are + * used and then close it afterwards. + */ +static void si_add_split_disasm(struct si_screen *screen, + struct ac_rtld_binary *rtld_binary, + struct si_shader_binary *binary, + uint64_t *addr, + unsigned *num, + struct si_shader_inst *instructions) { - char line[2000]; - unsigned num_waves = 0; - - FILE *p = popen("umr -wa", "r"); - if (!p) - return 0; + if (!ac_rtld_open(rtld_binary, (struct ac_rtld_open_info){ + .info = &screen->info, + .num_parts = 1, + .elf_ptrs = &binary->elf_buffer, + .elf_sizes = &binary->elf_size })) + return; - if (!fgets(line, sizeof(line), p) || - strncmp(line, "SE", 2) != 0) { - pclose(p); - return 0; - } + const char *disasm; + size_t nbytes; + if (!ac_rtld_get_section_by_name(rtld_binary, ".AMDGPU.disasm", + &disasm, &nbytes)) + return; - while (fgets(line, sizeof(line), p)) { - struct si_wave_info *w; - uint32_t pc_hi, pc_lo, exec_hi, exec_lo; + const char *end = disasm + nbytes; + while (disasm < end) { + const char *semicolon = memchr(disasm, ';', end - disasm); + if (!semicolon) + break; - assert(num_waves < MAX_WAVES_PER_CHIP); - w = &waves[num_waves]; + struct si_shader_inst *inst = &instructions[(*num)++]; + const char *inst_end = memchr(semicolon + 1, '\n', end - semicolon - 1); + if (!inst_end) + inst_end = end; - if (sscanf(line, "%u %u %u %u %u %x %x %x %x %x %x %x", - &w->se, &w->sh, &w->cu, &w->simd, &w->wave, - &w->status, &pc_hi, &pc_lo, &w->inst_dw0, - &w->inst_dw1, &exec_hi, &exec_lo) == 12) { - w->pc = ((uint64_t)pc_hi << 32) | pc_lo; - w->exec = ((uint64_t)exec_hi << 32) | exec_lo; - w->matched = false; - num_waves++; - } - } + inst->text = disasm; + inst->textlen = inst_end - disasm; - qsort(waves, num_waves, sizeof(struct si_wave_info), compare_wave); + inst->addr = *addr; + /* More than 16 chars after ";" means the instruction is 8 bytes long. */ + inst->size = inst_end - semicolon > 16 ? 8 : 4; + *addr += inst->size; - pclose(p); - return num_waves; + if (inst_end == end) + break; + disasm = inst_end + 1; + } } /* If the shader is being executed, print its asm instructions, and annotate @@ -605,13 +985,14 @@ static unsigned si_get_wave_info(struct si_wave_info waves[MAX_WAVES_PER_CHIP]) * execute them. This is most useful during a GPU hang. */ static void si_print_annotated_shader(struct si_shader *shader, - struct si_wave_info *waves, + struct ac_wave_info *waves, unsigned num_waves, FILE *f) { - if (!shader || !shader->binary.disasm_string) + if (!shader) return; + struct si_screen *screen = shader->selector->screen; uint64_t start_addr = shader->bo->gpu_address; uint64_t end_addr = start_addr + shader->bo->b.b.width0; unsigned i; @@ -632,18 +1013,28 @@ static void si_print_annotated_shader(struct si_shader *shader, * Buffer size / 4 is the upper bound of the instruction count. */ unsigned num_inst = 0; + uint64_t inst_addr = start_addr; + struct ac_rtld_binary rtld_binaries[5] = {}; struct si_shader_inst *instructions = calloc(shader->bo->b.b.width0 / 4, sizeof(struct si_shader_inst)); if (shader->prolog) { - si_add_split_disasm(shader->prolog->binary.disasm_string, - start_addr, &num_inst, instructions); + si_add_split_disasm(screen, &rtld_binaries[0], &shader->prolog->binary, + &inst_addr, &num_inst, instructions); + } + if (shader->previous_stage) { + si_add_split_disasm(screen, &rtld_binaries[1], &shader->previous_stage->binary, + &inst_addr, &num_inst, instructions); } - si_add_split_disasm(shader->binary.disasm_string, - start_addr, &num_inst, instructions); + if (shader->prolog2) { + si_add_split_disasm(screen, &rtld_binaries[2], &shader->prolog2->binary, + &inst_addr, &num_inst, instructions); + } + si_add_split_disasm(screen, &rtld_binaries[3], &shader->binary, + &inst_addr, &num_inst, instructions); if (shader->epilog) { - si_add_split_disasm(shader->epilog->binary.disasm_string, - start_addr, &num_inst, instructions); + si_add_split_disasm(screen, &rtld_binaries[4], &shader->epilog->binary, + &inst_addr, &num_inst, instructions); } fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n", @@ -653,10 +1044,11 @@ static void si_print_annotated_shader(struct si_shader *shader, for (i = 0; i < num_inst; i++) { struct si_shader_inst *inst = &instructions[i]; - fprintf(f, "%s\n", inst->text); + fprintf(f, "%.*s [PC=0x%"PRIx64", size=%u]\n", + inst->textlen, inst->text, inst->addr, inst->size); /* Print which waves execute the instruction right now. */ - while (num_waves && start_addr + inst->offset == waves->pc) { + while (num_waves && inst->addr == waves->pc) { fprintf(f, " " COLOR_GREEN "^ SE%u SH%u CU%u " "SIMD%u WAVE%u EXEC=%016"PRIx64 " ", @@ -679,12 +1071,14 @@ static void si_print_annotated_shader(struct si_shader *shader, fprintf(f, "\n\n"); free(instructions); + for (unsigned i = 0; i < ARRAY_SIZE(rtld_binaries); ++i) + ac_rtld_close(&rtld_binaries[i]); } static void si_dump_annotated_shaders(struct si_context *sctx, FILE *f) { - struct si_wave_info waves[MAX_WAVES_PER_CHIP]; - unsigned num_waves = si_get_wave_info(waves); + struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]; + unsigned num_waves = ac_get_wave_info(waves); fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET "\n\n", num_waves); @@ -738,44 +1132,56 @@ static void si_dump_debug_state(struct pipe_context *ctx, FILE *f, { struct si_context *sctx = (struct si_context*)ctx; - if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS) - si_dump_debug_registers(sctx, f); + if (sctx->log) + u_log_flush(sctx->log); - if (flags & PIPE_DUMP_CURRENT_STATES) - si_dump_framebuffer(sctx, f); + if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS) { + si_dump_debug_registers(sctx, f); - if (flags & PIPE_DUMP_CURRENT_SHADERS) { - si_dump_shader(sctx->screen, &sctx->vs_shader, f); - si_dump_shader(sctx->screen, &sctx->tcs_shader, f); - si_dump_shader(sctx->screen, &sctx->tes_shader, f); - si_dump_shader(sctx->screen, &sctx->gs_shader, f); - si_dump_shader(sctx->screen, &sctx->ps_shader, f); + si_dump_annotated_shaders(sctx, f); + si_dump_command("Active waves (raw data)", "umr -O halt_waves -wa | column -t", f); + si_dump_command("Wave information", "umr -O halt_waves,bits -wa", f); + } +} - if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS) { - si_dump_annotated_shaders(sctx, f); - si_dump_command("Active waves (raw data)", "umr -wa | column -t", f); - si_dump_command("Wave information", "umr -O bits -wa", f); - } +void si_log_draw_state(struct si_context *sctx, struct u_log_context *log) +{ + struct si_shader_ctx_state *tcs_shader; - si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS], - "", "RW buffers", SI_NUM_RW_BUFFERS, f); - si_dump_descriptors(sctx, &sctx->vs_shader, f); - si_dump_descriptors(sctx, &sctx->tcs_shader, f); - si_dump_descriptors(sctx, &sctx->tes_shader, f); - si_dump_descriptors(sctx, &sctx->gs_shader, f); - si_dump_descriptors(sctx, &sctx->ps_shader, f); - } + if (!log) + return; - if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) { - si_dump_bo_list(sctx, &sctx->last_gfx, f); - si_dump_last_ib(sctx, f); + tcs_shader = &sctx->tcs_shader; + if (sctx->tes_shader.cso && !sctx->tcs_shader.cso) + tcs_shader = &sctx->fixed_func_tcs_shader; + + si_dump_framebuffer(sctx, log); + + si_dump_gfx_shader(sctx, &sctx->vs_shader, log); + si_dump_gfx_shader(sctx, tcs_shader, log); + si_dump_gfx_shader(sctx, &sctx->tes_shader, log); + si_dump_gfx_shader(sctx, &sctx->gs_shader, log); + si_dump_gfx_shader(sctx, &sctx->ps_shader, log); + + si_dump_descriptor_list(sctx->screen, + &sctx->descriptors[SI_DESCS_RW_BUFFERS], + "", "RW buffers", 4, + sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots, + si_identity, log); + si_dump_gfx_descriptors(sctx, &sctx->vs_shader, log); + si_dump_gfx_descriptors(sctx, tcs_shader, log); + si_dump_gfx_descriptors(sctx, &sctx->tes_shader, log); + si_dump_gfx_descriptors(sctx, &sctx->gs_shader, log); + si_dump_gfx_descriptors(sctx, &sctx->ps_shader, log); +} - fprintf(f, "Done.\n"); +void si_log_compute_state(struct si_context *sctx, struct u_log_context *log) +{ + if (!log) + return; - /* dump only once */ - radeon_clear_saved_cs(&sctx->last_gfx); - r600_resource_reference(&sctx->last_trace_buf, NULL); - } + si_dump_compute_shader(sctx, log); + si_dump_compute_descriptors(sctx, log); } static void si_dump_dma(struct si_context *sctx, @@ -798,99 +1204,16 @@ static void si_dump_dma(struct si_context *sctx, fprintf(f, "SDMA Dump Done.\n"); } -static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr) -{ - char line[2000]; - unsigned sec, usec; - int progress = 0; - uint64_t timestamp = 0; - bool fault = false; - - FILE *p = popen("dmesg", "r"); - if (!p) - return false; - - while (fgets(line, sizeof(line), p)) { - char *msg, len; - - if (!line[0] || line[0] == '\n') - continue; - - /* Get the timestamp. */ - if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) { - static bool hit = false; - if (!hit) { - fprintf(stderr, "%s: failed to parse line '%s'\n", - __func__, line); - hit = true; - } - continue; - } - timestamp = sec * 1000000llu + usec; - - /* If just updating the timestamp. */ - if (!out_addr) - continue; - - /* Process messages only if the timestamp is newer. */ - if (timestamp <= sctx->dmesg_timestamp) - continue; - - /* Only process the first VM fault. */ - if (fault) - continue; - - /* Remove trailing \n */ - len = strlen(line); - if (len && line[len-1] == '\n') - line[len-1] = 0; - - /* Get the message part. */ - msg = strchr(line, ']'); - if (!msg) { - assert(0); - continue; - } - msg++; - - switch (progress) { - case 0: - if (strstr(msg, "GPU fault detected:")) - progress = 1; - break; - case 1: - msg = strstr(msg, "VM_CONTEXT1_PROTECTION_FAULT_ADDR"); - if (msg) { - msg = strstr(msg, "0x"); - if (msg) { - msg += 2; - if (sscanf(msg, "%X", out_addr) == 1) - fault = true; - } - } - progress = 0; - break; - default: - progress = 0; - } - } - pclose(p); - - if (timestamp > sctx->dmesg_timestamp) - sctx->dmesg_timestamp = timestamp; - return fault; -} - -void si_check_vm_faults(struct r600_common_context *ctx, +void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, enum ring_type ring) { - struct si_context *sctx = (struct si_context *)ctx; - struct pipe_screen *screen = sctx->b.b.screen; + struct pipe_screen *screen = sctx->b.screen; FILE *f; - uint32_t addr; + uint64_t addr; char cmd_line[4096]; - if (!si_vm_fault_occured(sctx, &addr)) + if (!ac_vm_fault_occured(sctx->chip_class, + &sctx->dmesg_timestamp, &addr)) return; f = dd_get_debug_file(false); @@ -903,20 +1226,25 @@ void si_check_vm_faults(struct r600_common_context *ctx, fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen)); fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen)); fprintf(f, "Device name: %s\n\n", screen->get_name(screen)); - fprintf(f, "Failing VM page: 0x%08x\n\n", addr); + fprintf(f, "Failing VM page: 0x%08"PRIx64"\n\n", addr); if (sctx->apitrace_call_number) fprintf(f, "Last apitrace call: %u\n\n", sctx->apitrace_call_number); switch (ring) { - case RING_GFX: - si_dump_debug_state(&sctx->b.b, f, - PIPE_DUMP_CURRENT_STATES | - PIPE_DUMP_CURRENT_SHADERS | - PIPE_DUMP_LAST_COMMAND_BUFFER); - break; + case RING_GFX: { + struct u_log_context log; + u_log_context_init(&log); + si_log_draw_state(sctx, &log); + si_log_compute_state(sctx, &log); + si_log_cs(sctx, &log, true); + + u_log_new_page_print(&log, f); + u_log_context_destroy(&log); + break; + } case RING_DMA: si_dump_dma(sctx, saved, f); break; @@ -933,12 +1261,12 @@ void si_check_vm_faults(struct r600_common_context *ctx, void si_init_debug_functions(struct si_context *sctx) { - sctx->b.b.dump_debug_state = si_dump_debug_state; - sctx->b.check_vm_faults = si_check_vm_faults; + sctx->b.dump_debug_state = si_dump_debug_state; /* Set the initial dmesg timestamp for this context, so that * only new messages will be checked for VM faults. */ - if (sctx->screen->b.debug_flags & DBG_CHECK_VM) - si_vm_fault_occured(sctx, NULL); + if (sctx->screen->debug_flags & DBG(CHECK_VM)) + ac_vm_fault_occured(sctx->chip_class, + &sctx->dmesg_timestamp, NULL); }