X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_debug.c;h=c2242a6deabbbc5903131f99a4d1dfb825f9d8aa;hb=d500c9b060e1715e8d3a984d4a5c6f6179f46943;hp=d08a8fcf0eccb735a9c8d9924e8f3605fd56e8d3;hpb=362f8f67989e8e9a9bce3a2bf5e51fd4c0debe5b;p=mesa.git

diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index d08a8fcf0ec..c2242a6deab 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -30,9 +30,13 @@
 #include "gfx9d.h"
 #include "sid_tables.h"
 #include "ddebug/dd_util.h"
+#include "util/u_log.h"
 #include "util/u_memory.h"
 #include "ac_debug.h"
 
+static void si_dump_bo_list(struct si_context *sctx,
+			    const struct radeon_saved_cs *saved, FILE *f);
+
 DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
 
 static void si_dump_shader(struct si_screen *sscreen,
@@ -45,24 +49,72 @@ static void si_dump_shader(struct si_screen *sscreen,
 		si_shader_dump(sscreen, shader, NULL, processor, f, false);
 }
 
-static void si_dump_gfx_shader(struct si_screen *sscreen,
-			       const struct si_shader_ctx_state *state, FILE *f)
+struct si_log_chunk_shader {
+	/* The shader destroy code assumes a current context for unlinking of
+	 * PM4 packets etc.
+	 *
+	 * While we should be able to destroy shaders without a context, doing
+	 * so would happen only very rarely and be therefore likely to fail
+	 * just when you're trying to debug something. Let's just remember the
+	 * current context in the chunk.
+	 */
+	struct si_context *ctx;
+	struct si_shader *shader;
+
+	/* For keep-alive reference counts */
+	struct si_shader_selector *sel;
+	struct si_compute *program;
+};
+
+static void
+si_log_chunk_shader_destroy(void *data)
+{
+	struct si_log_chunk_shader *chunk = data;
+	si_shader_selector_reference(chunk->ctx, &chunk->sel, NULL);
+	si_compute_reference(&chunk->program, NULL);
+	FREE(chunk);
+}
+
+static void
+si_log_chunk_shader_print(void *data, FILE *f)
+{
+	struct si_log_chunk_shader *chunk = data;
+	struct si_screen *sscreen = chunk->ctx->screen;
+	si_dump_shader(sscreen, chunk->shader->selector->info.processor,
+		       chunk->shader, f);
+}
+
+static struct u_log_chunk_type si_log_chunk_type_shader = {
+	.destroy = si_log_chunk_shader_destroy,
+	.print = si_log_chunk_shader_print,
+};
+
+static void si_dump_gfx_shader(struct si_context *ctx,
+			       const struct si_shader_ctx_state *state,
+			       struct u_log_context *log)
 {
-	const struct si_shader *current = state->current;
+	struct si_shader *current = state->current;
 
 	if (!state->cso || !current)
 		return;
 
-	si_dump_shader(sscreen, state->cso->info.processor, current, f);
+	struct si_log_chunk_shader *chunk = CALLOC_STRUCT(si_log_chunk_shader);
+	chunk->ctx = ctx;
+	chunk->shader = current;
+	si_shader_selector_reference(ctx, &chunk->sel, current->selector);
+	u_log_chunk(log, &si_log_chunk_type_shader, chunk);
 }
 
-static void si_dump_compute_shader(struct si_screen *sscreen,
-				   const struct si_cs_shader_state *state, FILE *f)
+static void si_dump_compute_shader(const struct si_cs_shader_state *state,
+				   struct u_log_context *log)
 {
 	if (!state->program || state->program != state->emitted_program)
 		return;
 
-	si_dump_shader(sscreen, PIPE_SHADER_COMPUTE, &state->program->shader, f);
+	struct si_log_chunk_shader *chunk = CALLOC_STRUCT(si_log_chunk_shader);
+	chunk->shader = &state->program->shader;
+	si_compute_reference(&chunk->program, state->program);
+	u_log_chunk(log, &si_log_chunk_type_shader, chunk);
 }
 
 /**
@@ -217,40 +269,153 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
 	fprintf(f, "\n");
 }
 
-static void si_dump_last_ib(struct si_context *sctx, FILE *f)
+struct si_log_chunk_cs {
+	struct si_context *ctx;
+	struct si_saved_cs *cs;
+	bool dump_bo_list;
+	unsigned gfx_begin, gfx_end;
+};
+
+static void si_log_chunk_type_cs_destroy(void *data)
+{
+	struct si_log_chunk_cs *chunk = data;
+	si_saved_cs_reference(&chunk->cs, NULL);
+	free(chunk);
+}
+
+static void si_parse_current_ib(FILE *f, struct radeon_winsys_cs *cs,
+				unsigned begin, unsigned end,
+				unsigned last_trace_id, const char *name,
+				enum chip_class chip_class)
+{
+	unsigned orig_end = end;
+
+	assert(begin <= end);
+
+	fprintf(f, "------------------ %s begin (dw = %u) ------------------\n",
+		name, begin);
+
+	for (unsigned prev_idx = 0; prev_idx < cs->num_prev; ++prev_idx) {
+		struct radeon_winsys_cs_chunk *chunk = &cs->prev[prev_idx];
+
+		if (begin < chunk->cdw) {
+			ac_parse_ib_chunk(f, chunk->buf + begin,
+					  MIN2(end, chunk->cdw) - begin,
+					  last_trace_id, chip_class, NULL, NULL);
+		}
+
+		if (end <= chunk->cdw)
+			return;
+
+		if (begin < chunk->cdw)
+			fprintf(f, "\n---------- Next %s Chunk ----------\n\n",
+				name);
+
+		begin -= MIN2(begin, chunk->cdw);
+		end -= chunk->cdw;
+	}
+
+	assert(end <= cs->current.cdw);
+
+	ac_parse_ib_chunk(f, cs->current.buf + begin, end - begin, last_trace_id,
+			  chip_class, NULL, NULL);
+
+	fprintf(f, "------------------- %s end (dw = %u) -------------------\n\n",
+		name, orig_end);
+}
+
+static void si_log_chunk_type_cs_print(void *data, FILE *f)
 {
+	struct si_log_chunk_cs *chunk = data;
+	struct si_context *ctx = chunk->ctx;
+	struct si_saved_cs *scs = chunk->cs;
 	int last_trace_id = -1;
 
-	if (!sctx->last_gfx.ib)
-		return;
+	/* We are expecting that the ddebug pipe has already
+	 * waited for the context, so this buffer should be idle.
+	 * If the GPU is hung, there is no point in waiting for it.
+	 */
+	uint32_t *map = ctx->b.ws->buffer_map(scs->trace_buf->buf,
+					      NULL,
+					      PIPE_TRANSFER_UNSYNCHRONIZED |
+					      PIPE_TRANSFER_READ);
+	if (map)
+		last_trace_id = map[0];
+
+	if (chunk->gfx_end != chunk->gfx_begin) {
+		if (chunk->gfx_begin == 0) {
+			if (ctx->init_config)
+				ac_parse_ib(f, ctx->init_config->pm4, ctx->init_config->ndw,
+					    -1, "IB2: Init config", ctx->b.chip_class,
+					    NULL, NULL);
+
+			if (ctx->init_config_gs_rings)
+				ac_parse_ib(f, ctx->init_config_gs_rings->pm4,
+					    ctx->init_config_gs_rings->ndw,
+					    -1, "IB2: Init GS rings", ctx->b.chip_class,
+					    NULL, NULL);
+		}
 
-	if (sctx->last_trace_buf) {
-		/* We are expecting that the ddebug pipe has already
-		 * waited for the context, so this buffer should be idle.
-		 * If the GPU is hung, there is no point in waiting for it.
-		 */
-		uint32_t *map = sctx->b.ws->buffer_map(sctx->last_trace_buf->buf,
-						       NULL,
-						       PIPE_TRANSFER_UNSYNCHRONIZED |
-						       PIPE_TRANSFER_READ);
-		if (map)
-			last_trace_id = *map;
+		if (scs->flushed) {
+			ac_parse_ib(f, scs->gfx.ib + chunk->gfx_begin,
+				    chunk->gfx_end - chunk->gfx_begin,
+				    last_trace_id, "IB", ctx->b.chip_class,
+				    NULL, NULL);
+		} else {
+			si_parse_current_ib(f, ctx->b.gfx.cs, chunk->gfx_begin,
+					    chunk->gfx_end, last_trace_id, "IB",
+					    ctx->b.chip_class);
+		}
 	}
 
-	if (sctx->init_config)
-		ac_parse_ib(f, sctx->init_config->pm4, sctx->init_config->ndw,
-			    -1, "IB2: Init config", sctx->b.chip_class,
-			    NULL, NULL);
+	if (chunk->dump_bo_list) {
+		fprintf(f, "Flushing.\n\n");
+		si_dump_bo_list(ctx, &scs->gfx, f);
+	}
+}
+
+static const struct u_log_chunk_type si_log_chunk_type_cs = {
+	.destroy = si_log_chunk_type_cs_destroy,
+	.print = si_log_chunk_type_cs_print,
+};
+
+static void si_log_cs(struct si_context *ctx, struct u_log_context *log,
+		      bool dump_bo_list)
+{
+	assert(ctx->current_saved_cs);
+
+	struct si_saved_cs *scs = ctx->current_saved_cs;
+	unsigned gfx_cur = ctx->b.gfx.cs->prev_dw + ctx->b.gfx.cs->current.cdw;
+
+	if (!dump_bo_list &&
+	    gfx_cur == scs->gfx_last_dw)
+		return;
+
+	struct si_log_chunk_cs *chunk = calloc(1, sizeof(*chunk));
+
+	chunk->ctx = ctx;
+	si_saved_cs_reference(&chunk->cs, scs);
+	chunk->dump_bo_list = dump_bo_list;
 
-	if (sctx->init_config_gs_rings)
-		ac_parse_ib(f, sctx->init_config_gs_rings->pm4,
-			    sctx->init_config_gs_rings->ndw,
-			    -1, "IB2: Init GS rings", sctx->b.chip_class,
-			    NULL, NULL);
+	chunk->gfx_begin = scs->gfx_last_dw;
+	chunk->gfx_end = gfx_cur;
+	scs->gfx_last_dw = gfx_cur;
+
+	u_log_chunk(log, &si_log_chunk_type_cs, chunk);
+}
+
+void si_auto_log_cs(void *data, struct u_log_context *log)
+{
+	struct si_context *ctx = (struct si_context *)data;
+	si_log_cs(ctx, log, false);
+}
+
+void si_log_hw_flush(struct si_context *sctx)
+{
+	if (!sctx->b.log)
+		return;
 
-	ac_parse_ib(f, sctx->last_gfx.ib, sctx->last_gfx.num_dw,
-		    last_trace_id, "IB", sctx->b.chip_class,
-		     NULL, NULL);
+	si_log_cs(sctx, sctx->b.log, true);
 }
 
 static const char *priority_to_string(enum radeon_bo_priority priority)
@@ -344,7 +509,7 @@ static void si_dump_bo_list(struct si_context *sctx,
 
 		/* Print the usage. */
 		for (j = 0; j < 64; j++) {
-			if (!(saved->bo_list[i].priority_usage & (1llu << j)))
+			if (!(saved->bo_list[i].priority_usage & (1ull << j)))
 				continue;
 
 			fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
@@ -356,7 +521,7 @@ static void si_dump_bo_list(struct si_context *sctx,
 		   "      Other buffers can still be allocated there.\n\n");
 }
 
-static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
+static void si_dump_framebuffer(struct si_context *sctx, struct u_log_context *log)
 {
 	struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
 	struct r600_texture *rtex;
@@ -367,143 +532,223 @@ static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
 			continue;
 
 		rtex = (struct r600_texture*)state->cbufs[i]->texture;
-		fprintf(f, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
-		r600_print_texture_info(sctx->b.screen, rtex, f);
-		fprintf(f, "\n");
+		u_log_printf(log, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
+		r600_print_texture_info(sctx->b.screen, rtex, log);
+		u_log_printf(log, "\n");
 	}
 
 	if (state->zsbuf) {
 		rtex = (struct r600_texture*)state->zsbuf->texture;
-		fprintf(f, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
-		r600_print_texture_info(sctx->b.screen, rtex, f);
-		fprintf(f, "\n");
+		u_log_printf(log, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
+		r600_print_texture_info(sctx->b.screen, rtex, log);
+		u_log_printf(log, "\n");
 	}
 }
 
-static void si_dump_descriptor_list(struct si_descriptors *desc,
-				    const char *shader_name,
-				    const char *elem_name,
-				    unsigned num_elements,
-				    FILE *f)
+typedef unsigned (*slot_remap_func)(unsigned);
+
+struct si_log_chunk_desc_list {
+	/** Pointer to memory map of buffer where the list is uploader */
+	uint32_t *gpu_list;
+	/** Reference of buffer where the list is uploaded, so that gpu_list
+	 * is kept live. */
+	struct r600_resource *buf;
+
+	const char *shader_name;
+	const char *elem_name;
+	slot_remap_func slot_remap;
+	unsigned element_dw_size;
+	unsigned num_elements;
+
+	uint32_t list[0];
+};
+
+static void
+si_log_chunk_desc_list_destroy(void *data)
 {
-	unsigned i, j;
-	uint32_t *cpu_list = desc->list;
-	uint32_t *gpu_list = desc->gpu_list;
-	const char *list_note = "GPU list";
+	struct si_log_chunk_desc_list *chunk = data;
+	r600_resource_reference(&chunk->buf, NULL);
+	FREE(chunk);
+}
 
-	if (!gpu_list) {
-		gpu_list = cpu_list;
-		list_note = "CPU list";
-	}
+static void
+si_log_chunk_desc_list_print(void *data, FILE *f)
+{
+	struct si_log_chunk_desc_list *chunk = data;
+
+	for (unsigned i = 0; i < chunk->num_elements; i++) {
+		unsigned cpu_dw_offset = i * chunk->element_dw_size;
+		unsigned gpu_dw_offset = chunk->slot_remap(i) * chunk->element_dw_size;
+		const char *list_note = chunk->gpu_list ? "GPU list" : "CPU list";
+		uint32_t *cpu_list = chunk->list + cpu_dw_offset;
+		uint32_t *gpu_list = chunk->gpu_list ? chunk->gpu_list + gpu_dw_offset : cpu_list;
 
-	for (i = 0; i < num_elements; i++) {
 		fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n",
-			shader_name, elem_name, i, list_note);
+			chunk->shader_name, chunk->elem_name, i, list_note);
 
-		switch (desc->element_dw_size) {
+		switch (chunk->element_dw_size) {
 		case 4:
-			for (j = 0; j < 4; j++)
+			for (unsigned j = 0; j < 4; j++)
 				ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
 					    gpu_list[j], 0xffffffff);
 			break;
 		case 8:
-			for (j = 0; j < 8; j++)
+			for (unsigned j = 0; j < 8; j++)
 				ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
 					    gpu_list[j], 0xffffffff);
 
 			fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
-			for (j = 0; j < 4; j++)
+			for (unsigned j = 0; j < 4; j++)
 				ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
 					    gpu_list[4+j], 0xffffffff);
 			break;
 		case 16:
-			for (j = 0; j < 8; j++)
+			for (unsigned j = 0; j < 8; j++)
 				ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
 					    gpu_list[j], 0xffffffff);
 
 			fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
-			for (j = 0; j < 4; j++)
+			for (unsigned j = 0; j < 4; j++)
 				ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
 					    gpu_list[4+j], 0xffffffff);
 
 			fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
-			for (j = 0; j < 8; j++)
+			for (unsigned j = 0; j < 8; j++)
 				ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
 					    gpu_list[8+j], 0xffffffff);
 
 			fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
-			for (j = 0; j < 4; j++)
+			for (unsigned j = 0; j < 4; j++)
 				ac_dump_reg(f, R_008F30_SQ_IMG_SAMP_WORD0 + j*4,
 					    gpu_list[12+j], 0xffffffff);
 			break;
 		}
 
-		if (memcmp(gpu_list, cpu_list, desc->element_dw_size * 4) != 0) {
+		if (memcmp(gpu_list, cpu_list, chunk->element_dw_size * 4) != 0) {
 			fprintf(f, COLOR_RED "!!!!! This slot was corrupted in GPU memory !!!!!"
 				COLOR_RESET "\n");
 		}
 
 		fprintf(f, "\n");
-		gpu_list += desc->element_dw_size;
-		cpu_list += desc->element_dw_size;
 	}
+
+}
+
+static const struct u_log_chunk_type si_log_chunk_type_descriptor_list = {
+	.destroy = si_log_chunk_desc_list_destroy,
+	.print = si_log_chunk_desc_list_print,
+};
+
+static void si_dump_descriptor_list(struct si_descriptors *desc,
+				    const char *shader_name,
+				    const char *elem_name,
+				    unsigned element_dw_size,
+				    unsigned num_elements,
+				    slot_remap_func slot_remap,
+				    struct u_log_context *log)
+{
+	if (!desc->list)
+		return;
+
+	struct si_log_chunk_desc_list *chunk =
+		CALLOC_VARIANT_LENGTH_STRUCT(si_log_chunk_desc_list,
+					     4 * element_dw_size * num_elements);
+	chunk->shader_name = shader_name;
+	chunk->elem_name = elem_name;
+	chunk->element_dw_size = element_dw_size;
+	chunk->num_elements = num_elements;
+	chunk->slot_remap = slot_remap;
+
+	r600_resource_reference(&chunk->buf, desc->buffer);
+	chunk->gpu_list = desc->gpu_list;
+
+	for (unsigned i = 0; i < num_elements; ++i) {
+		memcpy(&chunk->list[i * element_dw_size],
+		       &desc->list[slot_remap(i) * element_dw_size],
+		       4 * element_dw_size);
+	}
+
+	u_log_chunk(log, &si_log_chunk_type_descriptor_list, chunk);
+}
+
+static unsigned si_identity(unsigned slot)
+{
+	return slot;
 }
 
 static void si_dump_descriptors(struct si_context *sctx,
 				enum pipe_shader_type processor,
-				const struct tgsi_shader_info *info, FILE *f)
+				const struct tgsi_shader_info *info,
+				struct u_log_context *log)
 {
 	struct si_descriptors *descs =
 		&sctx->descriptors[SI_DESCS_FIRST_SHADER +
 				   processor * SI_NUM_SHADER_DESCS];
 	static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
-
-	static const char *elem_name[] = {
-		" - Constant buffer",
-		" - Shader buffer",
-		" - Sampler",
-		" - Image",
-	};
-	unsigned enabled_slots[] = {
-		sctx->const_buffers[processor].enabled_mask,
-		sctx->shader_buffers[processor].enabled_mask,
-		sctx->samplers[processor].views.enabled_mask,
-		sctx->images[processor].enabled_mask,
-	};
-	unsigned required_slots[] = {
-		info ? info->const_buffers_declared : 0,
-		info ? info->shader_buffers_declared : 0,
-		info ? info->samplers_declared : 0,
-		info ? info->images_declared : 0,
-	};
+	const char *name = shader_name[processor];
+	unsigned enabled_constbuf, enabled_shaderbuf, enabled_samplers;
+	unsigned enabled_images;
+
+	if (info) {
+		enabled_constbuf = info->const_buffers_declared;
+		enabled_shaderbuf = info->shader_buffers_declared;
+		enabled_samplers = info->samplers_declared;
+		enabled_images = info->images_declared;
+	} else {
+		enabled_constbuf = sctx->const_and_shader_buffers[processor].enabled_mask >>
+				   SI_NUM_SHADER_BUFFERS;
+		enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask &
+				    u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
+		enabled_shaderbuf = util_bitreverse(enabled_shaderbuf) >>
+				    (32 - SI_NUM_SHADER_BUFFERS);
+		enabled_samplers = sctx->samplers[processor].views.enabled_mask;
+		enabled_images = sctx->images[processor].enabled_mask;
+	}
 
 	if (processor == PIPE_SHADER_VERTEX) {
-		si_dump_descriptor_list(&sctx->vertex_buffers, shader_name[processor],
-					" - Vertex buffer", info->num_inputs, f);
+		assert(info); /* only CS may not have an info struct */
+
+		si_dump_descriptor_list(&sctx->vertex_buffers, name,
+					" - Vertex buffer", 4, info->num_inputs,
+					si_identity, log);
 	}
 
-	for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
-		si_dump_descriptor_list(descs, shader_name[processor], elem_name[i],
-					util_last_bit(enabled_slots[i] | required_slots[i]), f);
+	si_dump_descriptor_list(&descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
+				name, " - Constant buffer", 4,
+				util_last_bit(enabled_constbuf),
+				si_get_constbuf_slot, log);
+	si_dump_descriptor_list(&descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
+				name, " - Shader buffer", 4,
+				util_last_bit(enabled_shaderbuf),
+				si_get_shaderbuf_slot, log);
+	si_dump_descriptor_list(&descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
+				name, " - Sampler", 16,
+				util_last_bit(enabled_samplers),
+				si_get_sampler_slot, log);
+	si_dump_descriptor_list(&descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
+				name, " - Image", 8,
+				util_last_bit(enabled_images),
+				si_get_image_slot, log);
 }
 
 static void si_dump_gfx_descriptors(struct si_context *sctx,
 				    const struct si_shader_ctx_state *state,
-				    FILE *f)
+				    struct u_log_context *log)
 {
 	if (!state->cso || !state->current)
 		return;
 
-	si_dump_descriptors(sctx, state->cso->type, &state->cso->info, f);
+	si_dump_descriptors(sctx, state->cso->type, &state->cso->info, log);
 }
 
-static void si_dump_compute_descriptors(struct si_context *sctx, FILE *f)
+static void si_dump_compute_descriptors(struct si_context *sctx,
+					struct u_log_context *log)
 {
 	if (!sctx->cs_shader_state.program ||
 	    sctx->cs_shader_state.program != sctx->cs_shader_state.emitted_program)
 		return;
 
-	si_dump_descriptors(sctx, PIPE_SHADER_COMPUTE, NULL, f);
+	si_dump_descriptors(sctx, PIPE_SHADER_COMPUTE, NULL, log);
 }
 
 struct si_shader_inst {
@@ -782,46 +1027,48 @@ static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
 {
 	struct si_context *sctx = (struct si_context*)ctx;
 
-	if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS)
-		si_dump_debug_registers(sctx, f);
+	if (sctx->b.log)
+		u_log_flush(sctx->b.log);
 
-	if (flags & PIPE_DUMP_CURRENT_STATES)
-		si_dump_framebuffer(sctx, f);
-
-	if (flags & PIPE_DUMP_CURRENT_SHADERS) {
-		si_dump_gfx_shader(sctx->screen, &sctx->vs_shader, f);
-		si_dump_gfx_shader(sctx->screen, &sctx->tcs_shader, f);
-		si_dump_gfx_shader(sctx->screen, &sctx->tes_shader, f);
-		si_dump_gfx_shader(sctx->screen, &sctx->gs_shader, f);
-		si_dump_gfx_shader(sctx->screen, &sctx->ps_shader, f);
-		si_dump_compute_shader(sctx->screen, &sctx->cs_shader_state, f);
-
-		if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS) {
-			si_dump_annotated_shaders(sctx, f);
-			si_dump_command("Active waves (raw data)", "umr -wa | column -t", f);
-			si_dump_command("Wave information", "umr -O bits -wa", f);
-		}
+	if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS) {
+		si_dump_debug_registers(sctx, f);
 
-		si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS],
-					"", "RW buffers", SI_NUM_RW_BUFFERS, f);
-		si_dump_gfx_descriptors(sctx, &sctx->vs_shader, f);
-		si_dump_gfx_descriptors(sctx, &sctx->tcs_shader, f);
-		si_dump_gfx_descriptors(sctx, &sctx->tes_shader, f);
-		si_dump_gfx_descriptors(sctx, &sctx->gs_shader, f);
-		si_dump_gfx_descriptors(sctx, &sctx->ps_shader, f);
-		si_dump_compute_descriptors(sctx, f);
+		si_dump_annotated_shaders(sctx, f);
+		si_dump_command("Active waves (raw data)", "umr -wa | column -t", f);
+		si_dump_command("Wave information", "umr -O bits -wa", f);
 	}
+}
 
-	if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
-		si_dump_bo_list(sctx, &sctx->last_gfx, f);
-		si_dump_last_ib(sctx, f);
+void si_log_draw_state(struct si_context *sctx, struct u_log_context *log)
+{
+	if (!log)
+		return;
 
-		fprintf(f, "Done.\n");
+	si_dump_framebuffer(sctx, log);
+
+	si_dump_gfx_shader(sctx, &sctx->vs_shader, log);
+	si_dump_gfx_shader(sctx, &sctx->tcs_shader, log);
+	si_dump_gfx_shader(sctx, &sctx->tes_shader, log);
+	si_dump_gfx_shader(sctx, &sctx->gs_shader, log);
+	si_dump_gfx_shader(sctx, &sctx->ps_shader, log);
+
+	si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS],
+				"", "RW buffers", 4, SI_NUM_RW_BUFFERS,
+				si_identity, log);
+	si_dump_gfx_descriptors(sctx, &sctx->vs_shader, log);
+	si_dump_gfx_descriptors(sctx, &sctx->tcs_shader, log);
+	si_dump_gfx_descriptors(sctx, &sctx->tes_shader, log);
+	si_dump_gfx_descriptors(sctx, &sctx->gs_shader, log);
+	si_dump_gfx_descriptors(sctx, &sctx->ps_shader, log);
+}
 
-		/* dump only once */
-		radeon_clear_saved_cs(&sctx->last_gfx);
-		r600_resource_reference(&sctx->last_trace_buf, NULL);
-	}
+void si_log_compute_state(struct si_context *sctx, struct u_log_context *log)
+{
+	if (!log)
+		return;
+
+	si_dump_compute_shader(&sctx->cs_shader_state, log);
+	si_dump_compute_descriptors(sctx, log);
 }
 
 static void si_dump_dma(struct si_context *sctx,
@@ -844,7 +1091,7 @@ static void si_dump_dma(struct si_context *sctx,
 	fprintf(f, "SDMA Dump Done.\n");
 }
 
-static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
+static bool si_vm_fault_occured(struct si_context *sctx, uint64_t *out_addr)
 {
 	char line[2000];
 	unsigned sec, usec;
@@ -872,7 +1119,7 @@ static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
 			}
 			continue;
 		}
-		timestamp = sec * 1000000llu + usec;
+		timestamp = sec * 1000000ull + usec;
 
 		/* If just updating the timestamp. */
 		if (!out_addr)
@@ -899,18 +1146,35 @@ static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
 		}
 		msg++;
 
+		const char *header_line, *addr_line_prefix, *addr_line_format;
+
+		if (sctx->b.chip_class >= GFX9) {
+			/* Match this:
+			 * ..: [gfxhub] VMC page fault (src_id:0 ring:158 vm_id:2 pas_id:0)
+			 * ..:   at page 0x0000000219f8f000 from 27
+			 * ..: VM_L2_PROTECTION_FAULT_STATUS:0x0020113C
+			 */
+			header_line = "VMC page fault";
+			addr_line_prefix = "   at page";
+			addr_line_format = "%"PRIx64;
+		} else {
+			header_line = "GPU fault detected:";
+			addr_line_prefix = "VM_CONTEXT1_PROTECTION_FAULT_ADDR";
+			addr_line_format = "%"PRIX64;
+		}
+
 		switch (progress) {
 		case 0:
-			if (strstr(msg, "GPU fault detected:"))
+			if (strstr(msg, header_line))
 				progress = 1;
 			break;
 		case 1:
-			msg = strstr(msg, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
+			msg = strstr(msg, addr_line_prefix);
 			if (msg) {
 				msg = strstr(msg, "0x");
 				if (msg) {
 					msg += 2;
-					if (sscanf(msg, "%X", out_addr) == 1)
+					if (sscanf(msg, addr_line_format, out_addr) == 1)
 						fault = true;
 				}
 			}
@@ -933,7 +1197,7 @@ void si_check_vm_faults(struct r600_common_context *ctx,
 	struct si_context *sctx = (struct si_context *)ctx;
 	struct pipe_screen *screen = sctx->b.b.screen;
 	FILE *f;
-	uint32_t addr;
+	uint64_t addr;
 	char cmd_line[4096];
 
 	if (!si_vm_fault_occured(sctx, &addr))
@@ -949,20 +1213,24 @@ void si_check_vm_faults(struct r600_common_context *ctx,
 	fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen));
 	fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen));
 	fprintf(f, "Device name: %s\n\n", screen->get_name(screen));
-	fprintf(f, "Failing VM page: 0x%08x\n\n", addr);
+	fprintf(f, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
 
 	if (sctx->apitrace_call_number)
 		fprintf(f, "Last apitrace call: %u\n\n",
 			sctx->apitrace_call_number);
 
 	switch (ring) {
-	case RING_GFX:
-		si_dump_debug_state(&sctx->b.b, f,
-				    PIPE_DUMP_CURRENT_STATES |
-				    PIPE_DUMP_CURRENT_SHADERS |
-				    PIPE_DUMP_LAST_COMMAND_BUFFER);
-		break;
+	case RING_GFX: {
+		struct u_log_context log;
+		u_log_context_init(&log);
 
+		si_log_draw_state(sctx, &log);
+		si_log_compute_state(sctx, &log);
+
+		u_log_new_page_print(&log, f);
+		u_log_context_destroy(&log);
+		break;
+	}
 	case RING_DMA:
 		si_dump_dma(sctx, saved, f);
 		break;