X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_dma.c;h=c277673c2dff3f5ec41cdb02cd24bb4aa8597957;hb=3b143369a55d1b79f7db14dda587e18f6b27c975;hp=d33ec6b11b3f411a1725567fa28a745d2d1a898f;hpb=529cdce799f30606ee857599f34de3ec9014dc09;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c index d33ec6b11b3..c277673c2df 100644 --- a/src/gallium/drivers/radeonsi/si_dma.c +++ b/src/gallium/drivers/radeonsi/si_dma.c @@ -1,5 +1,7 @@ /* * Copyright 2010 Jerome Glisse + * Copyright 2018 Advanced Micro Devices, Inc. + * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -24,7 +26,7 @@ #include "sid.h" #include "si_pipe.h" -#include "util/u_format.h" +#include "util/format/u_format.h" static void si_dma_copy_buffer(struct si_context *ctx, struct pipe_resource *dst, @@ -33,19 +35,19 @@ static void si_dma_copy_buffer(struct si_context *ctx, uint64_t src_offset, uint64_t size) { - struct radeon_winsys_cs *cs = ctx->b.dma.cs; + struct radeon_cmdbuf *cs = ctx->dma_cs; unsigned i, ncopy, count, max_size, sub_cmd, shift; - struct r600_resource *rdst = (struct r600_resource*)dst; - struct r600_resource *rsrc = (struct r600_resource*)src; + struct si_resource *sdst = si_resource(dst); + struct si_resource *ssrc = si_resource(src); /* Mark the buffer range of destination as valid (initialized), * so that transfer_map knows it should wait for the GPU when mapping * that range. */ - util_range_add(&rdst->valid_buffer_range, dst_offset, + util_range_add(dst, &sdst->valid_buffer_range, dst_offset, dst_offset + size); - dst_offset += rdst->gpu_address; - src_offset += rsrc->gpu_address; + dst_offset += sdst->gpu_address; + src_offset += ssrc->gpu_address; /* see whether we should use the dword-aligned or byte-aligned copy */ if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) { @@ -59,7 +61,7 @@ static void si_dma_copy_buffer(struct si_context *ctx, } ncopy = DIV_ROUND_UP(size, max_size); - si_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc); + si_need_dma_space(ctx, ncopy * 5, sdst, ssrc); for (i = 0; i < ncopy; i++) { count = MIN2(size, max_size); @@ -75,46 +77,6 @@ static void si_dma_copy_buffer(struct si_context *ctx, } } -static void si_dma_clear_buffer(struct pipe_context *ctx, - struct pipe_resource *dst, - uint64_t offset, - uint64_t size, - unsigned clear_value) -{ - struct si_context *sctx = (struct si_context *)ctx; - struct radeon_winsys_cs *cs = sctx->b.dma.cs; - unsigned i, ncopy, csize; - struct r600_resource *rdst = r600_resource(dst); - - if (!cs || offset % 4 != 0 || size % 4 != 0 || - dst->flags & PIPE_RESOURCE_FLAG_SPARSE) { - ctx->clear_buffer(ctx, dst, offset, size, &clear_value, 4); - return; - } - - /* Mark the buffer range of destination as valid (initialized), - * so that transfer_map knows it should wait for the GPU when mapping - * that range. */ - util_range_add(&rdst->valid_buffer_range, offset, offset + size); - - offset += rdst->gpu_address; - - /* the same maximum size as for copying */ - ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE); - si_need_dma_space(&sctx->b, ncopy * 4, rdst, NULL); - - for (i = 0; i < ncopy; i++) { - csize = MIN2(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE); - radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_CONSTANT_FILL, 0, - csize / 4)); - radeon_emit(cs, offset); - radeon_emit(cs, clear_value); - radeon_emit(cs, (offset >> 32) << 16); - offset += csize; - size -= csize; - } -} - static void si_dma_copy_tile(struct si_context *ctx, struct pipe_resource *dst, unsigned dst_level, @@ -130,17 +92,17 @@ static void si_dma_copy_tile(struct si_context *ctx, unsigned pitch, unsigned bpp) { - struct radeon_winsys_cs *cs = ctx->b.dma.cs; - struct r600_texture *rsrc = (struct r600_texture*)src; - struct r600_texture *rdst = (struct r600_texture*)dst; - unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode; + struct radeon_cmdbuf *cs = ctx->dma_cs; + struct si_texture *ssrc = (struct si_texture*)src; + struct si_texture *sdst = (struct si_texture*)dst; + unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode; bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED; - struct r600_texture *rlinear = detile ? rdst : rsrc; - struct r600_texture *rtiled = detile ? rsrc : rdst; + struct si_texture *linear = detile ? sdst : ssrc; + struct si_texture *tiled = detile ? ssrc : sdst; unsigned linear_lvl = detile ? dst_level : src_level; unsigned tiled_lvl = detile ? src_level : dst_level; - struct radeon_info *info = &ctx->screen->b.info; - unsigned index = rtiled->surface.u.legacy.tiling_index[tiled_lvl]; + struct radeon_info *info = &ctx->screen->info; + unsigned index = tiled->surface.u.legacy.tiling_index[tiled_lvl]; unsigned tile_mode = info->si_tile_mode_array[index]; unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; unsigned ncopy, height, cheight, i; @@ -149,7 +111,7 @@ static void si_dma_copy_tile(struct si_context *ctx, uint64_t base, addr; unsigned pipe_config; - assert(dst_mode != rsrc->surface.u.legacy.level[src_level].mode); + assert(dst_mode != ssrc->surface.u.legacy.level[src_level].mode); sub_cmd = SI_DMA_COPY_TILED; lbpp = util_logbase2(bpp); @@ -162,35 +124,35 @@ static void si_dma_copy_tile(struct si_context *ctx, tiled_y = detile ? src_y : dst_y; tiled_z = detile ? src_z : dst_z; - assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format)); + assert(!util_format_is_depth_and_stencil(tiled->buffer.b.b.format)); array_mode = G_009910_ARRAY_MODE(tile_mode); - slice_tile_max = (rtiled->surface.u.legacy.level[tiled_lvl].nblk_x * - rtiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1; + slice_tile_max = (tiled->surface.u.legacy.level[tiled_lvl].nblk_x * + tiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1; /* linear height must be the same as the slice tile max height, it's ok even * if the linear destination/source have smaller heigh as the size of the * dma packet will be using the copy_height which is always smaller or equal * to the linear height */ - height = rtiled->surface.u.legacy.level[tiled_lvl].nblk_y; - base = rtiled->surface.u.legacy.level[tiled_lvl].offset; - addr = rlinear->surface.u.legacy.level[linear_lvl].offset; - addr += rlinear->surface.u.legacy.level[linear_lvl].slice_size * linear_z; + height = tiled->surface.u.legacy.level[tiled_lvl].nblk_y; + base = tiled->surface.u.legacy.level[tiled_lvl].offset; + addr = linear->surface.u.legacy.level[linear_lvl].offset; + addr += (uint64_t)linear->surface.u.legacy.level[linear_lvl].slice_size_dw * 4 * linear_z; addr += linear_y * pitch + linear_x * bpp; bank_h = G_009910_BANK_HEIGHT(tile_mode); bank_w = G_009910_BANK_WIDTH(tile_mode); mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode); /* Non-depth modes don't have TILE_SPLIT set. */ - tile_split = util_logbase2(rtiled->surface.u.legacy.tile_split >> 6); + tile_split = util_logbase2(tiled->surface.u.legacy.tile_split >> 6); nbanks = G_009910_NUM_BANKS(tile_mode); - base += rtiled->resource.gpu_address; - addr += rlinear->resource.gpu_address; + base += tiled->buffer.gpu_address; + addr += linear->buffer.gpu_address; pipe_config = G_009910_PIPE_CONFIG(tile_mode); mt = G_009910_MICRO_TILE_MODE(tile_mode); size = copy_height * pitch; ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE); - si_need_dma_space(&ctx->b, ncopy * 9, &rdst->resource, &rsrc->resource); + si_need_dma_space(ctx, ncopy * 9, &sdst->buffer, &ssrc->buffer); for (i = 0; i < ncopy; i++) { cheight = copy_height; @@ -224,14 +186,14 @@ static void si_dma_copy(struct pipe_context *ctx, const struct pipe_box *src_box) { struct si_context *sctx = (struct si_context *)ctx; - struct r600_texture *rsrc = (struct r600_texture*)src; - struct r600_texture *rdst = (struct r600_texture*)dst; + struct si_texture *ssrc = (struct si_texture*)src; + struct si_texture *sdst = (struct si_texture*)dst; unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode; unsigned src_w, dst_w; unsigned src_x, src_y; unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz; - if (sctx->b.dma.cs == NULL || + if (sctx->dma_cs == NULL || src->flags & PIPE_RESOURCE_FLAG_SPARSE || dst->flags & PIPE_RESOURCE_FLAG_SPARSE) { goto fallback; @@ -258,8 +220,8 @@ static void si_dma_copy(struct pipe_context *ctx, goto fallback; if (src_box->depth > 1 || - !si_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty, - dstz, rsrc, src_level, src_box)) + !si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty, + dstz, ssrc, src_level, src_box)) goto fallback; src_x = util_format_get_nblocksx(src->format, src_box->x); @@ -267,21 +229,21 @@ static void si_dma_copy(struct pipe_context *ctx, src_y = util_format_get_nblocksy(src->format, src_box->y); dst_y = util_format_get_nblocksy(src->format, dst_y); - bpp = rdst->surface.bpe; - dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; - src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; - src_w = u_minify(rsrc->resource.b.b.width0, src_level); - dst_w = u_minify(rdst->resource.b.b.width0, dst_level); + bpp = sdst->surface.bpe; + dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x * sdst->surface.bpe; + src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x * ssrc->surface.bpe; + src_w = u_minify(ssrc->buffer.b.b.width0, src_level); + dst_w = u_minify(sdst->buffer.b.b.width0, dst_level); - dst_mode = rdst->surface.u.legacy.level[dst_level].mode; - src_mode = rsrc->surface.u.legacy.level[src_level].mode; + dst_mode = sdst->surface.u.legacy.level[dst_level].mode; + src_mode = ssrc->surface.u.legacy.level[src_level].mode; if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w || src_box->width != src_w || - src_box->height != u_minify(rsrc->resource.b.b.height0, src_level) || - src_box->height != u_minify(rdst->resource.b.b.height0, dst_level) || - rsrc->surface.u.legacy.level[src_level].nblk_y != - rdst->surface.u.legacy.level[dst_level].nblk_y) { + src_box->height != u_minify(ssrc->buffer.b.b.height0, src_level) || + src_box->height != u_minify(sdst->buffer.b.b.height0, dst_level) || + ssrc->surface.u.legacy.level[src_level].nblk_y != + sdst->surface.u.legacy.level[dst_level].nblk_y) { /* FIXME si can do partial blit */ goto fallback; } @@ -300,18 +262,18 @@ static void si_dma_copy(struct pipe_context *ctx, * dst_x/y == 0 * dst_pitch == src_pitch */ - src_offset= rsrc->surface.u.legacy.level[src_level].offset; - src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z; + src_offset= ssrc->surface.u.legacy.level[src_level].offset; + src_offset += (uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z; src_offset += src_y * src_pitch + src_x * bpp; - dst_offset = rdst->surface.u.legacy.level[dst_level].offset; - dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z; + dst_offset = sdst->surface.u.legacy.level[dst_level].offset; + dst_offset += (uint64_t)sdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; dst_offset += dst_y * dst_pitch + dst_x * bpp; si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, - rsrc->surface.u.legacy.level[src_level].slice_size); + (uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4); } else { si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z, src, src_level, src_x, src_y, src_box->z, - src_box->height / rsrc->surface.blk_h, + src_box->height / ssrc->surface.blk_h, dst_pitch, bpp); } return; @@ -323,6 +285,5 @@ fallback: void si_init_dma_functions(struct si_context *sctx) { - sctx->b.dma_copy = si_dma_copy; - sctx->b.dma_clear_buffer = si_dma_clear_buffer; + sctx->dma_copy = si_dma_copy; }