X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_get.c;h=01050cf02b4dd9beea5fe4c9b084882b3acfeb75;hb=34ea55d8201b9bfd31dd432f45b5423861f8ad0b;hp=f75c97685ce07a15d68218c4070053c8df3699f1;hpb=2be6143032939c5c5fb6de4a44ffe3b076e1f098;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index f75c97685ce..01050cf02b4 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -1,5 +1,6 @@ /* * Copyright 2017 Advanced Micro Devices, Inc. + * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -70,10 +71,11 @@ const char *si_get_family_name(const struct si_screen *sscreen) case CHIP_ICELAND: return "AMD ICELAND"; case CHIP_CARRIZO: return "AMD CARRIZO"; case CHIP_FIJI: return "AMD FIJI"; + case CHIP_STONEY: return "AMD STONEY"; case CHIP_POLARIS10: return "AMD POLARIS10"; case CHIP_POLARIS11: return "AMD POLARIS11"; case CHIP_POLARIS12: return "AMD POLARIS12"; - case CHIP_STONEY: return "AMD STONEY"; + case CHIP_VEGAM: return "AMD VEGAM"; case CHIP_VEGA10: return "AMD VEGA10"; case CHIP_VEGA12: return "AMD VEGA12"; case CHIP_RAVEN: return "AMD RAVEN"; @@ -81,16 +83,6 @@ const char *si_get_family_name(const struct si_screen *sscreen) } } -static bool si_have_tgsi_compute(struct si_screen *sscreen) -{ - /* Old kernels disallowed some register writes for SI - * that are used for indirect dispatches. */ - return (sscreen->info.chip_class >= CIK || - sscreen->info.drm_major == 3 || - (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor >= 45)); -} - static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) { struct si_screen *sscreen = (struct si_screen *)pscreen; @@ -159,6 +151,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: case PIPE_CAP_INVALIDATE_BUFFER: case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: + case PIPE_CAP_QUERY_BUFFER_OBJECT: case PIPE_CAP_QUERY_MEMORY_INFO: case PIPE_CAP_TGSI_PACK_HALF_FLOAT: case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: @@ -190,30 +183,23 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: + case PIPE_CAP_TGSI_BALLOT: case PIPE_CAP_TGSI_VOTE: case PIPE_CAP_TGSI_FS_FBFETCH: return 1; - case PIPE_CAP_TGSI_BALLOT: - return HAVE_LLVM >= 0x0500; - case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: return !SI_BIG_ENDIAN && sscreen->info.has_userptr; case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: - return (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor >= 43) || - sscreen->info.drm_major == 3; + return sscreen->info.has_gpu_reset_status_query || + sscreen->info.has_gpu_reset_counter_query; case PIPE_CAP_TEXTURE_MULTISAMPLE: - /* 2D tiling on CIK is supported since DRM 2.35.0 */ - return sscreen->info.chip_class < CIK || - (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor >= 35) || - sscreen->info.drm_major == 3; + return sscreen->info.has_2d_tiling; case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: - return R600_MAP_BUFFER_ALIGNMENT; + return SI_MAP_BUFFER_ALIGNMENT; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: @@ -224,34 +210,24 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 4; case PIPE_CAP_GLSL_FEATURE_LEVEL: - if (si_have_tgsi_compute(sscreen)) + if (sscreen->info.has_indirect_compute_dispatch) return 450; return 420; + case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: + return 140; + case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: return MIN2(sscreen->info.max_alloc_size, INT_MAX); case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - /* SI doesn't support unaligned loads. - * CIK needs DRM 2.50.0 on radeon. */ - return sscreen->info.chip_class == SI || - (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor < 50); + return !sscreen->info.has_unaligned_shader_loads; case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: - /* TODO: GFX9 hangs. */ - if (sscreen->info.chip_class >= GFX9) - return 0; - /* Disable on SI due to VM faults in CP DMA. Enable once these - * faults are mitigated in software. - */ - if (sscreen->info.chip_class >= CIK && - sscreen->info.drm_major == 3 && - sscreen->info.drm_minor >= 13) - return RADEON_SPARSE_PAGE_SIZE; - return 0; + return sscreen->info.has_sparse_vm_mappings ? + RADEON_SPARSE_PAGE_SIZE : 0; case PIPE_CAP_PACKED_UNIFORMS: if (sscreen->debug_flags & DBG(NIR)) @@ -275,20 +251,23 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TILE_RASTER_ORDER: case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: case PIPE_CAP_CONTEXT_PRIORITY_MASK: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: + case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: + case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: + case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: return 0; case PIPE_CAP_FENCE_SIGNAL: return sscreen->info.has_syncobj; case PIPE_CAP_CONSTBUF0_FLAGS: - return R600_RESOURCE_FLAG_32BIT; + return SI_RESOURCE_FLAG_32BIT; case PIPE_CAP_NATIVE_FENCE_FD: return sscreen->info.has_fence_to_handle; - case PIPE_CAP_QUERY_BUFFER_OBJECT: - return si_have_tgsi_compute(sscreen); - case PIPE_CAP_DRAW_PARAMETERS: case PIPE_CAP_MULTI_DRAW_INDIRECT: case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: @@ -374,6 +353,10 @@ static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param) return 16.0f; case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: return 16.0f; + case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: + case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: + case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: + return 0.0f; } return 0.0f; } @@ -397,7 +380,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_SUPPORTED_IRS: { int ir = 1 << PIPE_SHADER_IR_NATIVE; - if (si_have_tgsi_compute(sscreen)) + if (sscreen->info.has_indirect_compute_dispatch) ir |= 1 << PIPE_SHADER_IR_TGSI; return ir; @@ -475,12 +458,28 @@ static int si_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* TODO: Indirect indexing of GS inputs is unimplemented. */ - return shader != PIPE_SHADER_GEOMETRY && - (sscreen->llvm_has_working_vgpr_indexing || - /* TCS and TES load inputs directly from LDS or - * offchip memory, so indirect indexing is trivial. */ - shader == PIPE_SHADER_TESS_CTRL || - shader == PIPE_SHADER_TESS_EVAL); + if (shader == PIPE_SHADER_GEOMETRY) + return 0; + + if (shader == PIPE_SHADER_VERTEX && + !sscreen->llvm_has_working_vgpr_indexing) + return 0; + + /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs. + * This means we don't support INTERP instructions with + * indirect indexing on inputs. + */ + if (shader == PIPE_SHADER_FRAGMENT && + !sscreen->llvm_has_working_vgpr_indexing && + HAVE_LLVM < 0x0700) + return 0; + + /* TCS and TES load inputs directly from LDS or offchip + * memory, so indirect indexing is always supported. + * PS has to support indirect indexing, because we can't + * lower that to TEMPs for INTERP instructions. + */ + return 1; case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: return sscreen->llvm_has_working_vgpr_indexing || @@ -647,6 +646,10 @@ static int si_get_video_param(struct pipe_screen *screen, return false; } return true; + case PIPE_VIDEO_FORMAT_VP9: + if (sscreen->info.family < CHIP_RAVEN) + return false; + return true; default: return false; } @@ -657,7 +660,8 @@ static int si_get_video_param(struct pipe_screen *screen, case PIPE_VIDEO_CAP_MAX_HEIGHT: return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096; case PIPE_VIDEO_CAP_PREFERED_FORMAT: - if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) + if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 || + profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) return PIPE_FORMAT_P016; else return PIPE_FORMAT_NV12; @@ -670,6 +674,8 @@ static int si_get_video_param(struct pipe_screen *screen, return false; //The firmware doesn't support interlaced HEVC. else if (format == PIPE_VIDEO_FORMAT_JPEG) return false; + else if (format == PIPE_VIDEO_FORMAT_VP9) + return false; return true; } case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: @@ -945,32 +951,29 @@ static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen) static void si_init_renderer_string(struct si_screen *sscreen) { struct radeon_winsys *ws = sscreen->ws; - char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {}; + char family_name[32] = {}, kernel_version[128] = {}; struct utsname uname_data; const char *chip_name = si_get_marketing_name(ws); if (chip_name) - snprintf(family_name, sizeof(family_name), "%s / ", + snprintf(family_name, sizeof(family_name), "%s, ", si_get_family_name(sscreen) + 4); else chip_name = si_get_family_name(sscreen); if (uname(&uname_data) == 0) snprintf(kernel_version, sizeof(kernel_version), - " / %s", uname_data.release); - - if (HAVE_LLVM > 0) { - snprintf(llvm_string, sizeof(llvm_string), - ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff, - HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH); - } + ", %s", uname_data.release); snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string), - "%s (%sDRM %i.%i.%i%s%s)", + "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)", chip_name, family_name, sscreen->info.drm_major, sscreen->info.drm_minor, sscreen->info.drm_patchlevel, - kernel_version, llvm_string); + kernel_version, + (HAVE_LLVM >> 8) & 0xff, + HAVE_LLVM & 0xff, + MESA_LLVM_VERSION_PATCH); } void si_init_screen_get_functions(struct si_screen *sscreen)