X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_get.c;h=8dc13ee08b2ba52e72c23a3793d81be1f0a18673;hb=f671cc4d95eaf9ecfaafb216afeff7dc89f66cbf;hp=c1bddca1a660d5a9cf27e34646d7a4af83af557e;hpb=abe9a51d27049971c77a0072693511caf9b793e2;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index c1bddca1a66..8dc13ee08b2 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -33,6 +33,7 @@ #include "util/u_video.h" #include "compiler/nir/nir.h" +#include #include static const char *si_get_vendor(struct pipe_screen *pscreen) @@ -71,7 +72,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: - case PIPE_CAP_SM3: + case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: + case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: + case PIPE_CAP_VERTEX_SHADER_SATURATE: case PIPE_CAP_SEAMLESS_CUBE_MAP: case PIPE_CAP_PRIMITIVE_RESTART: case PIPE_CAP_CONDITIONAL_RENDER: @@ -140,7 +143,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_QUERY_TIMESTAMP: case PIPE_CAP_QUERY_TIME_ELAPSED: case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: - case PIPE_CAP_QUERY_SO_OVERFLOW: case PIPE_CAP_MEMOBJ: case PIPE_CAP_LOAD_CONSTBUF: case PIPE_CAP_INT64: @@ -155,9 +157,19 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_FBFETCH: case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK: case PIPE_CAP_IMAGE_LOAD_FORMATTED: - case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA: + case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA: + case PIPE_CAP_TGSI_DIV: return 1; + case PIPE_CAP_QUERY_SO_OVERFLOW: + return !sscreen->use_ngg_streamout; + + case PIPE_CAP_POST_DEPTH_COVERAGE: + return sscreen->info.chip_class >= GFX10; + + case PIPE_CAP_GRAPHICS: + return sscreen->info.has_graphics; + case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: return !SI_BIG_ENDIAN && sscreen->info.has_userptr; @@ -196,17 +208,23 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - return HAVE_LLVM < 0x0900 && !sscreen->info.has_unaligned_shader_loads; + return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads; case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: return sscreen->info.has_sparse_vm_mappings ? RADEON_SPARSE_PAGE_SIZE : 0; case PIPE_CAP_PACKED_UNIFORMS: + case PIPE_CAP_SHADER_SAMPLES_IDENTICAL: if (sscreen->options.enable_nir) return 1; return 0; + case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF: + if (sscreen->options.enable_nir) + return 0; + return 1; + /* Unsupported features. */ case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: @@ -219,7 +237,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_MUL_ZERO_WINS: case PIPE_CAP_UMA: case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: - case PIPE_CAP_POST_DEPTH_COVERAGE: case PIPE_CAP_TILE_RASTER_ORDER: case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: case PIPE_CAP_CONTEXT_PRIORITY_MASK: @@ -263,7 +280,10 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) /* Geometry shader output. */ case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: - return 1024; + /* gfx9 has to report 256 to make piglit/gs-max-output pass. + * gfx8 and earlier can do 1024. + */ + return 256; case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: return 4095; case PIPE_CAP_MAX_GS_INVOCATIONS: @@ -280,9 +300,13 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: return 15; /* 16384 */ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: + if (sscreen->info.chip_class >= GFX10) + return 14; /* textures support 8192, but layered rendering supports 2048 */ return 12; case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: + if (sscreen->info.chip_class >= GFX10) + return 8192; /* textures support 8192, but layered rendering supports 2048 */ return 2048; @@ -321,6 +345,8 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return sscreen->info.pci_dev; case PIPE_CAP_PCI_FUNCTION: return sscreen->info.pci_func; + case PIPE_CAP_TGSI_ATOMINC_WRAP: + return LLVM_VERSION_MAJOR >= 10; default: return u_pipe_screen_get_param_defaults(pscreen, param); @@ -472,8 +498,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; - case PIPE_SHADER_CAP_SCALAR_ISA: - return 1; } return 0; } @@ -484,12 +508,12 @@ static const struct nir_shader_compiler_options nir_options = { .lower_flrp64 = true, .lower_fsat = true, .lower_fdiv = true, + .lower_bitfield_insert_to_bitfield_select = true, + .lower_bitfield_extract = true, .lower_sub = true, - .lower_ffma = true, + .fuse_ffma = true, .lower_fmod = true, - .lower_pack_snorm_2x16 = true, .lower_pack_snorm_4x8 = true, - .lower_pack_unorm_2x16 = true, .lower_pack_unorm_4x8 = true, .lower_unpack_snorm_2x16 = true, .lower_unpack_snorm_4x8 = true, @@ -497,8 +521,11 @@ static const struct nir_shader_compiler_options nir_options = { .lower_unpack_unorm_4x8 = true, .lower_extract_byte = true, .lower_extract_word = true, + .lower_rotate = true, + .lower_to_scalar = true, .optimize_sample_mask_in = true, .max_unroll_iterations = 32, + .use_interpolated_input_intrinsics = true, }; static const void * @@ -570,12 +597,10 @@ static int si_get_video_param(struct pipe_screen *screen, case PIPE_VIDEO_CAP_SUPPORTED: return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC && (si_vce_is_fw_version_supported(sscreen) || - sscreen->info.family == CHIP_RAVEN || - sscreen->info.family == CHIP_RAVEN2)) || + sscreen->info.family >= CHIP_RAVEN)) || (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN && - (sscreen->info.family == CHIP_RAVEN || - sscreen->info.family == CHIP_RAVEN2 || - si_radeon_uvd_enc_supported(sscreen))); + (sscreen->info.family >= CHIP_RAVEN || + si_radeon_uvd_enc_supported(sscreen))); case PIPE_VIDEO_CAP_NPOT_TEXTURES: return 1; case PIPE_VIDEO_CAP_MAX_WIDTH: @@ -623,8 +648,7 @@ static int si_get_video_param(struct pipe_screen *screen, return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN; return false; case PIPE_VIDEO_FORMAT_JPEG: - if (sscreen->info.family == CHIP_RAVEN || - sscreen->info.family == CHIP_RAVEN2) + if (sscreen->info.family >= CHIP_RAVEN) return true; if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10) return false; @@ -643,9 +667,25 @@ static int si_get_video_param(struct pipe_screen *screen, case PIPE_VIDEO_CAP_NPOT_TEXTURES: return 1; case PIPE_VIDEO_CAP_MAX_WIDTH: - return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096; + switch (codec) { + case PIPE_VIDEO_FORMAT_HEVC: + case PIPE_VIDEO_FORMAT_VP9: + return (sscreen->info.family < CHIP_RENOIR) ? + ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) : + 8192; + default: + return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096; + } case PIPE_VIDEO_CAP_MAX_HEIGHT: - return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096; + switch (codec) { + case PIPE_VIDEO_FORMAT_HEVC: + case PIPE_VIDEO_FORMAT_VP9: + return (sscreen->info.family < CHIP_RENOIR) ? + ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) : + 4352; + default: + return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096; + } case PIPE_VIDEO_CAP_PREFERED_FORMAT: if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 || profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) @@ -699,16 +739,21 @@ static int si_get_video_param(struct pipe_screen *screen, } } -static boolean si_vid_is_format_supported(struct pipe_screen *screen, - enum pipe_format format, - enum pipe_video_profile profile, - enum pipe_video_entrypoint entrypoint) +static bool si_vid_is_format_supported(struct pipe_screen *screen, + enum pipe_format format, + enum pipe_video_profile profile, + enum pipe_video_entrypoint entrypoint) { /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */ if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P016); + /* Vp9 profile 2 supports 10 bit decoding using P016 */ + if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) + return format == PIPE_FORMAT_P016; + + /* we can only handle this one with UVD */ if (profile != PIPE_VIDEO_PROFILE_UNKNOWN) return format == PIPE_FORMAT_NV12; @@ -722,14 +767,8 @@ static unsigned get_max_threads_per_block(struct si_screen *screen, if (ir_type == PIPE_SHADER_IR_NATIVE) return 256; - /* Only 16 waves per thread-group on gfx9. */ - if (screen->info.chip_class >= GFX9) - return 1024; - - /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice - * round number. - */ - return 2048; + /* LLVM 10 only supports 1024 threads per block. */ + return 1024; } static int si_get_compute_param(struct pipe_screen *screen, @@ -861,7 +900,7 @@ static int si_get_compute_param(struct pipe_screen *screen, case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: if (ret) { uint32_t *subgroup_size = ret; - *subgroup_size = 64; + *subgroup_size = sscreen->compute_wave_size; } return sizeof(uint32_t); case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: