X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_pipe.c;h=2bd96eaef1cbbe53ea8f132e68d5a0454f9d24cd;hb=6a8aaf7c00743a5c184960b0e275f319a16a4433;hp=e366b6b5458bd1c1aad5af8cac8ded5ab1d781c4;hpb=babd87f2e0865fde1386c4797131c26265b2da09;p=mesa.git

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index e366b6b5458..2bd96eaef1c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -33,6 +33,7 @@
 #include "si_public.h"
 #include "si_shader_internal.h"
 #include "sid.h"
+#include "ac_shadowed_regs.h"
 #include "util/disk_cache.h"
 #include "util/u_log.h"
 #include "util/u_memory.h"
@@ -90,6 +91,7 @@ static const struct debug_named_value debug_options[] = {
    {"check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info."},
    {"reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context."},
    {"zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations."},
+   {"shadowregs", DBG(SHADOW_REGS), "Enable CP register shadowing."},
 
    /* 3D engine options: */
    {"nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used."},
@@ -297,6 +299,7 @@ static void si_destroy_context(struct pipe_context *context)
    si_resource_reference(&sctx->index_ring, NULL);
    si_resource_reference(&sctx->barrier_buf, NULL);
    si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
+   si_resource_reference(&sctx->shadowed_regs, NULL);
    pb_reference(&sctx->gds, NULL);
    pb_reference(&sctx->gds_oa, NULL);
 
@@ -480,6 +483,14 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
         *    https://gitlab.freedesktop.org/mesa/mesa/-/issues/1889
         */
        (sctx->chip_class != GFX8 || sscreen->debug_flags & DBG(FORCE_SDMA)) &&
+       /* SDMA causes corruption on gfx9 APUs:
+        *    https://gitlab.freedesktop.org/mesa/mesa/-/issues/2814
+        *
+        * While we could keep buffer copies and clears enabled, let's disable
+        * everything, because neither gfx8 nor gfx10 enable SDMA, and it's not
+        * easy to test.
+        */
+       (sctx->chip_class != GFX9 || sscreen->debug_flags & DBG(FORCE_SDMA)) &&
        /* SDMA timeouts sometimes on gfx10 so disable it for now. See:
         *    https://bugs.freedesktop.org/show_bug.cgi?id=111481
         *    https://gitlab.freedesktop.org/mesa/mesa/-/issues/1907
@@ -552,7 +563,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
       si_init_msaa_functions(sctx);
       si_init_shader_functions(sctx);
       si_init_state_functions(sctx);
-      si_init_cs_preamble_state(sctx);
       si_init_streamout_functions(sctx);
       si_init_viewport_functions(sctx);
 
@@ -669,7 +679,12 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
 
    /* The remainder of this function initializes the gfx CS and must be last. */
    assert(sctx->gfx_cs->current.cdw == 0);
-   si_begin_new_gfx_cs(sctx);
+
+   if (sctx->has_graphics) {
+      si_init_cp_reg_shadowing(sctx);
+   }
+
+   si_begin_new_gfx_cs(sctx, true);
    assert(sctx->gfx_cs->current.cdw == sctx->initial_gfx_cs_size);
 
    /* Initialize per-context buffers. */
@@ -1137,6 +1152,11 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
       driQueryOptionb(config->options, "radeonsi_commutative_blend_add") ||
       driQueryOptionb(config->options, "allow_draw_out_of_order");
 
+   /* TODO: Find out why NGG culling hangs on gfx10.3 */
+   if (sscreen->info.chip_class == GFX10_3 &&
+       !(sscreen->debug_flags & (DBG(ALWAYS_NGG_CULLING_ALL) | DBG(ALWAYS_NGG_CULLING_TESS))))
+      sscreen->debug_flags |= DBG(NO_NGG_CULLING);
+
    sscreen->use_ngg = sscreen->info.chip_class >= GFX10 && sscreen->info.family != CHIP_NAVI14 &&
                       !(sscreen->debug_flags & DBG(NO_NGG));
    sscreen->use_ngg_culling = sscreen->use_ngg && !(sscreen->debug_flags & DBG(NO_NGG_CULLING));
@@ -1275,6 +1295,8 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
                                     RADEON_DOMAIN_OA);
    }
 
+   ac_print_shadowed_regs(&sscreen->info);
+
    STATIC_ASSERT(sizeof(union si_vgt_stages_key) == 4);
    return &sscreen->b;
 }