X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_pipe.c;h=99fa2b40c7a8bbce47b8886f01bb27db60839b4c;hb=1c1d34a67ac037facabe085f030c94cae46f574d;hp=e3ba1c2fb938c1c56242f0cdfbac617480aa5132;hpb=dcb1e8fef8ae60877a696a5bca337eba5475085d;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index e3ba1c2fb93..99fa2b40c7a 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -67,6 +67,7 @@ static const struct debug_named_value debug_options[] = { {"w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders."}, {"w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders."}, {"w64cs", DBG(W64_CS), "Use Wave64 for computes shaders."}, + {"noinfinterp", DBG(KILL_PS_INF_INTERP), "Kill PS with infinite interp coeff"}, /* Shader compiler options (with no effect on the shader cache): */ {"checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR"}, @@ -140,8 +141,8 @@ void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compil enum ac_target_machine_options tm_options = (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) | - (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) | - (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) | + (sscreen->info.chip_class <= GFX8 ? AC_TM_FORCE_DISABLE_XNACK : + sscreen->info.chip_class <= GFX10 ? AC_TM_FORCE_ENABLE_XNACK : 0) | (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) | (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) | (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0); @@ -193,9 +194,9 @@ static void si_destroy_context(struct pipe_context *context) si_resource_reference(&sctx->wait_mem_scratch, NULL); si_resource_reference(&sctx->small_prim_cull_info_buf, NULL); - si_pm4_free_state(sctx, sctx->init_config, ~0); - if (sctx->init_config_gs_rings) - si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0); + si_pm4_free_state(sctx, sctx->cs_preamble_state, ~0); + if (sctx->cs_preamble_gs_rings) + si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0); for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++) si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]); @@ -235,6 +236,8 @@ static void si_destroy_context(struct pipe_context *context) sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array); if (sctx->cs_clear_12bytes_buffer) sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer); + if (sctx->cs_dcc_decompress) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_decompress); if (sctx->cs_dcc_retile) sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile); @@ -319,7 +322,7 @@ static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx) enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx); if (status != PIPE_NO_RESET) { - /* Call the state tracker to set a no-op API dispatch. */ + /* Call the gallium frontend to set a no-op API dispatch. */ if (sctx->device_reset_callback.reset) { sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status); } @@ -471,13 +474,13 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign if (sscreen->info.num_rings[RING_DMA] && !(sscreen->debug_flags & DBG(NO_SDMA)) && /* SDMA causes corruption on RX 580: - * https://gitlab.freedesktop.org/mesa/mesa/issues/1399 - * https://gitlab.freedesktop.org/mesa/mesa/issues/1889 + * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1399 + * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1889 */ (sctx->chip_class != GFX8 || sscreen->debug_flags & DBG(FORCE_SDMA)) && /* SDMA timeouts sometimes on gfx10 so disable it for now. See: * https://bugs.freedesktop.org/show_bug.cgi?id=111481 - * https://gitlab.freedesktop.org/mesa/mesa/issues/1907 + * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1907 */ (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_SDMA))) { sctx->sdma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA, (void *)si_flush_dma_cs, sctx, @@ -547,6 +550,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign si_init_msaa_functions(sctx); si_init_shader_functions(sctx); si_init_state_functions(sctx); + si_init_cs_preamble_state(sctx); si_init_streamout_functions(sctx); si_init_viewport_functions(sctx); @@ -712,7 +716,7 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, v sscreen->info.is_amdgpu ? si_create_fence : NULL, &((struct si_context *)ctx)->tc); - if (os_get_total_physical_memory(&total_ram)) { + if (tc && tc != ctx && os_get_total_physical_memory(&total_ram)) { ((struct threaded_context *) tc)->bytes_mapped_limit = total_ram / 4; } @@ -850,7 +854,7 @@ static void si_test_gds_memory_management(struct si_context *sctx, unsigned allo SI_CPDMA_SKIP_BO_LIST_UPDATE | SI_CPDMA_SKIP_CHECK_CS_SPACE | SI_CPDMA_SKIP_GFX_SYNC, 0, 0); - ws->cs_add_buffer(cs[i], gds_bo[i], domain, RADEON_USAGE_READWRITE, 0); + ws->cs_add_buffer(cs[i], gds_bo[i], RADEON_USAGE_READWRITE, domain, 0); ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL); } } @@ -877,7 +881,7 @@ static void si_disk_cache_create(struct si_screen *sscreen) disk_cache_format_hex_id(cache_id, sha1, 20 * 2); /* These flags affect shader compilation. */ -#define ALL_FLAGS (DBG(GISEL)) +#define ALL_FLAGS (DBG(GISEL) | DBG(KILL_PS_INF_INTERP)) uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS; /* Add the high bits of 32-bit addresses, which affects @@ -922,6 +926,12 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->ws = ws; ws->query_info(ws, &sscreen->info); + if (sscreen->info.chip_class == GFX10_3 && LLVM_VERSION_MAJOR < 11) { + fprintf(stderr, "radeonsi: GFX 10.3 requires LLVM 11 or higher\n"); + FREE(sscreen); + return NULL; + } + if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) { fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n"); FREE(sscreen); @@ -994,6 +1004,10 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, #include "si_debug_options.h" } + if (sscreen->options.no_infinite_interp) { + sscreen->debug_flags |= DBG(KILL_PS_INF_INTERP); + } + si_disk_cache_create(sscreen); /* Determine the number of shader compiler threads. */ @@ -1081,7 +1095,11 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se; sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4; - if (sscreen->info.chip_class >= GFX7) { + if (sscreen->info.chip_class >= GFX10_3) { + sscreen->vgt_hs_offchip_param = + S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) | + S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity); + } else if (sscreen->info.chip_class >= GFX7) { if (sscreen->info.chip_class >= GFX8) --max_offchip_buffers; sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) | @@ -1118,7 +1136,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, /* Only enable primitive binning on APUs by default. */ if (sscreen->info.chip_class >= GFX10) { sscreen->dpbb_allowed = true; - sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram; + /* DFSM is not supported on GFX 10.3 and not beneficial on Navi1x. */ } else if (sscreen->info.chip_class == GFX9) { sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram; sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;