X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_pipe.c;h=a290d16b02d3aaffdb11dce1c0c70dc9ff561307;hb=7bb9bb0540cf5ce59040f278e0fc3dc68d6fceeb;hp=e9cf1c32724bfb05c1b3e14b7b3f89307bed8ce5;hpb=726a48c94f49010d9b4d48bfc5efeabae77825b2;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index e9cf1c32724..a290d16b02d 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -26,6 +26,7 @@ #include "si_pipe.h" #include "si_public.h" #include "si_shader_internal.h" +#include "si_compute.h" #include "sid.h" #include "ac_llvm_util.h" @@ -41,6 +42,10 @@ #include "vl/vl_decoder.h" #include "driver_ddebug/dd_util.h" +#include "gallium/winsys/radeon/drm/radeon_drm_public.h" +#include "gallium/winsys/amdgpu/drm/amdgpu_public.h" +#include + static const struct debug_named_value debug_options[] = { /* Shader logging options: */ { "vs", DBG(VS), "Print vertex shaders" }, @@ -61,7 +66,6 @@ static const struct debug_named_value debug_options[] = { /* Shader compiler options (with no effect on the shader cache): */ { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" }, - { "nir", DBG(NIR), "Enable experimental NIR shaders" }, { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" }, { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." }, @@ -80,6 +84,9 @@ static const struct debug_named_value debug_options[] = { { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." }, /* 3D engine options: */ + { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." }, + { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." }, + { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." }, { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." }, { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" }, { "nodpbb", DBG(NO_DPBB), "Disable DPBB." }, @@ -101,7 +108,10 @@ static const struct debug_named_value debug_options[] = { { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." }, { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." }, { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." }, - { "testclearbufperf", DBG(TEST_CLEARBUF_PERF), "Test Clearbuffer Performance" }, + { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" }, + { "testgds", DBG(TEST_GDS), "Test GDS." }, + { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." }, + { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." }, DEBUG_NAMED_VALUE_END /* must be last */ }; @@ -112,7 +122,7 @@ static void si_init_compiler(struct si_screen *sscreen, /* Only create the less-optimizing version of the compiler on APUs * predating Ryzen (Raven). */ bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram && - sscreen->info.chip_class <= VI; + sscreen->info.chip_class <= GFX8; enum ac_target_machine_options tm_options = (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) | @@ -124,7 +134,7 @@ static void si_init_compiler(struct si_screen *sscreen, (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0); ac_init_llvm_once(); - ac_init_llvm_compiler(compiler, true, sscreen->info.family, tm_options); + ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options); compiler->passes = ac_create_llvm_passes(compiler->tm); if (compiler->low_opt_tm) @@ -146,6 +156,9 @@ static void si_destroy_context(struct pipe_context *context) struct si_context *sctx = (struct si_context *)context; int i; + util_queue_finish(&sctx->screen->shader_compiler_queue); + util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority); + /* Unreference the framebuffer normally to disable related logic * properly. */ @@ -159,11 +172,12 @@ static void si_destroy_context(struct pipe_context *context) pipe_resource_reference(&sctx->gsvs_ring, NULL); pipe_resource_reference(&sctx->tess_rings, NULL); pipe_resource_reference(&sctx->null_const_buf.buffer, NULL); - r600_resource_reference(&sctx->border_color_buffer, NULL); + pipe_resource_reference(&sctx->sample_pos_buffer, NULL); + si_resource_reference(&sctx->border_color_buffer, NULL); free(sctx->border_color_table); - r600_resource_reference(&sctx->scratch_buffer, NULL); - r600_resource_reference(&sctx->compute_scratch_buffer, NULL); - r600_resource_reference(&sctx->wait_mem_scratch, NULL); + si_resource_reference(&sctx->scratch_buffer, NULL); + si_resource_reference(&sctx->compute_scratch_buffer, NULL); + si_resource_reference(&sctx->wait_mem_scratch, NULL); si_pm4_free_state(sctx, sctx->init_config, ~0); if (sctx->init_config_gs_rings) @@ -193,6 +207,20 @@ static void si_destroy_context(struct pipe_context *context) sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered); if (sctx->vs_blit_texcoord) sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord); + if (sctx->cs_clear_buffer) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer); + if (sctx->cs_copy_buffer) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer); + if (sctx->cs_copy_image) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image); + if (sctx->cs_copy_image_1d_array) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array); + if (sctx->cs_clear_render_target) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target); + if (sctx->cs_clear_render_target_1d_array) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array); + if (sctx->cs_dcc_retile) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile); if (sctx->blitter) util_blitter_destroy(sctx->blitter); @@ -234,7 +262,13 @@ static void si_destroy_context(struct pipe_context *context) sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL); sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL); - r600_resource_reference(&sctx->eop_bug_scratch, NULL); + sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL); + si_resource_reference(&sctx->eop_bug_scratch, NULL); + si_resource_reference(&sctx->index_ring, NULL); + si_resource_reference(&sctx->barrier_buf, NULL); + si_resource_reference(&sctx->last_ib_barrier_buf, NULL); + pb_reference(&sctx->gds, NULL); + pb_reference(&sctx->gds_oa, NULL); si_destroy_compiler(&sctx->compiler); @@ -248,6 +282,7 @@ static void si_destroy_context(struct pipe_context *context) util_dynarray_fini(&sctx->resident_tex_needs_color_decompress); util_dynarray_fini(&sctx->resident_img_needs_color_decompress); util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress); + si_unref_sdma_uploads(sctx); FREE(sctx); } @@ -255,21 +290,7 @@ static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx) { struct si_context *sctx = (struct si_context *)ctx; - if (sctx->screen->info.has_gpu_reset_status_query) - return sctx->ws->ctx_query_reset_status(sctx->ctx); - - if (sctx->screen->info.has_gpu_reset_counter_query) { - unsigned latest = sctx->ws->query_value(sctx->ws, - RADEON_GPU_RESET_COUNTER); - - if (sctx->gpu_reset_counter == latest) - return PIPE_NO_RESET; - - sctx->gpu_reset_counter = latest; - return PIPE_UNKNOWN_CONTEXT_RESET; - } - - return PIPE_NO_RESET; + return sctx->ws->ctx_query_reset_status(sctx->ctx); } static void si_set_device_reset_callback(struct pipe_context *ctx, @@ -291,10 +312,7 @@ bool si_check_device_reset(struct si_context *sctx) if (!sctx->device_reset_callback.reset) return false; - if (!sctx->b.get_device_reset_status) - return false; - - status = sctx->b.get_device_reset_status(&sctx->b); + status = sctx->ws->ctx_query_reset_status(sctx->ctx); if (status == PIPE_NO_RESET) return false; @@ -346,6 +364,20 @@ static void si_set_log_context(struct pipe_context *ctx, u_log_add_auto_logger(log, si_auto_log_cs, sctx); } +static void si_set_context_param(struct pipe_context *ctx, + enum pipe_context_param param, + unsigned value) +{ + struct radeon_winsys *ws = ((struct si_context *)ctx)->ws; + + switch (param) { + case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE: + ws->pin_threads_to_L3_cache(ws, value); + break; + default:; + } +} + static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags) { @@ -353,19 +385,20 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, struct si_screen* sscreen = (struct si_screen *)screen; struct radeon_winsys *ws = sscreen->ws; int shader, i; + bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0; if (!sctx) return NULL; + sctx->has_graphics = sscreen->info.chip_class == GFX6 || + !(flags & PIPE_CONTEXT_COMPUTE_ONLY); + if (flags & PIPE_CONTEXT_DEBUG) sscreen->record_llvm_ir = true; /* racy but not critical */ sctx->b.screen = screen; /* this must be set first */ sctx->b.priv = NULL; sctx->b.destroy = si_destroy_context; - sctx->b.emit_string_marker = si_emit_string_marker; - sctx->b.set_debug_callback = si_set_debug_callback; - sctx->b.set_log_context = si_set_log_context; sctx->screen = sscreen; /* Easy accessing of screen/winsys. */ sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0; @@ -376,30 +409,22 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, sctx->family = sscreen->info.family; sctx->chip_class = sscreen->info.chip_class; - if (sscreen->info.has_gpu_reset_counter_query) { - sctx->gpu_reset_counter = - sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER); - } - - sctx->b.get_device_reset_status = si_get_reset_status; - sctx->b.set_device_reset_callback = si_set_device_reset_callback; - - si_init_context_texture_functions(sctx); - si_init_query_functions(sctx); - - if (sctx->chip_class == CIK || - sctx->chip_class == VI || + if (sctx->chip_class == GFX7 || + sctx->chip_class == GFX8 || sctx->chip_class == GFX9) { - sctx->eop_bug_scratch = r600_resource( + sctx->eop_bug_scratch = si_resource( pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 16 * sscreen->info.num_render_backends)); if (!sctx->eop_bug_scratch) goto fail; } + /* Initialize context allocators. */ sctx->allocator_zeroed_memory = - u_suballocator_create(&sctx->b, sscreen->info.gart_page_size, - 0, PIPE_USAGE_DEFAULT, 0, true); + u_suballocator_create(&sctx->b, 128 * 1024, + 0, PIPE_USAGE_DEFAULT, + SI_RESOURCE_FLAG_UNMAPPABLE | + SI_RESOURCE_FLAG_CLEAR, false); if (!sctx->allocator_zeroed_memory) goto fail; @@ -409,14 +434,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (!sctx->b.stream_uploader) goto fail; - sctx->b.const_uploader = u_upload_create(&sctx->b, 128 * 1024, - 0, PIPE_USAGE_DEFAULT, - SI_RESOURCE_FLAG_32BIT | - (sscreen->cpdma_prefetch_writes_memory ? - 0 : SI_RESOURCE_FLAG_READ_ONLY)); - if (!sctx->b.const_uploader) - goto fail; - sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024, 0, PIPE_USAGE_STAGING, 0); if (!sctx->cached_gtt_allocator) @@ -428,29 +445,27 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) { sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA, - (void*)si_flush_dma_cs, - sctx); + (void*)si_flush_dma_cs, + sctx, stop_exec_on_failure); } - si_init_buffer_functions(sctx); - si_init_clear_functions(sctx); - si_init_blit_functions(sctx); - si_init_compute_functions(sctx); - si_init_cp_dma_functions(sctx); - si_init_debug_functions(sctx); - si_init_msaa_functions(sctx); - si_init_streamout_functions(sctx); + bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs; + sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024, + 0, PIPE_USAGE_DEFAULT, + SI_RESOURCE_FLAG_32BIT | + (use_sdma_upload ? + SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : + (sscreen->cpdma_prefetch_writes_memory ? + 0 : SI_RESOURCE_FLAG_READ_ONLY))); + if (!sctx->b.const_uploader) + goto fail; - if (sscreen->info.has_hw_decode) { - sctx->b.create_video_codec = si_uvd_create_decoder; - sctx->b.create_video_buffer = si_video_buffer_create; - } else { - sctx->b.create_video_codec = vl_create_decoder; - sctx->b.create_video_buffer = vl_video_buffer_create; - } + if (use_sdma_upload) + u_upload_enable_flush_explicit(sctx->b.const_uploader); - sctx->gfx_cs = ws->cs_create(sctx->ctx, RING_GFX, - (void*)si_flush_gfx_cs, sctx); + sctx->gfx_cs = ws->cs_create(sctx->ctx, + sctx->has_graphics ? RING_GFX : RING_COMPUTE, + (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure); /* Border colors. */ sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * @@ -458,7 +473,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (!sctx->border_color_table) goto fail; - sctx->border_color_buffer = r600_resource( + sctx->border_color_buffer = si_resource( pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table))); @@ -471,14 +486,50 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (!sctx->border_color_map) goto fail; + /* Initialize context functions used by graphics and compute. */ + if (sctx->chip_class >= GFX10) + sctx->emit_cache_flush = gfx10_emit_cache_flush; + else + sctx->emit_cache_flush = si_emit_cache_flush; + + sctx->b.emit_string_marker = si_emit_string_marker; + sctx->b.set_debug_callback = si_set_debug_callback; + sctx->b.set_log_context = si_set_log_context; + sctx->b.set_context_param = si_set_context_param; + sctx->b.get_device_reset_status = si_get_reset_status; + sctx->b.set_device_reset_callback = si_set_device_reset_callback; + si_init_all_descriptors(sctx); + si_init_buffer_functions(sctx); + si_init_clear_functions(sctx); + si_init_blit_functions(sctx); + si_init_compute_functions(sctx); + si_init_compute_blit_functions(sctx); + si_init_debug_functions(sctx); si_init_fence_functions(sctx); - si_init_state_functions(sctx); - si_init_shader_functions(sctx); - si_init_viewport_functions(sctx); - si_init_ia_multi_vgt_param_table(sctx); + si_init_query_functions(sctx); + si_init_state_compute_functions(sctx); + + /* Initialize graphics-only context functions. */ + if (sctx->has_graphics) { + si_init_context_texture_functions(sctx); + si_init_msaa_functions(sctx); + si_init_shader_functions(sctx); + si_init_state_functions(sctx); + si_init_streamout_functions(sctx); + si_init_viewport_functions(sctx); + + sctx->blitter = util_blitter_create(&sctx->b); + if (sctx->blitter == NULL) + goto fail; + sctx->blitter->skip_viewport_restore = true; - if (sctx->chip_class >= CIK) + si_init_draw_functions(sctx); + si_initialize_prim_discard_tunables(sctx); + } + + /* Initialize SDMA functions. */ + if (sctx->chip_class >= GFX7) cik_init_sdma_functions(sctx); else si_init_dma_functions(sctx); @@ -486,36 +537,31 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (sscreen->debug_flags & DBG(FORCE_DMA)) sctx->b.resource_copy_region = sctx->dma_copy; - sctx->blitter = util_blitter_create(&sctx->b); - if (sctx->blitter == NULL) - goto fail; - sctx->blitter->draw_rectangle = si_draw_rectangle; - sctx->blitter->skip_viewport_restore = true; - sctx->sample_mask = 0xffff; + /* Initialize multimedia functions. */ + if (sscreen->info.has_hw_decode) { + sctx->b.create_video_codec = si_uvd_create_decoder; + sctx->b.create_video_buffer = si_video_buffer_create; + } else { + sctx->b.create_video_codec = vl_create_decoder; + sctx->b.create_video_buffer = vl_video_buffer_create; + } + if (sctx->chip_class >= GFX9) { - sctx->wait_mem_scratch = r600_resource( - pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4)); + sctx->wait_mem_scratch = si_resource( + pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8)); if (!sctx->wait_mem_scratch) goto fail; /* Initialize the memory. */ - struct radeon_cmdbuf *cs = sctx->gfx_cs; - radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); - radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) | - S_370_WR_CONFIRM(1) | - S_370_ENGINE_SEL(V_370_ME)); - radeon_emit(cs, sctx->wait_mem_scratch->gpu_address); - radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32); - radeon_emit(cs, sctx->wait_mem_number); - radeon_add_to_buffer_list(sctx, cs, sctx->wait_mem_scratch, - RADEON_USAGE_WRITE, RADEON_PRIO_FENCE); + si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, + V_370_MEM, V_370_ME, &sctx->wait_mem_number); } - /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads + /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */ - if (sctx->chip_class == CIK) { + if (sctx->chip_class == GFX7) { sctx->null_const_buf.buffer = pipe_aligned_buffer_create(screen, SI_RESOURCE_FLAG_32BIT, @@ -525,7 +571,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, goto fail; sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0; - for (shader = 0; shader < SI_NUM_SHADERS; shader++) { + unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE; + for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) { for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) { sctx->b.set_constant_buffer(&sctx->b, shader, i, &sctx->null_const_buf); @@ -542,11 +589,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, &sctx->null_const_buf); si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &sctx->null_const_buf); - - /* Clear the NULL constant buffer, because loads should return zeros. */ - si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, - sctx->null_const_buf.buffer->width0, 0, - SI_COHERENCY_SHADER, SI_METHOD_BEST); } uint64_t max_threads_per_block; @@ -583,8 +625,25 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL); util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL); + sctx->sample_pos_buffer = + pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT, + sizeof(sctx->sample_positions)); + pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0, + sizeof(sctx->sample_positions), &sctx->sample_positions); + /* this must be last */ si_begin_new_gfx_cs(sctx); + + if (sctx->chip_class == GFX7) { + /* Clear the NULL constant buffer, because loads should return zeros. + * Note that this forces CP DMA to be used, because clover deadlocks + * for some reason when the compute codepath is used. + */ + uint32_t clear_value = 0; + si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, + sctx->null_const_buf.buffer->width0, + &clear_value, 4, SI_COHERENCY_SHADER, true); + } return &sctx->b; fail: fprintf(stderr, "radeonsi: Failed to create a context.\n"); @@ -619,7 +678,7 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, * implementation for fence_server_sync is incomplete. */ return threaded_context_create(ctx, &sscreen->pool_transfers, si_replace_buffer_storage, - sscreen->info.drm_major >= 3 ? si_create_fence : NULL, + sscreen->info.is_amdgpu ? si_create_fence : NULL, &((struct si_context*)ctx)->tc); } @@ -641,6 +700,17 @@ static void si_destroy_screen(struct pipe_screen* pscreen) if (!sscreen->ws->unref(sscreen->ws)) return; + mtx_destroy(&sscreen->aux_context_lock); + + struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log; + if (aux_log) { + sscreen->aux_context->set_log_context(sscreen->aux_context, NULL); + u_log_context_destroy(aux_log); + FREE(aux_log); + } + + sscreen->aux_context->destroy(sscreen->aux_context); + util_queue_destroy(&sscreen->shader_compiler_queue); util_queue_destroy(&sscreen->shader_compiler_queue_low_priority); @@ -656,19 +726,17 @@ static void si_destroy_screen(struct pipe_screen* pscreen) struct si_shader_part *part = parts[i]; parts[i] = part->next; - ac_shader_binary_clean(&part->binary); + si_shader_binary_clean(&part->binary); FREE(part); } } mtx_destroy(&sscreen->shader_parts_mutex); si_destroy_shader_cache(sscreen); - si_perfcounters_destroy(sscreen); + si_destroy_perfcounters(sscreen); si_gpu_load_kill_thread(sscreen); mtx_destroy(&sscreen->gpu_load_mutex); - mtx_destroy(&sscreen->aux_context_lock); - sscreen->aux_context->destroy(sscreen->aux_context); slab_destroy_parent(&sscreen->pool_transfers); @@ -683,38 +751,6 @@ static void si_init_gs_info(struct si_screen *sscreen) sscreen->info.family); } -static void si_handle_env_var_force_family(struct si_screen *sscreen) -{ - const char *family = debug_get_option("SI_FORCE_FAMILY", NULL); - unsigned i; - - if (!family) - return; - - for (i = CHIP_TAHITI; i < CHIP_LAST; i++) { - if (!strcmp(family, ac_get_llvm_processor_name(i))) { - /* Override family and chip_class. */ - sscreen->info.family = i; - - if (i >= CHIP_VEGA10) - sscreen->info.chip_class = GFX9; - else if (i >= CHIP_TONGA) - sscreen->info.chip_class = VI; - else if (i >= CHIP_BONAIRE) - sscreen->info.chip_class = CIK; - else - sscreen->info.chip_class = SI; - - /* Don't submit any IBs. */ - setenv("RADEON_NOOP", "1", 1); - return; - } - } - - fprintf(stderr, "radeonsi: Unknown family: %s\n", family); - exit(1); -} - static void si_test_vmfault(struct si_screen *sscreen) { struct pipe_context *ctx = sscreen->aux_context; @@ -727,15 +763,16 @@ static void si_test_vmfault(struct si_screen *sscreen) exit(1); } - r600_resource(buf)->gpu_address = 0; /* cause a VM fault */ + si_resource(buf)->gpu_address = 0; /* cause a VM fault */ if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) { - si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0); + si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0, + SI_COHERENCY_NONE, L2_BYPASS); ctx->flush(ctx, NULL, 0); puts("VM fault test: CP - done."); } if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) { - sctx->dma_clear_buffer(sctx, buf, 0, 4, 0); + si_sdma_clear_buffer(sctx, buf, 0, 4, 0); ctx->flush(ctx, NULL, 0); puts("VM fault test: SDMA - done."); } @@ -746,52 +783,114 @@ static void si_test_vmfault(struct si_screen *sscreen) exit(0); } +static void si_test_gds_memory_management(struct si_context *sctx, + unsigned alloc_size, unsigned alignment, + enum radeon_bo_domain domain) +{ + struct radeon_winsys *ws = sctx->ws; + struct radeon_cmdbuf *cs[8]; + struct pb_buffer *gds_bo[ARRAY_SIZE(cs)]; + + for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) { + cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE, + NULL, NULL, false); + gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0); + assert(gds_bo[i]); + } + + for (unsigned iterations = 0; iterations < 20000; iterations++) { + for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) { + /* This clears GDS with CP DMA. + * + * We don't care if GDS is present. Just add some packet + * to make the GPU busy for a moment. + */ + si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0, + SI_CPDMA_SKIP_BO_LIST_UPDATE | + SI_CPDMA_SKIP_CHECK_CS_SPACE | + SI_CPDMA_SKIP_GFX_SYNC, 0, 0); + + ws->cs_add_buffer(cs[i], gds_bo[i], domain, + RADEON_USAGE_READWRITE, 0); + ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL); + } + } + exit(0); +} + static void si_disk_cache_create(struct si_screen *sscreen) { /* Don't use the cache if shader dumping is enabled. */ if (sscreen->debug_flags & DBG_ALL_SHADERS) return; - uint32_t mesa_timestamp; - if (disk_cache_get_function_timestamp(si_disk_cache_create, - &mesa_timestamp)) { - char *timestamp_str; - int res = -1; - uint32_t llvm_timestamp; - - if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, - &llvm_timestamp)) { - res = asprintf(×tamp_str, "%u_%u", - mesa_timestamp, llvm_timestamp); - } + struct mesa_sha1 ctx; + unsigned char sha1[20]; + char cache_id[20 * 2 + 1]; - if (res != -1) { - /* These flags affect shader compilation. */ - #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \ - DBG(SI_SCHED) | \ - DBG(GISEL) | \ - DBG(UNSAFE_MATH) | \ - DBG(NIR)) - uint64_t shader_debug_flags = sscreen->debug_flags & - ALL_FLAGS; - - /* Add the high bits of 32-bit addresses, which affects - * how 32-bit addresses are expanded to 64 bits. - */ - STATIC_ASSERT(ALL_FLAGS <= UINT_MAX); - shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32; - - sscreen->disk_shader_cache = - disk_cache_create(si_get_family_name(sscreen), - timestamp_str, - shader_debug_flags); - free(timestamp_str); - } + _mesa_sha1_init(&ctx); + + if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) || + !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, + &ctx)) + return; + + _mesa_sha1_final(&ctx, sha1); + disk_cache_format_hex_id(cache_id, sha1, 20 * 2); + + /* These flags affect shader compilation. */ + #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \ + DBG(SI_SCHED) | \ + DBG(GISEL) | \ + DBG(UNSAFE_MATH)) + uint64_t shader_debug_flags = sscreen->debug_flags & + ALL_FLAGS; + + /* Add the high bits of 32-bit addresses, which affects + * how 32-bit addresses are expanded to 64 bits. + */ + STATIC_ASSERT(ALL_FLAGS <= UINT_MAX); + assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi); + shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32; + + if (sscreen->options.enable_nir) + shader_debug_flags |= 1ull << 48; + + sscreen->disk_shader_cache = + disk_cache_create(sscreen->info.name, + cache_id, + shader_debug_flags); +} + +static void si_set_max_shader_compiler_threads(struct pipe_screen *screen, + unsigned max_threads) +{ + struct si_screen *sscreen = (struct si_screen *)screen; + + /* This function doesn't allow a greater number of threads than + * the queue had at its creation. */ + util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, + max_threads); + /* Don't change the number of threads on the low priority queue. */ +} + +static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen, + void *shader, + unsigned shader_type) +{ + if (shader_type == PIPE_SHADER_COMPUTE) { + struct si_compute *cs = (struct si_compute*)shader; + + return util_queue_fence_is_signalled(&cs->ready); } + struct si_shader_selector *sel = (struct si_shader_selector *)shader; + + return util_queue_fence_is_signalled(&sel->ready); } -struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, - const struct pipe_screen_config *config) +static struct pipe_screen * +radeonsi_screen_create_impl(struct radeon_winsys *ws, + const struct pipe_screen_config *config) { struct si_screen *sscreen = CALLOC_STRUCT(si_screen); unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i; @@ -802,14 +901,34 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->ws = ws; ws->query_info(ws, &sscreen->info); - si_handle_env_var_force_family(sscreen); + + if (sscreen->info.chip_class == GFX10 && HAVE_LLVM < 0x0900) { + fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n"); + FREE(sscreen); + return NULL; + } + + if (sscreen->info.chip_class >= GFX9) { + sscreen->se_tile_repeat = 32 * sscreen->info.max_se; + } else { + ac_get_raster_config(&sscreen->info, + &sscreen->pa_sc_raster_config, + &sscreen->pa_sc_raster_config_1, + &sscreen->se_tile_repeat); + } sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", - debug_options, 0); + debug_options, 0); + sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", + debug_options, 0); /* Set functions first. */ sscreen->b.context_create = si_pipe_create_context; sscreen->b.destroy = si_destroy_screen; + sscreen->b.set_max_shader_compiler_threads = + si_set_max_shader_compiler_threads; + sscreen->b.is_parallel_shader_compilation_finished = + si_is_parallel_shader_compilation_finished; si_init_screen_get_functions(sscreen); si_init_screen_buffer_functions(sscreen); @@ -827,7 +946,6 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, if (driQueryOptionb(config->options, "radeonsi_enable_sisched")) sscreen->debug_flags |= DBG(SI_SCHED); - if (sscreen->debug_flags & DBG(INFO)) ac_print_gpu_info(&sscreen->info); @@ -835,6 +953,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sizeof(struct si_transfer), 64); sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1)); + if (sscreen->force_aniso == -1) { + sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1)); + } + if (sscreen->force_aniso >= 0) { printf("radeonsi: Forcing anisotropy filter to %ix\n", /* round down to a power of two */ @@ -876,7 +998,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, if (!util_queue_init(&sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads, - UTIL_QUEUE_INIT_RESIZE_IF_FULL)) { + UTIL_QUEUE_INIT_RESIZE_IF_FULL | + UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) { si_destroy_shader_cache(sscreen); FREE(sscreen); return NULL; @@ -886,6 +1009,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, "shlo", 64, num_comp_lo_threads, UTIL_QUEUE_INIT_RESIZE_IF_FULL | + UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY | UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) { si_destroy_shader_cache(sscreen); FREE(sscreen); @@ -896,11 +1020,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, si_init_perfcounters(sscreen); /* Determine tessellation ring info. */ - bool double_offchip_buffers = sscreen->info.chip_class >= CIK && + bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 && sscreen->info.family != CHIP_CARRIZO && sscreen->info.family != CHIP_STONEY; /* This must be one less than the maximum number due to a hw limitation. - * Various hardware bugs in SI, CIK, and GFX9 need this. + * Various hardware bugs need this. */ unsigned max_offchip_buffers_per_se; @@ -931,8 +1055,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4; - if (sscreen->info.chip_class >= CIK) { - if (sscreen->info.chip_class >= VI) + if (sscreen->info.chip_class >= GFX7) { + if (sscreen->info.chip_class >= GFX8) --max_offchip_buffers; sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) | @@ -944,62 +1068,79 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs - * on SI. */ - sscreen->has_clear_state = sscreen->info.chip_class >= CIK; + * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. + * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/ + sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 && + sscreen->info.is_amdgpu; sscreen->has_distributed_tess = - sscreen->info.chip_class >= VI && + sscreen->info.chip_class >= GFX8 && sscreen->info.max_se >= 2; sscreen->has_draw_indirect_multi = (sscreen->info.family >= CHIP_POLARIS10) || - (sscreen->info.chip_class == VI && + (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 && sscreen->info.me_fw_version >= 87) || - (sscreen->info.chip_class == CIK && + (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 && sscreen->info.me_fw_version >= 173) || - (sscreen->info.chip_class == SI && + (sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 && sscreen->info.me_fw_version >= 142); - sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI && + sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 && sscreen->info.max_se >= 2 && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER)); sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights"); sscreen->commutative_blend_add = driQueryOptionb(config->options, "radeonsi_commutative_blend_add"); - sscreen->clear_db_cache_before_clear = - driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear"); + + { +#define OPT_BOOL(name, dflt, description) \ + sscreen->options.name = \ + driQueryOptionb(config->options, "radeonsi_"#name); +#include "si_debug_options.h" + } + + sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 || + sscreen->info.family == CHIP_RAVEN; sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 && sscreen->info.family <= CHIP_POLARIS12) || sscreen->info.family == CHIP_VEGA10 || sscreen->info.family == CHIP_RAVEN; sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 || sscreen->info.family == CHIP_RAVEN; + sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2; + /* Only enable primitive binning on APUs by default. */ + sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN || + sscreen->info.family == CHIP_RAVEN2; + + sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN || + sscreen->info.family == CHIP_RAVEN2; + + /* Process DPBB enable flags. */ if (sscreen->debug_flags & DBG(DPBB)) { sscreen->dpbb_allowed = true; - } else { - /* Only enable primitive binning on Raven by default. */ - /* TODO: Investigate if binning is profitable on Vega12. */ - sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN && - !(sscreen->debug_flags & DBG(NO_DPBB)); + if (sscreen->debug_flags & DBG(DFSM)) + sscreen->dfsm_allowed = true; } - if (sscreen->debug_flags & DBG(DFSM)) { - sscreen->dfsm_allowed = sscreen->dpbb_allowed; - } else { - sscreen->dfsm_allowed = sscreen->dpbb_allowed && - !(sscreen->debug_flags & DBG(NO_DFSM)); + /* Process DPBB disable flags. */ + if (sscreen->debug_flags & DBG(NO_DPBB)) { + sscreen->dpbb_allowed = false; + sscreen->dfsm_allowed = false; + } else if (sscreen->debug_flags & DBG(NO_DFSM)) { + sscreen->dfsm_allowed = false; } /* While it would be nice not to have this flag, we are constrained * by the reality that LLVM 5.0 doesn't have working VGPR indexing * on GFX9. */ - sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI; + sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= GFX8; /* Some chips have RB+ registers, but don't support RB+. Those must * always disable it. @@ -1012,23 +1153,24 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, !(sscreen->debug_flags & DBG(NO_RB_PLUS)) && (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA12 || - sscreen->info.family == CHIP_RAVEN); + sscreen->info.family == CHIP_RAVEN || + sscreen->info.family == CHIP_RAVEN2); } sscreen->dcc_msaa_allowed = !(sscreen->debug_flags & DBG(NO_DCC_MSAA)); - sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI; + sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8; (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain); sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0; - sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 | - SI_CONTEXT_INV_VMEM_L1; - if (sscreen->info.chip_class <= VI) { - sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2; - sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | + SI_CONTEXT_INV_VCACHE; + if (sscreen->info.chip_class <= GFX8) { + sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2; + sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2; } if (debug_get_bool_option("RADEON_DUMP_SHADERS", false)) @@ -1065,13 +1207,19 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, si_init_compiler(sscreen, &sscreen->compiler_lowp[i]); /* Create the auxiliary context. This must be done last. */ - sscreen->aux_context = si_create_context(&sscreen->b, 0); + sscreen->aux_context = si_create_context( + &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0); + if (sscreen->options.aux_debug) { + struct u_log_context *log = CALLOC_STRUCT(u_log_context); + u_log_context_init(log); + sscreen->aux_context->set_log_context(sscreen->aux_context, log); + } if (sscreen->debug_flags & DBG(TEST_DMA)) si_test_dma(sscreen); - if (sscreen->debug_flags & DBG(TEST_CLEARBUF_PERF)) { - si_test_clearbuffer(sscreen); + if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) { + si_test_dma_perf(sscreen); } if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) | @@ -1079,5 +1227,35 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, DBG(TEST_VMFAULT_SHADER))) si_test_vmfault(sscreen); + if (sscreen->debug_flags & DBG(TEST_GDS)) + si_test_gds((struct si_context*)sscreen->aux_context); + + if (sscreen->debug_flags & DBG(TEST_GDS_MM)) { + si_test_gds_memory_management((struct si_context*)sscreen->aux_context, + 32 * 1024, 4, RADEON_DOMAIN_GDS); + } + if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) { + si_test_gds_memory_management((struct si_context*)sscreen->aux_context, + 4, 1, RADEON_DOMAIN_OA); + } + return &sscreen->b; } + +struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config) +{ + drmVersionPtr version = drmGetVersion(fd); + struct radeon_winsys *rw = NULL; + + switch (version->version_major) { + case 2: + rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl); + break; + case 3: + rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl); + break; + } + + drmFreeVersion(version); + return rw ? rw->screen : NULL; +}