X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_pipe.c;h=aa627279ed3ca33cc21da9bb141c8f3a5b743fda;hb=4675cb2019cdab3f4980e3f98ce243f668092425;hp=9b1eab8284b2bbf72602abd240a19b0578e0bf6b;hpb=a1378639ab19682a818ee627745db7f67485d406;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 9b1eab8284b..aa627279ed3 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -26,11 +26,11 @@ #include "si_pipe.h" #include "si_public.h" #include "si_shader_internal.h" +#include "si_compute.h" #include "sid.h" #include "ac_llvm_util.h" #include "radeon/radeon_uvd.h" -#include "gallivm/lp_bld_misc.h" #include "util/disk_cache.h" #include "util/u_log.h" #include "util/u_memory.h" @@ -41,6 +41,15 @@ #include "vl/vl_decoder.h" #include "driver_ddebug/dd_util.h" +#include "gallium/winsys/radeon/drm/radeon_drm_public.h" +#include "gallium/winsys/amdgpu/drm/amdgpu_public.h" +#include + +#include + +static struct pipe_context *si_create_context(struct pipe_screen *screen, + unsigned flags); + static const struct debug_named_value debug_options[] = { /* Shader logging options: */ { "vs", DBG(VS), "Print vertex shaders" }, @@ -55,13 +64,17 @@ static const struct debug_named_value debug_options[] = { { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" }, /* Shader compiler options the shader cache should be aware of: */ - { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" }, { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." }, { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." }, + { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." }, + { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." }, + { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." }, + { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." }, + { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." }, + { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." }, /* Shader compiler options (with no effect on the shader cache): */ { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" }, - { "nir", DBG(NIR), "Enable experimental NIR shaders" }, { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" }, { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." }, @@ -80,6 +93,11 @@ static const struct debug_named_value debug_options[] = { { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." }, /* 3D engine options: */ + { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." }, + { "nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline." }, + { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." }, + { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." }, + { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." }, { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." }, { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" }, { "nodpbb", DBG(NO_DPBB), "Disable DPBB." }, @@ -109,13 +127,12 @@ static const struct debug_named_value debug_options[] = { DEBUG_NAMED_VALUE_END /* must be last */ }; -static void si_init_compiler(struct si_screen *sscreen, - struct ac_llvm_compiler *compiler) +void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler) { /* Only create the less-optimizing version of the compiler on APUs * predating Ryzen (Raven). */ bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram && - sscreen->info.chip_class <= VI; + sscreen->info.chip_class <= GFX8; enum ac_target_machine_options tm_options = (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) | @@ -130,14 +147,14 @@ static void si_init_compiler(struct si_screen *sscreen, ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options); compiler->passes = ac_create_llvm_passes(compiler->tm); + if (compiler->tm_wave32) + compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32); if (compiler->low_opt_tm) compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm); } static void si_destroy_compiler(struct ac_llvm_compiler *compiler) { - ac_destroy_llvm_passes(compiler->passes); - ac_destroy_llvm_passes(compiler->low_opt_passes); ac_destroy_llvm_compiler(compiler); } @@ -149,6 +166,9 @@ static void si_destroy_context(struct pipe_context *context) struct si_context *sctx = (struct si_context *)context; int i; + util_queue_finish(&sctx->screen->shader_compiler_queue); + util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority); + /* Unreference the framebuffer normally to disable related logic * properly. */ @@ -158,6 +178,9 @@ static void si_destroy_context(struct pipe_context *context) si_release_all_descriptors(sctx); + if (sctx->chip_class >= GFX10 && sctx->has_graphics) + gfx10_destroy_query(sctx); + pipe_resource_reference(&sctx->esgs_ring, NULL); pipe_resource_reference(&sctx->gsvs_ring, NULL); pipe_resource_reference(&sctx->tess_rings, NULL); @@ -209,6 +232,17 @@ static void si_destroy_context(struct pipe_context *context) sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target); if (sctx->cs_clear_render_target_1d_array) sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array); + if (sctx->cs_dcc_retile) + sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile); + + for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) { + for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) { + if (sctx->cs_fmask_expand[i][j]) { + sctx->b.delete_compute_state(&sctx->b, + sctx->cs_fmask_expand[i][j]); + } + } + } if (sctx->blitter) util_blitter_destroy(sctx->blitter); @@ -227,6 +261,8 @@ static void si_destroy_context(struct pipe_context *context) if (sctx->query_result_shader) sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader); + if (sctx->sh_query_result_shader) + sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader); if (sctx->gfx_cs) sctx->ws->cs_destroy(sctx->gfx_cs); @@ -250,7 +286,13 @@ static void si_destroy_context(struct pipe_context *context) sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL); sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL); + sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL); si_resource_reference(&sctx->eop_bug_scratch, NULL); + si_resource_reference(&sctx->index_ring, NULL); + si_resource_reference(&sctx->barrier_buf, NULL); + si_resource_reference(&sctx->last_ib_barrier_buf, NULL); + pb_reference(&sctx->gds, NULL); + pb_reference(&sctx->gds_oa, NULL); si_destroy_compiler(&sctx->compiler); @@ -265,28 +307,39 @@ static void si_destroy_context(struct pipe_context *context) util_dynarray_fini(&sctx->resident_img_needs_color_decompress); util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress); si_unref_sdma_uploads(sctx); + free(sctx->sdma_uploads); FREE(sctx); } static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx) { struct si_context *sctx = (struct si_context *)ctx; + struct si_screen *sscreen = sctx->screen; + enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx); + + if (status != PIPE_NO_RESET) { + /* Call the state tracker to set a no-op API dispatch. */ + if (sctx->device_reset_callback.reset) { + sctx->device_reset_callback.reset(sctx->device_reset_callback.data, + status); + } - if (sctx->screen->info.has_gpu_reset_status_query) - return sctx->ws->ctx_query_reset_status(sctx->ctx); - - if (sctx->screen->info.has_gpu_reset_counter_query) { - unsigned latest = sctx->ws->query_value(sctx->ws, - RADEON_GPU_RESET_COUNTER); + /* Re-create the auxiliary context, because it won't submit + * any new IBs due to a GPU reset. + */ + simple_mtx_lock(&sscreen->aux_context_lock); - if (sctx->gpu_reset_counter == latest) - return PIPE_NO_RESET; + struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log; + sscreen->aux_context->set_log_context(sscreen->aux_context, NULL); + sscreen->aux_context->destroy(sscreen->aux_context); - sctx->gpu_reset_counter = latest; - return PIPE_UNKNOWN_CONTEXT_RESET; + sscreen->aux_context = si_create_context(&sscreen->b, + (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) | + (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY)); + sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log); + simple_mtx_unlock(&sscreen->aux_context_lock); } - - return PIPE_NO_RESET; + return status; } static void si_set_device_reset_callback(struct pipe_context *ctx, @@ -301,24 +354,6 @@ static void si_set_device_reset_callback(struct pipe_context *ctx, sizeof(sctx->device_reset_callback)); } -bool si_check_device_reset(struct si_context *sctx) -{ - enum pipe_reset_status status; - - if (!sctx->device_reset_callback.reset) - return false; - - if (!sctx->b.get_device_reset_status) - return false; - - status = sctx->b.get_device_reset_status(&sctx->b); - if (status == PIPE_NO_RESET) - return false; - - sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status); - return true; -} - /* Apitrace profiling: * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call @@ -380,8 +415,14 @@ static void si_set_context_param(struct pipe_context *ctx, static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags) { - struct si_context *sctx = CALLOC_STRUCT(si_context); struct si_screen* sscreen = (struct si_screen *)screen; + + /* Don't create a context if it's not compute-only and hw is compute-only. */ + if (!sscreen->info.has_graphics && + !(flags & PIPE_CONTEXT_COMPUTE_ONLY)) + return NULL; + + struct si_context *sctx = CALLOC_STRUCT(si_context); struct radeon_winsys *ws = sscreen->ws; int shader, i; bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0; @@ -389,7 +430,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (!sctx) return NULL; - sctx->has_graphics = sscreen->info.chip_class == SI || + sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY); if (flags & PIPE_CONTEXT_DEBUG) @@ -408,14 +449,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, sctx->family = sscreen->info.family; sctx->chip_class = sscreen->info.chip_class; - if (sscreen->info.has_gpu_reset_counter_query) { - sctx->gpu_reset_counter = - sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER); - } - - - if (sctx->chip_class == CIK || - sctx->chip_class == VI || + if (sctx->chip_class == GFX7 || + sctx->chip_class == GFX8 || sctx->chip_class == GFX9) { sctx->eop_bug_scratch = si_resource( pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT, @@ -448,7 +483,13 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (!sctx->ctx) goto fail; - if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) { + if (sscreen->info.num_rings[RING_DMA] && + !(sscreen->debug_flags & DBG(NO_ASYNC_DMA)) && + /* SDMA timeouts sometimes on gfx10 so disable it for now. See: + * https://bugs.freedesktop.org/show_bug.cgi?id=111481 + * https://gitlab.freedesktop.org/mesa/mesa/issues/1907 + */ + (sctx->chip_class != GFX10 || sscreen->debug_flags & DBG(FORCE_DMA))) { sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA, (void*)si_flush_dma_cs, sctx, stop_exec_on_failure); @@ -459,9 +500,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, 0, PIPE_USAGE_DEFAULT, SI_RESOURCE_FLAG_32BIT | (use_sdma_upload ? - SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : - (sscreen->cpdma_prefetch_writes_memory ? - 0 : SI_RESOURCE_FLAG_READ_ONLY))); + SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0)); if (!sctx->b.const_uploader) goto fail; @@ -491,14 +530,20 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (!sctx->border_color_map) goto fail; + sctx->ngg = sscreen->use_ngg; + /* Initialize context functions used by graphics and compute. */ + if (sctx->chip_class >= GFX10) + sctx->emit_cache_flush = gfx10_emit_cache_flush; + else + sctx->emit_cache_flush = si_emit_cache_flush; + sctx->b.emit_string_marker = si_emit_string_marker; sctx->b.set_debug_callback = si_set_debug_callback; sctx->b.set_log_context = si_set_log_context; sctx->b.set_context_param = si_set_context_param; sctx->b.get_device_reset_status = si_get_reset_status; sctx->b.set_device_reset_callback = si_set_device_reset_callback; - sctx->b.memory_barrier = si_memory_barrier; si_init_all_descriptors(sctx); si_init_buffer_functions(sctx); @@ -508,14 +553,14 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, si_init_compute_blit_functions(sctx); si_init_debug_functions(sctx); si_init_fence_functions(sctx); - - if (sscreen->debug_flags & DBG(FORCE_DMA)) - sctx->b.resource_copy_region = sctx->dma_copy; + si_init_query_functions(sctx); + si_init_state_compute_functions(sctx); + si_init_context_texture_functions(sctx); /* Initialize graphics-only context functions. */ if (sctx->has_graphics) { - si_init_context_texture_functions(sctx); - si_init_query_functions(sctx); + if (sctx->chip_class >= GFX10) + gfx10_init_query(sctx); si_init_msaa_functions(sctx); si_init_shader_functions(sctx); si_init_state_functions(sctx); @@ -527,15 +572,30 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, goto fail; sctx->blitter->skip_viewport_restore = true; + /* Some states are expected to be always non-NULL. */ + sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter); + sctx->queued.named.blend = sctx->noop_blend; + + sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter); + sctx->queued.named.dsa = sctx->noop_dsa; + + sctx->discard_rasterizer_state = + util_blitter_get_discard_rasterizer_state(sctx->blitter); + sctx->queued.named.rasterizer = sctx->discard_rasterizer_state; + si_init_draw_functions(sctx); + si_initialize_prim_discard_tunables(sctx); } /* Initialize SDMA functions. */ - if (sctx->chip_class >= CIK) + if (sctx->chip_class >= GFX7) cik_init_sdma_functions(sctx); else si_init_dma_functions(sctx); + if (sscreen->debug_flags & DBG(FORCE_DMA)) + sctx->b.resource_copy_region = sctx->dma_copy; + sctx->sample_mask = 0xffff; /* Initialize multimedia functions. */ @@ -549,7 +609,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, if (sctx->chip_class >= GFX9) { sctx->wait_mem_scratch = si_resource( - pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4)); + pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8)); if (!sctx->wait_mem_scratch) goto fail; @@ -558,9 +618,9 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, V_370_MEM, V_370_ME, &sctx->wait_mem_number); } - /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads + /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */ - if (sctx->chip_class == CIK) { + if (sctx->chip_class == GFX7) { sctx->null_const_buf.buffer = pipe_aligned_buffer_create(screen, SI_RESOURCE_FLAG_32BIT, @@ -610,8 +670,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units, max_threads_per_block / 64); - si_init_compiler(sscreen, &sctx->compiler); - /* Bindless handles. */ sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal); @@ -633,12 +691,15 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, /* this must be last */ si_begin_new_gfx_cs(sctx); - if (sctx->chip_class == CIK) { - /* Clear the NULL constant buffer, because loads should return zeros. */ + if (sctx->chip_class == GFX7) { + /* Clear the NULL constant buffer, because loads should return zeros. + * Note that this forces CP DMA to be used, because clover deadlocks + * for some reason when the compute codepath is used. + */ uint32_t clear_value = 0; si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0, - &clear_value, 4, SI_COHERENCY_SHADER); + &clear_value, 4, SI_COHERENCY_SHADER, true); } return &sctx->b; fail: @@ -674,7 +735,7 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, * implementation for fence_server_sync is incomplete. */ return threaded_context_create(ctx, &sscreen->pool_transfers, si_replace_buffer_storage, - sscreen->info.drm_major >= 3 ? si_create_fence : NULL, + sscreen->info.is_amdgpu ? si_create_fence : NULL, &((struct si_context*)ctx)->tc); } @@ -696,9 +757,23 @@ static void si_destroy_screen(struct pipe_screen* pscreen) if (!sscreen->ws->unref(sscreen->ws)) return; + simple_mtx_destroy(&sscreen->aux_context_lock); + + struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log; + if (aux_log) { + sscreen->aux_context->set_log_context(sscreen->aux_context, NULL); + u_log_context_destroy(aux_log); + FREE(aux_log); + } + + sscreen->aux_context->destroy(sscreen->aux_context); + util_queue_destroy(&sscreen->shader_compiler_queue); util_queue_destroy(&sscreen->shader_compiler_queue_low_priority); + /* Release the reference on glsl types of the compiler threads. */ + glsl_type_singleton_decref(); + for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++) si_destroy_compiler(&sscreen->compiler[i]); @@ -711,19 +786,17 @@ static void si_destroy_screen(struct pipe_screen* pscreen) struct si_shader_part *part = parts[i]; parts[i] = part->next; - ac_shader_binary_clean(&part->binary); + si_shader_binary_clean(&part->binary); FREE(part); } } - mtx_destroy(&sscreen->shader_parts_mutex); + simple_mtx_destroy(&sscreen->shader_parts_mutex); si_destroy_shader_cache(sscreen); si_destroy_perfcounters(sscreen); si_gpu_load_kill_thread(sscreen); - mtx_destroy(&sscreen->gpu_load_mutex); - mtx_destroy(&sscreen->aux_context_lock); - sscreen->aux_context->destroy(sscreen->aux_context); + simple_mtx_destroy(&sscreen->gpu_load_mutex); slab_destroy_parent(&sscreen->pool_transfers); @@ -826,19 +899,19 @@ static void si_disk_cache_create(struct si_screen *sscreen) disk_cache_format_hex_id(cache_id, sha1, 20 * 2); /* These flags affect shader compilation. */ - #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \ - DBG(SI_SCHED) | \ - DBG(GISEL) | \ - DBG(UNSAFE_MATH) | \ - DBG(NIR)) - uint64_t shader_debug_flags = sscreen->debug_flags & - ALL_FLAGS; + #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL)) + uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS; + /* Reserve left-most bit for tgsi/nir selector */ + assert(!(shader_debug_flags & (1u << 31))); + shader_debug_flags |= (uint32_t) + ((sscreen->options.enable_nir & 0x1) << 31); /* Add the high bits of 32-bit addresses, which affects * how 32-bit addresses are expanded to 64 bits. */ STATIC_ASSERT(ALL_FLAGS <= UINT_MAX); - shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32; + assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi); + shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32; sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, @@ -846,11 +919,33 @@ static void si_disk_cache_create(struct si_screen *sscreen) shader_debug_flags); } -struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, - const struct pipe_screen_config *config) +static void si_set_max_shader_compiler_threads(struct pipe_screen *screen, + unsigned max_threads) +{ + struct si_screen *sscreen = (struct si_screen *)screen; + + /* This function doesn't allow a greater number of threads than + * the queue had at its creation. */ + util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, + max_threads); + /* Don't change the number of threads on the low priority queue. */ +} + +static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen, + void *shader, + enum pipe_shader_type shader_type) +{ + struct si_shader_selector *sel = (struct si_shader_selector *)shader; + + return util_queue_fence_is_signalled(&sel->ready); +} + +static struct pipe_screen * +radeonsi_screen_create_impl(struct radeon_winsys *ws, + const struct pipe_screen_config *config) { struct si_screen *sscreen = CALLOC_STRUCT(si_screen); - unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i; + unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads; if (!sscreen) { return NULL; @@ -859,6 +954,12 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->ws = ws; ws->query_info(ws, &sscreen->info); + if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) { + fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n"); + FREE(sscreen); + return NULL; + } + if (sscreen->info.chip_class >= GFX9) { sscreen->se_tile_repeat = 32 * sscreen->info.max_se; } else { @@ -873,9 +974,17 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", debug_options, 0); + if (sscreen->debug_flags & DBG(NO_GFX)) + sscreen->info.has_graphics = false; + /* Set functions first. */ sscreen->b.context_create = si_pipe_create_context; sscreen->b.destroy = si_destroy_screen; + sscreen->b.set_max_shader_compiler_threads = + si_set_max_shader_compiler_threads; + sscreen->b.is_parallel_shader_compilation_finished = + si_is_parallel_shader_compilation_finished; + sscreen->b.finalize_nir = si_finalize_nir; si_init_screen_get_functions(sscreen); si_init_screen_buffer_functions(sscreen); @@ -892,8 +1001,6 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL); if (driQueryOptionb(config->options, "radeonsi_enable_sisched")) sscreen->debug_flags |= DBG(SI_SCHED); - if (driQueryOptionb(config->options, "radeonsi_enable_nir")) - sscreen->debug_flags |= DBG(NIR); if (sscreen->debug_flags & DBG(INFO)) ac_print_gpu_info(&sscreen->info); @@ -902,14 +1009,18 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sizeof(struct si_transfer), 64); sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1)); + if (sscreen->force_aniso == -1) { + sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1)); + } + if (sscreen->force_aniso >= 0) { printf("radeonsi: Forcing anisotropy filter to %ix\n", /* round down to a power of two */ 1 << util_logbase2(sscreen->force_aniso)); } - (void) mtx_init(&sscreen->aux_context_lock, mtx_plain); - (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain); + (void) simple_mtx_init(&sscreen->aux_context_lock, mtx_plain); + (void) simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain); si_init_gs_info(sscreen); if (!si_init_shader_cache(sscreen)) { @@ -917,6 +1028,13 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, return NULL; } + { +#define OPT_BOOL(name, dflt, description) \ + sscreen->options.name = \ + driQueryOptionb(config->options, "radeonsi_"#name); +#include "si_debug_options.h" + } + si_disk_cache_create(sscreen); /* Determine the number of shader compiler threads. */ @@ -941,12 +1059,16 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp)); + /* Take a reference on the glsl types for the compiler threads. */ + glsl_type_singleton_init_or_ref(); + if (!util_queue_init(&sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads, UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) { si_destroy_shader_cache(sscreen); FREE(sscreen); + glsl_type_singleton_decref(); return NULL; } @@ -958,6 +1080,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) { si_destroy_shader_cache(sscreen); FREE(sscreen); + glsl_type_singleton_decref(); return NULL; } @@ -965,17 +1088,19 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, si_init_perfcounters(sscreen); /* Determine tessellation ring info. */ - bool double_offchip_buffers = sscreen->info.chip_class >= CIK && + bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 && sscreen->info.family != CHIP_CARRIZO && sscreen->info.family != CHIP_STONEY; /* This must be one less than the maximum number due to a hw limitation. - * Various hardware bugs in SI, CIK, and GFX9 need this. + * Various hardware bugs need this. */ unsigned max_offchip_buffers_per_se; + if (sscreen->info.chip_class >= GFX10) + max_offchip_buffers_per_se = 256; /* Only certain chips can use the maximum value. */ - if (sscreen->info.family == CHIP_VEGA12 || - sscreen->info.family == CHIP_VEGA20) + else if (sscreen->info.family == CHIP_VEGA12 || + sscreen->info.family == CHIP_VEGA20) max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64; else max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63; @@ -996,12 +1121,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se; - assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0); sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4; - if (sscreen->info.chip_class >= CIK) { - if (sscreen->info.chip_class >= VI) + if (sscreen->info.chip_class >= GFX7) { + if (sscreen->info.chip_class >= GFX8) --max_offchip_buffers; sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) | @@ -1012,51 +1136,38 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); } - /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs - * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc. - * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/ - sscreen->has_clear_state = sscreen->info.chip_class >= CIK && - sscreen->info.drm_major == 3; - - sscreen->has_distributed_tess = - sscreen->info.chip_class >= VI && - sscreen->info.max_se >= 2; - sscreen->has_draw_indirect_multi = (sscreen->info.family >= CHIP_POLARIS10) || - (sscreen->info.chip_class == VI && + (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 && sscreen->info.me_fw_version >= 87) || - (sscreen->info.chip_class == CIK && + (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 && sscreen->info.me_fw_version >= 173) || - (sscreen->info.chip_class == SI && + (sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 && sscreen->info.me_fw_version >= 142); - sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI && - sscreen->info.max_se >= 2 && + sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER)); sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights"); sscreen->commutative_blend_add = driQueryOptionb(config->options, "radeonsi_commutative_blend_add"); - sscreen->clear_db_cache_before_clear = - driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear"); - sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 && - sscreen->info.family <= CHIP_POLARIS12) || - sscreen->info.family == CHIP_VEGA10 || - sscreen->info.family == CHIP_RAVEN; - sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 || - sscreen->info.family == CHIP_RAVEN; - sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2; - /* Only enable primitive binning on APUs by default. */ - sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN || - sscreen->info.family == CHIP_RAVEN2; + sscreen->use_ngg = sscreen->info.chip_class >= GFX10 && + sscreen->info.family != CHIP_NAVI14 && + !(sscreen->debug_flags & DBG(NO_NGG)); + sscreen->use_ngg_streamout = false; - sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN || - sscreen->info.family == CHIP_RAVEN2; + /* Only enable primitive binning on APUs by default. */ + if (sscreen->info.chip_class >= GFX10) { + sscreen->dpbb_allowed = true; + sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram; + } else if (sscreen->info.chip_class == GFX9) { + sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram; + sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram; + } /* Process DPBB enable flags. */ if (sscreen->debug_flags & DBG(DPBB)) { @@ -1074,40 +1185,22 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } /* While it would be nice not to have this flag, we are constrained - * by the reality that LLVM 5.0 doesn't have working VGPR indexing - * on GFX9. + * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9. */ - sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI; - - /* Some chips have RB+ registers, but don't support RB+. Those must - * always disable it. - */ - if (sscreen->info.family == CHIP_STONEY || - sscreen->info.chip_class >= GFX9) { - sscreen->has_rbplus = true; - - sscreen->rbplus_allowed = - !(sscreen->debug_flags & DBG(NO_RB_PLUS)) && - (sscreen->info.family == CHIP_STONEY || - sscreen->info.family == CHIP_VEGA12 || - sscreen->info.family == CHIP_RAVEN || - sscreen->info.family == CHIP_RAVEN2); - } + sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9; sscreen->dcc_msaa_allowed = !(sscreen->debug_flags & DBG(NO_DCC_MSAA)); - sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI; - - (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain); + (void) simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain); sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0; - sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 | - SI_CONTEXT_INV_VMEM_L1; - if (sscreen->info.chip_class <= VI) { - sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2; - sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | + SI_CONTEXT_INV_VCACHE; + if (sscreen->info.chip_class <= GFX8) { + sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2; + sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2; } if (debug_get_bool_option("RADEON_DUMP_SHADERS", false)) @@ -1138,13 +1231,40 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } } - for (i = 0; i < num_comp_hi_threads; i++) - si_init_compiler(sscreen, &sscreen->compiler[i]); - for (i = 0; i < num_comp_lo_threads; i++) - si_init_compiler(sscreen, &sscreen->compiler_lowp[i]); + sscreen->ge_wave_size = 64; + sscreen->ps_wave_size = 64; + sscreen->compute_wave_size = 64; + + if (sscreen->info.chip_class >= GFX10) { + /* Pixels shaders: Wave64 is recommended. + * Compute shaders: There are piglit failures with Wave32. + */ + sscreen->ge_wave_size = 32; + + if (sscreen->debug_flags & DBG(W32_GE)) + sscreen->ge_wave_size = 32; + if (sscreen->debug_flags & DBG(W32_PS)) + sscreen->ps_wave_size = 32; + if (sscreen->debug_flags & DBG(W32_CS)) + sscreen->compute_wave_size = 32; + + if (sscreen->debug_flags & DBG(W64_GE)) + sscreen->ge_wave_size = 64; + if (sscreen->debug_flags & DBG(W64_PS)) + sscreen->ps_wave_size = 64; + if (sscreen->debug_flags & DBG(W64_CS)) + sscreen->compute_wave_size = 64; + } /* Create the auxiliary context. This must be done last. */ - sscreen->aux_context = si_create_context(&sscreen->b, 0); + sscreen->aux_context = si_create_context(&sscreen->b, + (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) | + (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY)); + if (sscreen->options.aux_debug) { + struct u_log_context *log = CALLOC_STRUCT(u_log_context); + u_log_context_init(log); + sscreen->aux_context->set_log_context(sscreen->aux_context, log); + } if (sscreen->debug_flags & DBG(TEST_DMA)) si_test_dma(sscreen); @@ -1172,3 +1292,21 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, return &sscreen->b; } + +struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config) +{ + drmVersionPtr version = drmGetVersion(fd); + struct radeon_winsys *rw = NULL; + + switch (version->version_major) { + case 2: + rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl); + break; + case 3: + rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl); + break; + } + + drmFreeVersion(version); + return rw ? rw->screen : NULL; +}