X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_pipe.h;h=179671e8871d8b2ad3398ed087665d5c4b604b9c;hb=ce785f5ffd7dbed14a3909164e55a975a023ee97;hp=eb0c226ed79cdb839ce5a1c5cecf8b035de1a38d;hpb=f3b3ee6974d1b34b219f0d960a1424afe07a93f1;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index eb0c226ed79..179671e8871 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -30,7 +30,6 @@ #include "util/u_dynarray.h" #include "util/u_idalloc.h" -#include "util/u_range.h" #include "util/u_threaded_context.h" #ifdef PIPE_ARCH_BIG_ENDIAN @@ -49,10 +48,16 @@ #define SI_BASE_VERTEX_UNKNOWN INT_MIN #define SI_RESTART_INDEX_UNKNOWN INT_MIN #define SI_NUM_SMOOTH_AA_SAMPLES 8 +#define SI_MAX_POINT_SIZE 2048 #define SI_GS_PER_ES 128 /* Alignment for optimal CP DMA performance. */ #define SI_CPDMA_ALIGNMENT 32 +/* Tunables for compute-based clear_buffer and copy_buffer: */ +#define SI_COMPUTE_CLEAR_DW_PER_THREAD 4 +#define SI_COMPUTE_COPY_DW_PER_THREAD 4 +#define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM + /* Pipeline & streamout query controls. */ #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0) #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1) @@ -98,11 +103,12 @@ #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0) #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1) -#define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2) +#define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2) #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4) #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5) #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6) +#define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7) /* Debug flags. */ enum { @@ -122,6 +128,7 @@ enum { DBG_FS_CORRECT_DERIVS_AFTER_KILL, DBG_UNSAFE_MATH, DBG_SI_SCHED, + DBG_GISEL, /* Shader compiler options (with no effect on the shader cache): */ DBG_CHECK_IR, @@ -141,6 +148,7 @@ enum { DBG_NO_WC, DBG_CHECK_VM, DBG_RESERVE_VMID, + DBG_ZERO_VRAM, /* 3D engine options: */ DBG_SWITCH_ON_EOP, @@ -164,11 +172,28 @@ enum { DBG_TEST_VMFAULT_CP, DBG_TEST_VMFAULT_SDMA, DBG_TEST_VMFAULT_SHADER, + DBG_TEST_DMA_PERF, + DBG_TEST_GDS, + DBG_TEST_GDS_MM, + DBG_TEST_GDS_OA_MM, }; #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1)) #define DBG(name) (1ull << DBG_##name) +enum si_cache_policy { + L2_BYPASS, + L2_STREAM, /* same as SLC=1 */ + L2_LRU, /* same as SLC=0 */ +}; + +enum si_coherency { + SI_COHERENCY_NONE, /* no cache flushes needed */ + SI_COHERENCY_SHADER, + SI_COHERENCY_CB_META, + SI_COHERENCY_CP, +}; + struct si_compute; struct hash_table; struct u_suballocator; @@ -216,45 +241,37 @@ struct r600_resource { */ bool TC_L2_dirty; - /* Whether the resource has been exported via resource_get_handle. */ - unsigned external_usage; /* PIPE_HANDLE_USAGE_* */ - /* Whether this resource is referenced by bindless handles. */ bool texture_handle_allocated; bool image_handle_allocated; + + /* Whether the resource has been exported via resource_get_handle. */ + unsigned external_usage; /* PIPE_HANDLE_USAGE_* */ }; -struct r600_transfer { +struct si_transfer { struct threaded_transfer b; struct r600_resource *staging; unsigned offset; }; -struct r600_cmask_info { - uint64_t offset; - uint64_t size; - unsigned alignment; - unsigned slice_tile_max; - uint64_t base_address_reg; -}; - -struct r600_texture { +struct si_texture { struct r600_resource buffer; struct radeon_surf surface; uint64_t size; - struct r600_texture *flushed_depth_texture; + struct si_texture *flushed_depth_texture; /* Colorbuffer compression and fast clear. */ uint64_t fmask_offset; - struct r600_cmask_info cmask; + uint64_t cmask_offset; + uint64_t cmask_base_address_reg; struct r600_resource *cmask_buffer; uint64_t dcc_offset; /* 0 = disabled */ unsigned cb_color_info; /* fast clear enable bit */ unsigned color_clear_value[2]; unsigned last_msaa_resolve_target_micro_mode; unsigned num_level0_transfers; - unsigned num_color_samples; /* Depth buffer compression and fast clear. */ uint64_t htile_offset; @@ -305,7 +322,7 @@ struct r600_texture { unsigned num_slow_clears; }; -struct r600_surface { +struct si_surface { struct pipe_surface base; /* These can vary with block-compressed textures. */ @@ -386,11 +403,10 @@ union si_mmio_counters { unsigned array[0]; }; -struct r600_memory_object { +struct si_memory_object { struct pipe_memory_object b; struct pb_buffer *buf; uint32_t stride; - uint32_t offset; }; /* Saved CS data for debugging features. */ @@ -411,6 +427,9 @@ struct si_screen { uint64_t debug_flags; char renderer_string[183]; + unsigned pa_sc_raster_config; + unsigned pa_sc_raster_config_1; + unsigned se_tile_repeat; unsigned gs_table_depth; unsigned tess_offchip_block_dw_size; unsigned tess_offchip_ring_size; @@ -428,6 +447,7 @@ struct si_screen { bool clear_db_cache_before_clear; bool has_msaa_sample_loc_bug; bool has_ls_vgpr_init_bug; + bool has_dcc_constant_encode; bool dpbb_allowed; bool dfsm_allowed; bool llvm_has_working_vgpr_indexing; @@ -523,12 +543,12 @@ struct si_screen { /* Use at most 3 normal compiler threads on quadcore and better. * Hyperthreaded CPUs report the number of threads, but we want * the number of cores. We only need this many threads for shader-db. */ - struct si_compiler compiler[24]; /* used by the queue only */ + struct ac_llvm_compiler compiler[24]; /* used by the queue only */ struct util_queue shader_compiler_queue_low_priority; /* Use at most 2 low priority threads on quadcore and better. * We want to minimize the impact on multithreaded Mesa. */ - struct si_compiler compiler_lowp[10]; + struct ac_llvm_compiler compiler_lowp[10]; }; struct si_blend_color { @@ -600,17 +620,26 @@ struct si_framebuffer { ubyte color_is_int8; ubyte color_is_int10; ubyte dirty_cbufs; + ubyte dcc_overwrite_combiner_watermark; bool dirty_zsbuf; bool any_dst_linear; bool CB_has_shader_readable_metadata; bool DB_has_shader_readable_metadata; }; +enum si_quant_mode { + /* This is the list we want to support. */ + SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH, + SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH, + SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH, +}; + struct si_signed_scissor { int minx; int miny; int maxx; int maxy; + enum si_quant_mode quant_mode; }; struct si_scissors { @@ -744,8 +773,8 @@ struct si_context { struct radeon_winsys *ws; struct radeon_winsys_ctx *ctx; - struct radeon_winsys_cs *gfx_cs; - struct radeon_winsys_cs *dma_cs; + struct radeon_cmdbuf *gfx_cs; + struct radeon_cmdbuf *dma_cs; struct pipe_fence_handle *last_gfx_fence; struct pipe_fence_handle *last_sdma_fence; struct r600_resource *eop_bug_scratch; @@ -768,9 +797,11 @@ struct si_context { void *vs_blit_color; void *vs_blit_color_layered; void *vs_blit_texcoord; + void *cs_clear_buffer; + void *cs_copy_buffer; struct si_screen *screen; struct pipe_debug_callback debug; - struct si_compiler compiler; /* only non-threaded compilation */ + struct ac_llvm_compiler compiler; /* only non-threaded compilation */ struct si_shader_ctx_state fixed_func_tcs_shader; struct r600_resource *wait_mem_scratch; unsigned wait_mem_number; @@ -811,6 +842,9 @@ struct si_context { struct si_scissors scissors; struct si_streamout streamout; struct si_viewports viewports; + unsigned num_window_rectangles; + bool window_rectangles_include; + struct pipe_scissor_state window_rectangles[4]; /* Precomputed states. */ struct si_pm4_state *init_config; @@ -829,6 +863,7 @@ struct si_context { /* shader information */ struct si_vertex_elements *vertex_elements; unsigned sprite_coord_enable; + unsigned cs_max_waves_per_sh; bool flatshade; bool do_update_shaders; @@ -858,6 +893,7 @@ struct si_context { unsigned border_color_count; unsigned num_vs_blit_sgprs; uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD]; + uint32_t cs_user_data[4]; /* Vertex and index buffers. */ bool vertex_buffers_dirty; @@ -963,11 +999,14 @@ struct si_context { /* MSAA sample locations. * The first index is the sample index. * The second index is the coordinate: X, Y. */ - float sample_locations_1x[1][2]; - float sample_locations_2x[2][2]; - float sample_locations_4x[4][2]; - float sample_locations_8x[8][2]; - float sample_locations_16x[16][2]; + struct { + float x1[1][2]; + float x2[2][2]; + float x4[4][2]; + float x8[8][2]; + float x16[16][2]; + } sample_positions; + struct pipe_resource *sample_pos_buffer; /* Misc stats. */ unsigned num_draw_calls; @@ -989,6 +1028,7 @@ struct si_context { unsigned num_resident_handles; uint64_t num_alloc_tex_transfer_bytes; unsigned last_tex_ps_draw_ratio; /* for query */ + unsigned context_roll_counter; /* Queries. */ /* Maintain the list of active queries for pausing between IBs. */ @@ -1004,7 +1044,7 @@ struct si_context { bool render_cond_force_off; /* for u_blitter */ /* Statistics gathering for the DCC enablement heuristic. It can't be - * in r600_texture because r600_texture can be shared by multiple + * in si_texture because si_texture can be shared by multiple * contexts. This is for back buffers only. We shouldn't get too many * of those. * @@ -1013,7 +1053,7 @@ struct si_context { * enabled by DCC stat gathering. */ struct { - struct r600_texture *tex; + struct si_texture *tex; /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */ struct pipe_query *ps_stats[3]; /* If all slots are used and another slot is needed, @@ -1031,9 +1071,6 @@ struct si_context { unsigned src_level, const struct pipe_box *src_box); - void (*dma_clear_buffer)(struct si_context *sctx, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value); - struct si_tracked_regs tracked_regs; }; @@ -1060,10 +1097,10 @@ void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *src, unsigned src_level, const struct pipe_box *src_box); -void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex); +void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex); void si_blit_decompress_depth(struct pipe_context *ctx, - struct r600_texture *texture, - struct r600_texture *staging, + struct si_texture *texture, + struct si_texture *staging, unsigned first_level, unsigned last_level, unsigned first_layer, unsigned last_layer, unsigned first_sample, unsigned last_sample); @@ -1096,10 +1133,21 @@ void si_init_buffer_functions(struct si_context *sctx); enum pipe_format si_simplify_cb_format(enum pipe_format format); bool vi_alpha_is_on_msb(enum pipe_format format); void vi_dcc_clear_level(struct si_context *sctx, - struct r600_texture *rtex, + struct si_texture *tex, unsigned level, unsigned clear_value); void si_init_clear_functions(struct si_context *sctx); +/* si_compute_blit.c */ +unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher, + enum si_cache_policy cache_policy); +void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, + uint64_t offset, uint64_t size, uint32_t *clear_value, + uint32_t clear_value_size, enum si_coherency coher); +void si_copy_buffer(struct si_context *sctx, + struct pipe_resource *dst, struct pipe_resource *src, + uint64_t dst_offset, uint64_t src_offset, unsigned size); +void si_init_compute_blit_functions(struct si_context *sctx); + /* si_cp_dma.c */ #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */ #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */ @@ -1112,27 +1160,23 @@ void si_init_clear_functions(struct si_context *sctx); SI_CPDMA_SKIP_GFX_SYNC | \ SI_CPDMA_SKIP_BO_LIST_UPDATE) -enum si_coherency { - SI_COHERENCY_NONE, /* no cache flushes needed */ - SI_COHERENCY_SHADER, - SI_COHERENCY_CB_META, -}; - void si_cp_dma_wait_for_idle(struct si_context *sctx); -void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, - uint64_t offset, uint64_t size, unsigned value, - enum si_coherency coher); -void si_copy_buffer(struct si_context *sctx, - struct pipe_resource *dst, struct pipe_resource *src, - uint64_t dst_offset, uint64_t src_offset, unsigned size, - unsigned user_flags); +void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs, + struct pipe_resource *dst, uint64_t offset, + uint64_t size, unsigned value, unsigned user_flags, + enum si_coherency coher, enum si_cache_policy cache_policy); +void si_cp_dma_copy_buffer(struct si_context *sctx, + struct pipe_resource *dst, struct pipe_resource *src, + uint64_t dst_offset, uint64_t src_offset, unsigned size, + unsigned user_flags, enum si_coherency coher, + enum si_cache_policy cache_policy); void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf, uint64_t offset, unsigned size); void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only); -void si_init_cp_dma_functions(struct si_context *sctx); +void si_test_gds(struct si_context *sctx); /* si_debug.c */ -void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, +void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved, bool get_buffer_list); void si_clear_saved_cs(struct radeon_saved_cs *saved); void si_destroy_saved_cs(struct si_saved_cs *scs); @@ -1149,6 +1193,10 @@ bool si_replace_shader(unsigned num, struct ac_shader_binary *binary); void si_init_dma_functions(struct si_context *sctx); /* si_dma_cs.c */ +void si_dma_emit_timestamp(struct si_context *sctx, struct r600_resource *dst, + uint64_t offset); +void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, + uint64_t offset, uint64_t size, unsigned clear_value); void si_need_dma_space(struct si_context *ctx, unsigned num_dw, struct r600_resource *dst, struct r600_resource *src); void si_flush_dma_cs(struct si_context *ctx, unsigned flags, @@ -1157,21 +1205,20 @@ void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst uint64_t offset, uint64_t size, unsigned value); /* si_fence.c */ -void si_gfx_write_event_eop(struct si_context *ctx, - unsigned event, unsigned event_flags, - unsigned data_sel, - struct r600_resource *buf, uint64_t va, - uint32_t new_fence, unsigned query_type); -unsigned si_gfx_write_fence_dwords(struct si_screen *screen); -void si_gfx_wait_fence(struct si_context *ctx, - uint64_t va, uint32_t ref, uint32_t mask); +void si_cp_release_mem(struct si_context *ctx, + unsigned event, unsigned event_flags, + unsigned dst_sel, unsigned int_sel, unsigned data_sel, + struct r600_resource *buf, uint64_t va, + uint32_t new_fence, unsigned query_type); +unsigned si_cp_write_fence_dwords(struct si_screen *screen); +void si_cp_wait_mem(struct si_context *ctx, + uint64_t va, uint32_t ref, uint32_t mask, unsigned flags); void si_init_fence_functions(struct si_context *ctx); void si_init_screen_fence_functions(struct si_screen *screen); struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx, struct tc_unflushed_batch_token *tc_token); /* si_get.c */ -const char *si_get_family_name(const struct si_screen *sscreen); void si_init_screen_get_functions(struct si_screen *sscreen); /* si_gfx_cs.c */ @@ -1204,9 +1251,21 @@ void si_init_query_functions(struct si_context *sctx); void si_suspend_queries(struct si_context *sctx); void si_resume_queries(struct si_context *sctx); +/* si_shaderlib_tgsi.c */ +void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type, + unsigned num_layers); +void *si_create_fixed_func_tcs(struct si_context *sctx); +void *si_create_dma_compute_shader(struct pipe_context *ctx, + unsigned num_dwords_per_thread, + bool dst_stream_cache_policy, bool is_copy); +void *si_create_query_result_cs(struct si_context *sctx); + /* si_test_dma.c */ void si_test_dma(struct si_screen *sscreen); +/* si_test_clearbuffer.c */ +void si_test_dma_perf(struct si_screen *sscreen); + /* si_uvd.c */ struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context, const struct pipe_video_codec *templ); @@ -1218,26 +1277,23 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe, void si_update_vs_viewport_state(struct si_context *ctx); void si_init_viewport_functions(struct si_context *ctx); -/* r600_texture.c */ +/* si_texture.c */ bool si_prepare_for_dma_blit(struct si_context *sctx, - struct r600_texture *rdst, + struct si_texture *dst, unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz, - struct r600_texture *rsrc, + struct si_texture *src, unsigned src_level, const struct pipe_box *src_box); -void si_texture_get_cmask_info(struct si_screen *sscreen, - struct r600_texture *rtex, - struct r600_cmask_info *out); void si_eliminate_fast_color_clear(struct si_context *sctx, - struct r600_texture *rtex); + struct si_texture *tex); void si_texture_discard_cmask(struct si_screen *sscreen, - struct r600_texture *rtex); + struct si_texture *tex); bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture, - struct r600_texture **staging); + struct si_texture **staging); void si_print_texture_info(struct si_screen *sscreen, - struct r600_texture *rtex, struct u_log_context *log); + struct si_texture *tex, struct u_log_context *log); struct pipe_resource *si_texture_create(struct pipe_screen *screen, const struct pipe_resource *templ); bool vi_dcc_formats_compatible(enum pipe_format format1, @@ -1256,15 +1312,15 @@ struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe, unsigned width, unsigned height); unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap); void vi_separate_dcc_try_enable(struct si_context *sctx, - struct r600_texture *tex); + struct si_texture *tex); void vi_separate_dcc_start_query(struct si_context *sctx, - struct r600_texture *tex); + struct si_texture *tex); void vi_separate_dcc_stop_query(struct si_context *sctx, - struct r600_texture *tex); + struct si_texture *tex); void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx, - struct r600_texture *tex); + struct si_texture *tex); bool si_texture_disable_dcc(struct si_context *sctx, - struct r600_texture *rtex); + struct si_texture *tex); void si_init_screen_texture_functions(struct si_screen *sscreen); void si_init_context_texture_functions(struct si_context *sctx); @@ -1286,24 +1342,24 @@ r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res) } static inline void -r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res) +si_texture_reference(struct si_texture **ptr, struct si_texture *res) { pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b); } static inline bool -vi_dcc_enabled(struct r600_texture *tex, unsigned level) +vi_dcc_enabled(struct si_texture *tex, unsigned level) { return tex->dcc_offset && level < tex->surface.num_dcc_levels; } static inline unsigned -si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) +si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil) { if (stencil) - return rtex->surface.u.legacy.stencil_tiling_index[level]; + return tex->surface.u.legacy.stencil_tiling_index[level]; else - return rtex->surface.u.legacy.tiling_index[level]; + return tex->surface.u.legacy.tiling_index[level]; } static inline void @@ -1458,20 +1514,20 @@ si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples, } static inline bool -si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler) +si_can_sample_zs(struct si_texture *tex, bool stencil_sampler) { return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z); } static inline bool -si_htile_enabled(struct r600_texture *tex, unsigned level) +si_htile_enabled(struct si_texture *tex, unsigned level) { return tex->htile_offset && level == 0; } static inline bool -vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level) +vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level) { assert(!tex->tc_compatible_htile || tex->htile_offset); return tex->tc_compatible_htile && level == 0; @@ -1531,7 +1587,7 @@ static inline bool util_prim_is_points_or_lines(unsigned prim) */ static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint64_t vram, uint64_t gtt) { vram += cs->used_vram; @@ -1556,7 +1612,7 @@ radeon_cs_memory_below_limit(struct si_screen *screen, * rebuilt. */ static inline void radeon_add_to_buffer_list(struct si_context *sctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, struct r600_resource *rbo, enum radeon_bo_usage usage, enum radeon_bo_priority priority)