X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_pipe.h;h=431d8a3a4290f34e8cd3e6e8f0e7623bef8a35bb;hb=c485b47383337af02601ab41ad63cc8dbd2fd3ee;hp=174baaa01d33c410d548524782c7b9a719971c4c;hpb=ba2e7c68ce8d37ebd666614a47abb33502b38ce5;p=mesa.git

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 174baaa01d3..431d8a3a429 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -79,6 +79,7 @@ struct si_screen {
 	bool				has_distributed_tess;
 	bool				has_draw_indirect_multi;
 	bool				has_ds_bpermute;
+	bool				has_msaa_sample_loc_bug;
 
 	/* Whether shaders are monolithic (1-part) or separate (3-part). */
 	bool				use_monolithic_shaders;
@@ -86,7 +87,6 @@ struct si_screen {
 
 	mtx_t			shader_parts_mutex;
 	struct si_shader_part		*vs_prologs;
-	struct si_shader_part		*vs_epilogs;
 	struct si_shader_part		*tcs_epilogs;
 	struct si_shader_part		*gs_prologs;
 	struct si_shader_part		*ps_prologs;
@@ -127,6 +127,7 @@ struct si_sampler_view {
 	unsigned			base_level;
 	unsigned			block_width;
 	bool is_stencil_sampler;
+	bool dcc_incompatible;
 };
 
 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
@@ -216,7 +217,7 @@ union si_vgt_param_key {
 		unsigned count_from_stream_output:1;
 		unsigned line_stipple_enabled:1;
 		unsigned uses_tess:1;
-		unsigned tcs_tes_uses_prim_id:1;
+		unsigned tess_uses_prim_id:1;
 		unsigned uses_gs:1;
 		unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 	} u;
@@ -259,6 +260,7 @@ struct si_context {
 	struct r600_atom		msaa_config;
 	struct si_sample_mask		sample_mask;
 	struct r600_atom		cb_render_state;
+	unsigned			last_cb_target_mask;
 	struct si_blend_color		blend_color;
 	struct r600_atom		clip_regs;
 	struct si_clip_state		clip_state;
@@ -312,7 +314,6 @@ struct si_context {
 	/* Vertex and index buffers. */
 	bool				vertex_buffers_dirty;
 	bool				vertex_buffer_pointer_dirty;
-	struct pipe_index_buffer	index_buffer;
 	struct pipe_vertex_buffer	vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 
 	/* MSAA config state. */
@@ -345,7 +346,9 @@ struct si_context {
 	int			last_multi_vgt_param;
 	int			last_rast_prim;
 	unsigned		last_sc_line_stipple;
-	int			current_rast_prim; /* primitive type after TES, GS */
+	unsigned		current_vs_state;
+	unsigned		last_vs_state;
+	enum pipe_prim_type	current_rast_prim; /* primitive type after TES, GS */
 	bool			gs_tri_strip_adj_fix;
 
 	/* Scratch buffer */
@@ -357,7 +360,8 @@ struct si_context {
 	struct r600_resource	*compute_scratch_buffer;
 
 	/* Emitted derived tessellation state. */
-	struct si_shader	*last_ls; /* local shader (VS) */
+	/* Local shader (VS), or HS if LS-HS are merged. */
+	struct si_shader	*last_ls;
 	struct si_shader_selector *last_tcs;
 	int			last_num_tcs_input_cp;
 	int			last_tes_sh_base;
@@ -503,16 +507,6 @@ static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 		return sctx->vs_shader.current;
 }
 
-static inline bool si_vs_exports_prim_id(struct si_shader *shader)
-{
-	if (shader->selector->type == PIPE_SHADER_VERTEX)
-		return shader->key.part.vs.epilog.export_prim_id;
-	else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
-		return shader->key.part.tes.epilog.export_prim_id;
-	else
-		return false;
-}
-
 static inline unsigned
 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 {