X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_pipe.h;h=431d8a3a4290f34e8cd3e6e8f0e7623bef8a35bb;hb=c485b47383337af02601ab41ad63cc8dbd2fd3ee;hp=4075d2c0aa15b09ebd494961d32324af0c3f659d;hpb=65df38b191b107a9ff917ae3cf9b2f0ca2d15627;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 4075d2c0aa1..431d8a3a429 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -41,6 +41,8 @@ #define SI_RESTART_INDEX_UNKNOWN INT_MIN #define SI_NUM_SMOOTH_AA_SAMPLES 8 #define SI_GS_PER_ES 128 +/* Alignment for optimal CP DMA performance. */ +#define SI_CPDMA_ALIGNMENT 32 /* Instruction cache. */ #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0) @@ -64,9 +66,6 @@ #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12) #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13) -#define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \ - SI_CONTEXT_FLUSH_AND_INV_DB) - #define SI_MAX_BORDER_COLORS 4096 struct si_compute; @@ -80,14 +79,14 @@ struct si_screen { bool has_distributed_tess; bool has_draw_indirect_multi; bool has_ds_bpermute; + bool has_msaa_sample_loc_bug; /* Whether shaders are monolithic (1-part) or separate (3-part). */ bool use_monolithic_shaders; bool record_llvm_ir; - pipe_mutex shader_parts_mutex; + mtx_t shader_parts_mutex; struct si_shader_part *vs_prologs; - struct si_shader_part *vs_epilogs; struct si_shader_part *tcs_epilogs; struct si_shader_part *gs_prologs; struct si_shader_part *ps_prologs; @@ -105,7 +104,7 @@ struct si_screen { * - GS and CS aren't cached, but it's certainly possible to cache * those as well. */ - pipe_mutex shader_cache_mutex; + mtx_t shader_cache_mutex; struct hash_table *shader_cache; /* Shader compiler queue for multithreaded compilation. */ @@ -124,10 +123,11 @@ struct si_sampler_view { * [4..7] = buffer descriptor */ uint32_t state[8]; uint32_t fmask_state[8]; - const struct radeon_surf_level *base_level_info; + const struct legacy_surf_level *base_level_info; unsigned base_level; unsigned block_width; bool is_stencil_sampler; + bool dcc_incompatible; }; #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a @@ -170,7 +170,8 @@ struct si_framebuffer { unsigned spi_shader_col_format_alpha; unsigned spi_shader_col_format_blend; unsigned spi_shader_col_format_blend_alpha; - unsigned color_is_int8; /* bitmask */ + unsigned color_is_int8; + unsigned color_is_int10; unsigned dirty_cbufs; bool dirty_zsbuf; bool any_dst_linear; @@ -216,7 +217,7 @@ union si_vgt_param_key { unsigned count_from_stream_output:1; unsigned line_stipple_enabled:1; unsigned uses_tess:1; - unsigned tcs_tes_uses_prim_id:1; + unsigned tess_uses_prim_id:1; unsigned uses_gs:1; unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS; } u; @@ -259,6 +260,7 @@ struct si_context { struct r600_atom msaa_config; struct si_sample_mask sample_mask; struct r600_atom cb_render_state; + unsigned last_cb_target_mask; struct si_blend_color blend_color; struct r600_atom clip_regs; struct si_clip_state clip_state; @@ -312,7 +314,6 @@ struct si_context { /* Vertex and index buffers. */ bool vertex_buffers_dirty; bool vertex_buffer_pointer_dirty; - struct pipe_index_buffer index_buffer; struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS]; /* MSAA config state. */ @@ -345,7 +346,9 @@ struct si_context { int last_multi_vgt_param; int last_rast_prim; unsigned last_sc_line_stipple; - int current_rast_prim; /* primitive type after TES, GS */ + unsigned current_vs_state; + unsigned last_vs_state; + enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ bool gs_tri_strip_adj_fix; /* Scratch buffer */ @@ -357,7 +360,8 @@ struct si_context { struct r600_resource *compute_scratch_buffer; /* Emitted derived tessellation state. */ - struct si_shader *last_ls; /* local shader (VS) */ + /* Local shader (VS), or HS if LS-HS are merged. */ + struct si_shader *last_ls; struct si_shader_selector *last_tcs; int last_num_tcs_input_cp; int last_tes_sh_base; @@ -419,7 +423,7 @@ void si_init_cp_dma_functions(struct si_context *sctx); void si_init_debug_functions(struct si_context *sctx); void si_check_vm_faults(struct r600_common_context *ctx, struct radeon_saved_cs *saved, enum ring_type ring); -bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary); +bool si_replace_shader(unsigned num, struct ac_shader_binary *binary); /* si_dma.c */ void si_init_dma_functions(struct si_context *sctx); @@ -503,14 +507,19 @@ static inline struct si_shader* si_get_vs_state(struct si_context *sctx) return sctx->vs_shader.current; } -static inline bool si_vs_exports_prim_id(struct si_shader *shader) +static inline unsigned +si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size) { - if (shader->selector->type == PIPE_SHADER_VERTEX) - return shader->key.part.vs.epilog.export_prim_id; - else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) - return shader->key.part.tes.epilog.export_prim_id; - else - return false; + unsigned alignment, tcc_cache_line_size; + + /* If the upload size is less than the cache line size (e.g. 16, 32), + * the whole thing will fit into a cache line if we align it to its size. + * The idea is that multiple small uploads can share a cache line. + * If the upload size is greater, align it to the cache line size. + */ + alignment = util_next_power_of_two(upload_size); + tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size; + return MIN2(alignment, tcc_cache_line_size); } #endif