X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state.c;h=f6400d8c51a87e5e6a6f5694fc580bc70888dba5;hb=2fd42001231b70ba1764b1455d642037d2d5fff5;hp=61ede6453f039b87c065af48ab0b8c382ccc520a;hpb=dc21e30a6283629bed6db282caff0af13f3b88ec;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 61ede6453f0..f6400d8c51a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -30,12 +30,123 @@ #include "util/u_helpers.h" #include "util/u_math.h" #include "util/u_pack_color.h" +#include "util/u_upload_mgr.h" +#include "util/u_format_s3tc.h" #include "tgsi/tgsi_parse.h" #include "radeonsi_pipe.h" #include "radeonsi_shader.h" #include "si_state.h" +#include "../radeon/r600_cs.h" #include "sid.h" +static uint32_t cik_num_banks(uint32_t nbanks) +{ + switch (nbanks) { + case 2: + return V_02803C_ADDR_SURF_2_BANK; + case 4: + return V_02803C_ADDR_SURF_4_BANK; + case 8: + default: + return V_02803C_ADDR_SURF_8_BANK; + case 16: + return V_02803C_ADDR_SURF_16_BANK; + } +} + + +static unsigned cik_tile_split(unsigned tile_split) +{ + switch (tile_split) { + case 64: + tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B; + break; + case 128: + tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B; + break; + case 256: + tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B; + break; + case 512: + tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B; + break; + default: + case 1024: + tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB; + break; + case 2048: + tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB; + break; + case 4096: + tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB; + break; + } + return tile_split; +} + +static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect) +{ + switch (macro_tile_aspect) { + default: + case 1: + macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1; + break; + case 2: + macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2; + break; + case 4: + macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4; + break; + case 8: + macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8; + break; + } + return macro_tile_aspect; +} + +static unsigned cik_bank_wh(unsigned bankwh) +{ + switch (bankwh) { + default: + case 1: + bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1; + break; + case 2: + bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2; + break; + case 4: + bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4; + break; + case 8: + bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8; + break; + } + return bankwh; +} + +static unsigned cik_db_pipe_config(unsigned tile_pipes, + unsigned num_rbs) +{ + unsigned pipe_config; + + switch (tile_pipes) { + case 8: + pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16; + break; + case 4: + default: + if (num_rbs == 4) + pipe_config = V_02803C_X_ADDR_SURF_P4_16X16; + else + pipe_config = V_02803C_X_ADDR_SURF_P4_8X16; + break; + case 2: + pipe_config = V_02803C_ADDR_SURF_P2; + break; + } + return pipe_config; +} + /* * inferred framebuffer and blender state */ @@ -48,7 +159,7 @@ static void si_update_fb_blend_state(struct r600_context *rctx) if (blend == NULL) return; - pm4 = CALLOC_STRUCT(si_pm4_state); + pm4 = si_pm4_alloc_state(rctx); if (pm4 == NULL) return; @@ -133,8 +244,9 @@ static uint32_t si_translate_blend_factor(int blend_fact) return 0; } -static void *si_create_blend_state(struct pipe_context *ctx, - const struct pipe_blend_state *state) +static void *si_create_blend_state_mode(struct pipe_context *ctx, + const struct pipe_blend_state *state, + unsigned mode) { struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); struct si_pm4_state *pm4 = &blend->pm4; @@ -144,7 +256,9 @@ static void *si_create_blend_state(struct pipe_context *ctx, if (blend == NULL) return NULL; - color_control = S_028808_MODE(V_028808_CB_NORMAL); + blend->alpha_to_one = state->alpha_to_one; + + color_control = S_028808_MODE(mode); if (state->logicop_enable) { color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); } else { @@ -152,8 +266,12 @@ static void *si_create_blend_state(struct pipe_context *ctx, } si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); - si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0); - si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0); + si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, + S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | + S_028B70_ALPHA_TO_MASK_OFFSET0(2) | + S_028B70_ALPHA_TO_MASK_OFFSET1(2) | + S_028B70_ALPHA_TO_MASK_OFFSET2(2) | + S_028B70_ALPHA_TO_MASK_OFFSET3(2)); blend->cb_target_mask = 0; for (int i = 0; i < 8; i++) { @@ -194,6 +312,12 @@ static void *si_create_blend_state(struct pipe_context *ctx, return blend; } +static void *si_create_blend_state(struct pipe_context *ctx, + const struct pipe_blend_state *state) +{ + return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL); +} + static void si_bind_blend_state(struct pipe_context *ctx, void *state) { struct r600_context *rctx = (struct r600_context *)ctx; @@ -211,7 +335,7 @@ static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); if (pm4 == NULL) return; @@ -232,7 +356,8 @@ static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); + struct pipe_constant_buffer cb; if (pm4 == NULL) return; @@ -248,14 +373,23 @@ static void si_set_clip_state(struct pipe_context *ctx, fui(state->ucp[i][3])); } + cb.buffer = NULL; + cb.user_buffer = state->ucp; + cb.buffer_offset = 0; + cb.buffer_size = 4*4*8; + ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb); + pipe_resource_reference(&cb.buffer, NULL); + si_pm4_set_state(rctx, clip, pm4); } -static void si_set_scissor_state(struct pipe_context *ctx, - const struct pipe_scissor_state *state) +static void si_set_scissor_states(struct pipe_context *ctx, + unsigned start_slot, + unsigned num_scissors, + const struct pipe_scissor_state *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); uint32_t tl, br; if (pm4 == NULL) @@ -275,8 +409,10 @@ static void si_set_scissor_state(struct pipe_context *ctx, si_pm4_set_state(rctx, scissor, pm4); } -static void si_set_viewport_state(struct pipe_context *ctx, - const struct pipe_viewport_state *state) +static void si_set_viewport_states(struct pipe_context *ctx, + unsigned start_slot, + unsigned num_viewports, + const struct pipe_viewport_state *state) { struct r600_context *rctx = (struct r600_context *)ctx; struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); @@ -335,7 +471,11 @@ static void si_update_fb_rs_state(struct r600_context *rctx) return; } - pm4 = CALLOC_STRUCT(si_pm4_state); + pm4 = si_pm4_alloc_state(rctx); + + if (pm4 == NULL) + return; + /* FIXME some of those reg can be computed with cso */ offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, @@ -383,6 +523,9 @@ static void *si_create_rs_state(struct pipe_context *ctx, } rs->two_side = state->light_twoside; + rs->multisample_enable = state->multisample; + rs->clip_plane_enable = state->clip_plane_enable; + rs->line_stipple_enable = state->line_stipple_enable; polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || state->fill_back != PIPE_POLYGON_MODE_FILL); @@ -410,10 +553,8 @@ static void *si_create_rs_state(struct pipe_context *ctx, S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | + S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); - rs->pa_cl_vs_out_cntl = - S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | - S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); clip_rule = state->scissor ? 0xAAAA : 0xFFFF; @@ -455,11 +596,12 @@ static void *si_create_rs_state(struct pipe_context *ctx, tmp = (unsigned)state->line_width * 8; si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, - S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)); + S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | + S_028A48_MSAA_ENABLE(state->multisample)); - si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400); si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, - S_028BE4_PIX_CENTER(state->gl_rasterization_rules)); + S_028BE4_PIX_CENTER(state->half_pixel_center) | + S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH)); si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000); @@ -483,8 +625,6 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state) rctx->sprite_coord_enable = rs->sprite_coord_enable; rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; - rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl; - rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl; si_pm4_bind_state(rctx, rasterizer, rs); si_update_fb_rs_state(rctx); @@ -501,7 +641,7 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state) */ static void si_update_dsa_stencil_ref(struct r600_context *rctx) { - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); struct pipe_stencil_ref *ref = &rctx->stencil_ref; struct si_state_dsa *dsa = rctx->queued.named.dsa; @@ -605,6 +745,9 @@ static void *si_create_dsa_state(struct pipe_context *ctx, if (state->alpha.enabled) { dsa->alpha_func = state->alpha.func; dsa->alpha_ref = state->alpha.ref_value; + + si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + + SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref)); } else { dsa->alpha_func = PIPE_FUNC_ALWAYS; } @@ -627,7 +770,6 @@ static void *si_create_dsa_state(struct pipe_context *ctx, si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); - si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00); dsa->db_render_override = db_render_override; return dsa; @@ -652,19 +794,20 @@ static void si_delete_dsa_state(struct pipe_context *ctx, void *state) } static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth, - bool copy_stencil) + bool copy_stencil, int sample) { struct pipe_depth_stencil_alpha_state dsa; struct si_state_dsa *state; memset(&dsa, 0, sizeof(dsa)); - state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); + state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa); if (copy_depth || copy_stencil) { si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, S_028000_DEPTH_COPY(copy_depth) | S_028000_STENCIL_COPY(copy_stencil) | - S_028000_COPY_CENTROID(1)); + S_028000_COPY_CENTROID(1) | + S_028000_COPY_SAMPLE(sample)); } else { si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, S_028000_DEPTH_COMPRESS_DISABLE(1) | @@ -684,366 +827,124 @@ static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth, */ static uint32_t si_translate_colorformat(enum pipe_format format) { - switch (format) { - /* 8-bit buffers. */ - case PIPE_FORMAT_A8_UNORM: - case PIPE_FORMAT_A8_SNORM: - case PIPE_FORMAT_A8_UINT: - case PIPE_FORMAT_A8_SINT: - case PIPE_FORMAT_I8_UNORM: - case PIPE_FORMAT_I8_SNORM: - case PIPE_FORMAT_I8_UINT: - case PIPE_FORMAT_I8_SINT: - case PIPE_FORMAT_L8_UNORM: - case PIPE_FORMAT_L8_SNORM: - case PIPE_FORMAT_L8_UINT: - case PIPE_FORMAT_L8_SINT: - case PIPE_FORMAT_L8_SRGB: - case PIPE_FORMAT_R8_UNORM: - case PIPE_FORMAT_R8_SNORM: - case PIPE_FORMAT_R8_UINT: - case PIPE_FORMAT_R8_SINT: - return V_028C70_COLOR_8; - - /* 16-bit buffers. */ - case PIPE_FORMAT_B5G6R5_UNORM: - return V_028C70_COLOR_5_6_5; - - case PIPE_FORMAT_B5G5R5A1_UNORM: - case PIPE_FORMAT_B5G5R5X1_UNORM: - return V_028C70_COLOR_1_5_5_5; - - case PIPE_FORMAT_B4G4R4A4_UNORM: - case PIPE_FORMAT_B4G4R4X4_UNORM: - return V_028C70_COLOR_4_4_4_4; - - case PIPE_FORMAT_L8A8_UNORM: - case PIPE_FORMAT_L8A8_SNORM: - case PIPE_FORMAT_L8A8_UINT: - case PIPE_FORMAT_L8A8_SINT: - case PIPE_FORMAT_R8G8_SNORM: - case PIPE_FORMAT_R8G8_UNORM: - case PIPE_FORMAT_R8G8_UINT: - case PIPE_FORMAT_R8G8_SINT: - return V_028C70_COLOR_8_8; + const struct util_format_description *desc = util_format_description(format); - case PIPE_FORMAT_Z16_UNORM: - case PIPE_FORMAT_R16_UNORM: - case PIPE_FORMAT_R16_SNORM: - case PIPE_FORMAT_R16_UINT: - case PIPE_FORMAT_R16_SINT: - case PIPE_FORMAT_R16_FLOAT: - case PIPE_FORMAT_L16_UNORM: - case PIPE_FORMAT_L16_SNORM: - case PIPE_FORMAT_L16_FLOAT: - case PIPE_FORMAT_I16_UNORM: - case PIPE_FORMAT_I16_SNORM: - case PIPE_FORMAT_I16_FLOAT: - case PIPE_FORMAT_A16_UNORM: - case PIPE_FORMAT_A16_SNORM: - case PIPE_FORMAT_A16_FLOAT: - return V_028C70_COLOR_16; - - /* 32-bit buffers. */ - case PIPE_FORMAT_A8B8G8R8_SRGB: - case PIPE_FORMAT_A8B8G8R8_UNORM: - case PIPE_FORMAT_A8R8G8B8_UNORM: - case PIPE_FORMAT_B8G8R8A8_SRGB: - case PIPE_FORMAT_B8G8R8A8_UNORM: - case PIPE_FORMAT_B8G8R8X8_UNORM: - case PIPE_FORMAT_R8G8B8A8_SNORM: - case PIPE_FORMAT_R8G8B8A8_UNORM: - case PIPE_FORMAT_R8G8B8X8_UNORM: - case PIPE_FORMAT_R8G8B8X8_SNORM: - case PIPE_FORMAT_R8G8B8X8_SRGB: - case PIPE_FORMAT_R8G8B8X8_UINT: - case PIPE_FORMAT_R8G8B8X8_SINT: - case PIPE_FORMAT_R8SG8SB8UX8U_NORM: - case PIPE_FORMAT_X8B8G8R8_UNORM: - case PIPE_FORMAT_X8R8G8B8_UNORM: - case PIPE_FORMAT_R8G8B8A8_SSCALED: - case PIPE_FORMAT_R8G8B8A8_USCALED: - case PIPE_FORMAT_R8G8B8A8_SINT: - case PIPE_FORMAT_R8G8B8A8_UINT: - return V_028C70_COLOR_8_8_8_8; - - case PIPE_FORMAT_R10G10B10A2_UNORM: - case PIPE_FORMAT_R10G10B10X2_SNORM: - case PIPE_FORMAT_B10G10R10A2_UNORM: - case PIPE_FORMAT_B10G10R10A2_UINT: - case PIPE_FORMAT_B10G10R10X2_UNORM: - case PIPE_FORMAT_R10SG10SB10SA2U_NORM: - return V_028C70_COLOR_2_10_10_10; - - case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_UINT: - return V_028C70_COLOR_8_24; +#define HAS_SIZE(x,y,z,w) \ + (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \ + desc->channel[2].size == (z) && desc->channel[3].size == (w)) - case PIPE_FORMAT_S8X24_UINT: - case PIPE_FORMAT_X8Z24_UNORM: - case PIPE_FORMAT_S8_UINT_Z24_UNORM: - return V_028C70_COLOR_24_8; - - case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: - return V_028C70_COLOR_X24_8_32_FLOAT; - - case PIPE_FORMAT_I32_FLOAT: - case PIPE_FORMAT_L32_FLOAT: - case PIPE_FORMAT_R32_FLOAT: - case PIPE_FORMAT_A32_FLOAT: - case PIPE_FORMAT_Z32_FLOAT: - return V_028C70_COLOR_32; - - case PIPE_FORMAT_L16A16_UNORM: - case PIPE_FORMAT_L16A16_SNORM: - case PIPE_FORMAT_L16A16_FLOAT: - case PIPE_FORMAT_R16G16_SSCALED: - case PIPE_FORMAT_R16G16_UNORM: - case PIPE_FORMAT_R16G16_SNORM: - case PIPE_FORMAT_R16G16_UINT: - case PIPE_FORMAT_R16G16_SINT: - case PIPE_FORMAT_R16G16_FLOAT: - return V_028C70_COLOR_16_16; - - case PIPE_FORMAT_R11G11B10_FLOAT: + if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ return V_028C70_COLOR_10_11_11; - /* 64-bit buffers. */ - case PIPE_FORMAT_R16G16B16A16_UINT: - case PIPE_FORMAT_R16G16B16A16_SINT: - case PIPE_FORMAT_R16G16B16A16_USCALED: - case PIPE_FORMAT_R16G16B16A16_SSCALED: - case PIPE_FORMAT_R16G16B16A16_UNORM: - case PIPE_FORMAT_R16G16B16A16_SNORM: - case PIPE_FORMAT_R16G16B16A16_FLOAT: - case PIPE_FORMAT_R16G16B16X16_UNORM: - case PIPE_FORMAT_R16G16B16X16_SNORM: - case PIPE_FORMAT_R16G16B16X16_FLOAT: - case PIPE_FORMAT_R16G16B16X16_UINT: - case PIPE_FORMAT_R16G16B16X16_SINT: - return V_028C70_COLOR_16_16_16_16; - - case PIPE_FORMAT_L32A32_FLOAT: - case PIPE_FORMAT_L32A32_UINT: - case PIPE_FORMAT_L32A32_SINT: - case PIPE_FORMAT_R32G32_FLOAT: - case PIPE_FORMAT_R32G32_USCALED: - case PIPE_FORMAT_R32G32_SSCALED: - case PIPE_FORMAT_R32G32_SINT: - case PIPE_FORMAT_R32G32_UINT: - return V_028C70_COLOR_32_32; - - /* 128-bit buffers. */ - case PIPE_FORMAT_R32G32B32A32_SNORM: - case PIPE_FORMAT_R32G32B32A32_UNORM: - case PIPE_FORMAT_R32G32B32A32_SSCALED: - case PIPE_FORMAT_R32G32B32A32_USCALED: - case PIPE_FORMAT_R32G32B32A32_SINT: - case PIPE_FORMAT_R32G32B32A32_UINT: - case PIPE_FORMAT_R32G32B32A32_FLOAT: - case PIPE_FORMAT_R32G32B32X32_FLOAT: - case PIPE_FORMAT_R32G32B32X32_UINT: - case PIPE_FORMAT_R32G32B32X32_SINT: - return V_028C70_COLOR_32_32_32_32; - - /* YUV buffers. */ - case PIPE_FORMAT_UYVY: - case PIPE_FORMAT_YUYV: - /* 96-bit buffers. */ - case PIPE_FORMAT_R32G32B32_FLOAT: - /* 8-bit buffers. */ - case PIPE_FORMAT_L4A4_UNORM: - case PIPE_FORMAT_R4A4_UNORM: - case PIPE_FORMAT_A4R4_UNORM: - default: - return V_028C70_COLOR_INVALID; /* Unsupported. */ + if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) + return V_028C70_COLOR_INVALID; + + switch (desc->nr_channels) { + case 1: + switch (desc->channel[0].size) { + case 8: + return V_028C70_COLOR_8; + case 16: + return V_028C70_COLOR_16; + case 32: + return V_028C70_COLOR_32; + } + break; + case 2: + if (desc->channel[0].size == desc->channel[1].size) { + switch (desc->channel[0].size) { + case 8: + return V_028C70_COLOR_8_8; + case 16: + return V_028C70_COLOR_16_16; + case 32: + return V_028C70_COLOR_32_32; + } + } else if (HAS_SIZE(8,24,0,0)) { + return V_028C70_COLOR_24_8; + } else if (HAS_SIZE(24,8,0,0)) { + return V_028C70_COLOR_8_24; + } + break; + case 3: + if (HAS_SIZE(5,6,5,0)) { + return V_028C70_COLOR_5_6_5; + } else if (HAS_SIZE(32,8,24,0)) { + return V_028C70_COLOR_X24_8_32_FLOAT; + } + break; + case 4: + if (desc->channel[0].size == desc->channel[1].size && + desc->channel[0].size == desc->channel[2].size && + desc->channel[0].size == desc->channel[3].size) { + switch (desc->channel[0].size) { + case 4: + return V_028C70_COLOR_4_4_4_4; + case 8: + return V_028C70_COLOR_8_8_8_8; + case 16: + return V_028C70_COLOR_16_16_16_16; + case 32: + return V_028C70_COLOR_32_32_32_32; + } + } else if (HAS_SIZE(5,5,5,1)) { + return V_028C70_COLOR_1_5_5_5; + } else if (HAS_SIZE(10,10,10,2)) { + return V_028C70_COLOR_2_10_10_10; + } + break; } + return V_028C70_COLOR_INVALID; } static uint32_t si_translate_colorswap(enum pipe_format format) { - switch (format) { - /* 8-bit buffers. */ - case PIPE_FORMAT_L4A4_UNORM: - case PIPE_FORMAT_A4R4_UNORM: - return V_028C70_SWAP_ALT; - - case PIPE_FORMAT_A8_UNORM: - case PIPE_FORMAT_A8_SNORM: - case PIPE_FORMAT_A8_UINT: - case PIPE_FORMAT_A8_SINT: - case PIPE_FORMAT_R4A4_UNORM: - return V_028C70_SWAP_ALT_REV; - case PIPE_FORMAT_I8_UNORM: - case PIPE_FORMAT_I8_SNORM: - case PIPE_FORMAT_L8_UNORM: - case PIPE_FORMAT_L8_SNORM: - case PIPE_FORMAT_I8_UINT: - case PIPE_FORMAT_I8_SINT: - case PIPE_FORMAT_L8_UINT: - case PIPE_FORMAT_L8_SINT: - case PIPE_FORMAT_L8_SRGB: - case PIPE_FORMAT_R8_UNORM: - case PIPE_FORMAT_R8_SNORM: - case PIPE_FORMAT_R8_UINT: - case PIPE_FORMAT_R8_SINT: - return V_028C70_SWAP_STD; - - /* 16-bit buffers. */ - case PIPE_FORMAT_B5G6R5_UNORM: - return V_028C70_SWAP_STD_REV; - - case PIPE_FORMAT_B5G5R5A1_UNORM: - case PIPE_FORMAT_B5G5R5X1_UNORM: - return V_028C70_SWAP_ALT; - - case PIPE_FORMAT_B4G4R4A4_UNORM: - case PIPE_FORMAT_B4G4R4X4_UNORM: - return V_028C70_SWAP_ALT; - - case PIPE_FORMAT_Z16_UNORM: - return V_028C70_SWAP_STD; - - case PIPE_FORMAT_L8A8_UNORM: - case PIPE_FORMAT_L8A8_SNORM: - case PIPE_FORMAT_L8A8_UINT: - case PIPE_FORMAT_L8A8_SINT: - return V_028C70_SWAP_ALT; - case PIPE_FORMAT_R8G8_SNORM: - case PIPE_FORMAT_R8G8_UNORM: - case PIPE_FORMAT_R8G8_UINT: - case PIPE_FORMAT_R8G8_SINT: - return V_028C70_SWAP_STD; + const struct util_format_description *desc = util_format_description(format); - case PIPE_FORMAT_I16_UNORM: - case PIPE_FORMAT_I16_SNORM: - case PIPE_FORMAT_I16_FLOAT: - case PIPE_FORMAT_L16_UNORM: - case PIPE_FORMAT_L16_SNORM: - case PIPE_FORMAT_L16_FLOAT: - case PIPE_FORMAT_R16_UNORM: - case PIPE_FORMAT_R16_SNORM: - case PIPE_FORMAT_R16_UINT: - case PIPE_FORMAT_R16_SINT: - case PIPE_FORMAT_R16_FLOAT: - return V_028C70_SWAP_STD; +#define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz) - case PIPE_FORMAT_A16_UNORM: - case PIPE_FORMAT_A16_SNORM: - case PIPE_FORMAT_A16_FLOAT: - return V_028C70_SWAP_ALT_REV; - - /* 32-bit buffers. */ - case PIPE_FORMAT_A8B8G8R8_SRGB: - return V_028C70_SWAP_STD_REV; - case PIPE_FORMAT_B8G8R8A8_SRGB: - return V_028C70_SWAP_ALT; - - case PIPE_FORMAT_B8G8R8A8_UNORM: - case PIPE_FORMAT_B8G8R8X8_UNORM: - return V_028C70_SWAP_ALT; - - case PIPE_FORMAT_A8R8G8B8_UNORM: - case PIPE_FORMAT_X8R8G8B8_UNORM: - return V_028C70_SWAP_ALT_REV; - case PIPE_FORMAT_R8G8B8A8_SNORM: - case PIPE_FORMAT_R8G8B8A8_UNORM: - case PIPE_FORMAT_R8G8B8A8_SSCALED: - case PIPE_FORMAT_R8G8B8A8_USCALED: - case PIPE_FORMAT_R8G8B8A8_SINT: - case PIPE_FORMAT_R8G8B8A8_UINT: - case PIPE_FORMAT_R8G8B8X8_UNORM: - case PIPE_FORMAT_R8G8B8X8_SNORM: - case PIPE_FORMAT_R8G8B8X8_SRGB: - case PIPE_FORMAT_R8G8B8X8_UINT: - case PIPE_FORMAT_R8G8B8X8_SINT: + if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ return V_028C70_SWAP_STD; - case PIPE_FORMAT_A8B8G8R8_UNORM: - case PIPE_FORMAT_X8B8G8R8_UNORM: - /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ - return V_028C70_SWAP_STD_REV; - - case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_UINT: - return V_028C70_SWAP_STD; - - case PIPE_FORMAT_S8X24_UINT: - case PIPE_FORMAT_X8Z24_UNORM: - case PIPE_FORMAT_S8_UINT_Z24_UNORM: - return V_028C70_SWAP_STD_REV; - - case PIPE_FORMAT_R10G10B10A2_UNORM: - case PIPE_FORMAT_R10G10B10X2_SNORM: - case PIPE_FORMAT_R10SG10SB10SA2U_NORM: - return V_028C70_SWAP_STD; - - case PIPE_FORMAT_B10G10R10A2_UNORM: - case PIPE_FORMAT_B10G10R10A2_UINT: - case PIPE_FORMAT_B10G10R10X2_UNORM: - return V_028C70_SWAP_ALT; - - case PIPE_FORMAT_R11G11B10_FLOAT: - case PIPE_FORMAT_I32_FLOAT: - case PIPE_FORMAT_L32_FLOAT: - case PIPE_FORMAT_R32_FLOAT: - case PIPE_FORMAT_R32_UINT: - case PIPE_FORMAT_R32_SINT: - case PIPE_FORMAT_Z32_FLOAT: - case PIPE_FORMAT_R16G16_FLOAT: - case PIPE_FORMAT_R16G16_UNORM: - case PIPE_FORMAT_R16G16_SNORM: - case PIPE_FORMAT_R16G16_UINT: - case PIPE_FORMAT_R16G16_SINT: - return V_028C70_SWAP_STD; + if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) + return ~0; - case PIPE_FORMAT_L16A16_UNORM: - case PIPE_FORMAT_L16A16_SNORM: - case PIPE_FORMAT_L16A16_FLOAT: - return V_028C70_SWAP_ALT; - - case PIPE_FORMAT_A32_FLOAT: - return V_028C70_SWAP_ALT_REV; - - /* 64-bit buffers. */ - case PIPE_FORMAT_R32G32_FLOAT: - case PIPE_FORMAT_R32G32_UINT: - case PIPE_FORMAT_R32G32_SINT: - case PIPE_FORMAT_R16G16B16A16_UNORM: - case PIPE_FORMAT_R16G16B16A16_SNORM: - case PIPE_FORMAT_R16G16B16A16_USCALED: - case PIPE_FORMAT_R16G16B16A16_SSCALED: - case PIPE_FORMAT_R16G16B16A16_UINT: - case PIPE_FORMAT_R16G16B16A16_SINT: - case PIPE_FORMAT_R16G16B16A16_FLOAT: - case PIPE_FORMAT_R16G16B16X16_UNORM: - case PIPE_FORMAT_R16G16B16X16_SNORM: - case PIPE_FORMAT_R16G16B16X16_FLOAT: - case PIPE_FORMAT_R16G16B16X16_UINT: - case PIPE_FORMAT_R16G16B16X16_SINT: - case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: - return V_028C70_SWAP_STD; - - case PIPE_FORMAT_L32A32_FLOAT: - case PIPE_FORMAT_L32A32_UINT: - case PIPE_FORMAT_L32A32_SINT: - return V_028C70_SWAP_ALT; - - /* 128-bit buffers. */ - case PIPE_FORMAT_R32G32B32A32_FLOAT: - case PIPE_FORMAT_R32G32B32A32_SNORM: - case PIPE_FORMAT_R32G32B32A32_UNORM: - case PIPE_FORMAT_R32G32B32A32_SSCALED: - case PIPE_FORMAT_R32G32B32A32_USCALED: - case PIPE_FORMAT_R32G32B32A32_SINT: - case PIPE_FORMAT_R32G32B32A32_UINT: - case PIPE_FORMAT_R32G32B32X32_FLOAT: - case PIPE_FORMAT_R32G32B32X32_UINT: - case PIPE_FORMAT_R32G32B32X32_SINT: - return V_028C70_SWAP_STD; - default: - R600_ERR("unsupported colorswap format %d\n", format); - return ~0U; + switch (desc->nr_channels) { + case 1: + if (HAS_SWIZZLE(0,X)) + return V_028C70_SWAP_STD; /* X___ */ + else if (HAS_SWIZZLE(3,X)) + return V_028C70_SWAP_ALT_REV; /* ___X */ + break; + case 2: + if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) || + (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) || + (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y))) + return V_028C70_SWAP_STD; /* XY__ */ + else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) || + (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) || + (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) + return V_028C70_SWAP_STD_REV; /* YX__ */ + else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) + return V_028C70_SWAP_ALT; /* X__Y */ + break; + case 3: + if (HAS_SWIZZLE(0,X)) + return V_028C70_SWAP_STD; /* XYZ */ + else if (HAS_SWIZZLE(0,Z)) + return V_028C70_SWAP_STD_REV; /* ZYX */ + break; + case 4: + /* check the middle channels, the 1st and 4th channel can be NONE */ + if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) + return V_028C70_SWAP_STD; /* XYZW */ + else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) + return V_028C70_SWAP_STD_REV; /* WZYX */ + else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) + return V_028C70_SWAP_ALT; /* ZYXW */ + else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y)) + return V_028C70_SWAP_ALT_REV; /* WXYZ */ + break; } return ~0U; } @@ -1164,6 +1065,8 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, const struct util_format_description *desc, int first_non_void) { + struct r600_screen *rscreen = (struct r600_screen*)screen; + bool enable_s3tc = rscreen->b.info.drm_minor >= 31; boolean uniform = TRUE; int i; @@ -1205,7 +1108,51 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, break; } - /* TODO compressed formats */ + if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { + if (!enable_s3tc) + goto out_unknown; + + switch (format) { + case PIPE_FORMAT_RGTC1_SNORM: + case PIPE_FORMAT_LATC1_SNORM: + case PIPE_FORMAT_RGTC1_UNORM: + case PIPE_FORMAT_LATC1_UNORM: + return V_008F14_IMG_DATA_FORMAT_BC4; + case PIPE_FORMAT_RGTC2_SNORM: + case PIPE_FORMAT_LATC2_SNORM: + case PIPE_FORMAT_RGTC2_UNORM: + case PIPE_FORMAT_LATC2_UNORM: + return V_008F14_IMG_DATA_FORMAT_BC5; + default: + goto out_unknown; + } + } + + if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { + + if (!enable_s3tc) + goto out_unknown; + + if (!util_format_s3tc_enabled) { + goto out_unknown; + } + + switch (format) { + case PIPE_FORMAT_DXT1_RGB: + case PIPE_FORMAT_DXT1_RGBA: + case PIPE_FORMAT_DXT1_SRGB: + case PIPE_FORMAT_DXT1_SRGBA: + return V_008F14_IMG_DATA_FORMAT_BC1; + case PIPE_FORMAT_DXT3_RGBA: + case PIPE_FORMAT_DXT3_SRGBA: + return V_008F14_IMG_DATA_FORMAT_BC2; + case PIPE_FORMAT_DXT5_RGBA: + case PIPE_FORMAT_DXT5_SRGBA: + return V_008F14_IMG_DATA_FORMAT_BC3; + default: + goto out_unknown; + } + } if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { return V_008F14_IMG_DATA_FORMAT_5_9_9_9; @@ -1373,7 +1320,7 @@ static unsigned si_tex_compare(unsigned compare) } } -static unsigned si_tex_dim(unsigned dim) +static unsigned si_tex_dim(unsigned dim, unsigned nr_samples) { switch (dim) { default: @@ -1383,9 +1330,11 @@ static unsigned si_tex_dim(unsigned dim) return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; case PIPE_TEXTURE_2D: case PIPE_TEXTURE_RECT: - return V_008F1C_SQ_RSRC_IMG_2D; + return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : + V_008F1C_SQ_RSRC_IMG_2D; case PIPE_TEXTURE_2D_ARRAY: - return V_008F1C_SQ_RSRC_IMG_2D_ARRAY; + return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : + V_008F1C_SQ_RSRC_IMG_2D_ARRAY; case PIPE_TEXTURE_3D: return V_008F1C_SQ_RSRC_IMG_3D; case PIPE_TEXTURE_CUBE: @@ -1444,7 +1393,12 @@ static uint32_t si_translate_vertexformat(struct pipe_screen *screen, } break; case 32: - if (type != UTIL_FORMAT_TYPE_FLOAT) + /* From the Southern Islands ISA documentation about MTBUF: + * 'Memory reads of data in memory that is 32 or 64 bits do not + * undergo any format conversion.' + */ + if (type != UTIL_FORMAT_TYPE_FLOAT && + !desc->channel[first_non_void].pure_integer) return V_008F0C_BUF_DATA_FORMAT_INVALID; switch (desc->nr_channels) { @@ -1492,6 +1446,7 @@ boolean si_is_format_supported(struct pipe_screen *screen, unsigned sample_count, unsigned usage) { + struct r600_screen *rscreen = (struct r600_screen *)screen; unsigned retval = 0; if (target >= PIPE_MAX_TEXTURE_TYPES) { @@ -1502,9 +1457,19 @@ boolean si_is_format_supported(struct pipe_screen *screen, if (!util_format_is_supported(format, usage)) return FALSE; - /* Multisample */ - if (sample_count > 1) - return FALSE; + if (sample_count > 1) { + if (HAVE_LLVM < 0x0304 || rscreen->b.chip_class != SI) + return FALSE; + + switch (sample_count) { + case 2: + case 4: + case 8: + break; + default: + return FALSE; + } + } if ((usage & PIPE_BIND_SAMPLER_VIEW) && si_is_sampler_format_supported(screen, format)) { @@ -1541,7 +1506,7 @@ boolean si_is_format_supported(struct pipe_screen *screen, return retval == usage; } -static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil) +static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) { unsigned tile_mode_index = 0; @@ -1560,7 +1525,7 @@ static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, const struct pipe_framebuffer_state *state, int cb) { - struct r600_resource_texture *rtex; + struct r600_texture *rtex; struct r600_surface *surf; unsigned level = state->cbufs[cb]->u.tex.level; unsigned pitch, slice; @@ -1574,7 +1539,7 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, unsigned max_comp_size; surf = (struct r600_surface *)state->cbufs[cb]; - rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; + rtex = (struct r600_texture*)state->cbufs[cb]->texture; offset = rtex->surface.level[level].offset; if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { @@ -1655,7 +1620,27 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) | S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1); - offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); + if (rtex->resource.b.b.nr_samples > 1) { + unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples); + + color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | + S_028C74_NUM_FRAGMENTS(log_samples); + + if (rtex->fmask.size) { + color_info |= S_028C70_COMPRESSION(1); + unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); + + /* due to a bug in the hw, FMASK_BANK_HEIGHT must be set on SI too */ + color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index) | + S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); + } + } + + if (rtex->cmask.size) { + color_info |= S_028C70_FAST_CLEAR(1); + } + + offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture); offset >>= 8; /* FIXME handle enabling of CB beyond BASE8 which has different offset */ @@ -1674,6 +1659,25 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info); si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib); + if (rtex->cmask.size) { + si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C, + offset + (rtex->cmask.offset >> 8)); + si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C, + S_028C80_TILE_MAX(rtex->cmask.slice_tile_max)); + } + if (rtex->fmask.size) { + si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C, + offset + (rtex->fmask.offset >> 8)); + si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C, + S_028C88_TILE_MAX(rtex->fmask.slice_tile_max)); + } + + /* set CB_COLOR1_INFO for possible dual-src blending */ + if (state->nr_cbufs == 1) { + assert(cb == 0); + si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info); + } + /* Determine pixel shader export format */ max_comp_size = si_colorformat_max_comp_size(format); if (ntype == V_028C70_NUMBER_SRGB || @@ -1681,16 +1685,21 @@ static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, max_comp_size <= 10) || (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) { rctx->export_16bpc |= 1 << cb; + /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */ + if (state->nr_cbufs == 1) + rctx->export_16bpc |= 1 << 1; } } static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, const struct pipe_framebuffer_state *state) { - struct r600_resource_texture *rtex; + struct r600_screen *rscreen = rctx->screen; + struct r600_texture *rtex; struct r600_surface *surf; - unsigned level, pitch, slice, format, tile_mode_index; - uint32_t z_info, s_info; + unsigned level, pitch, slice, format, tile_mode_index, array_mode; + unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config; + uint32_t z_info, s_info, db_depth_info; uint64_t z_offs, s_offs; if (state->zsbuf == NULL) { @@ -1701,16 +1710,16 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, surf = (struct r600_surface *)state->zsbuf; level = surf->base.u.tex.level; - rtex = (struct r600_resource_texture*)surf->base.texture; + rtex = (struct r600_texture*)surf->base.texture; - format = si_translate_dbformat(rtex->real_format); + format = si_translate_dbformat(rtex->resource.b.b.format); if (format == V_028040_Z_INVALID) { - R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format); + R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format); } assert(format != V_028040_Z_INVALID); - s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture); + s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture); z_offs += rtex->surface.level[level].offset; s_offs += rtex->surface.stencil_level[level].offset; @@ -1723,22 +1732,64 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, slice = slice - 1; } + db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1); + z_info = S_028040_FORMAT(format); + if (rtex->resource.b.b.nr_samples > 1) { + z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); + } + if (rtex->surface.flags & RADEON_SURF_SBUFFER) s_info = S_028044_FORMAT(V_028044_STENCIL_8); else s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); - tile_mode_index = si_tile_mode_index(rtex, level, false); - z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); - tile_mode_index = si_tile_mode_index(rtex, level, true); - s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); + if (rctx->b.chip_class >= CIK) { + switch (rtex->surface.level[level].mode) { + case RADEON_SURF_MODE_2D: + array_mode = V_02803C_ARRAY_2D_TILED_THIN1; + break; + case RADEON_SURF_MODE_1D: + case RADEON_SURF_MODE_LINEAR_ALIGNED: + case RADEON_SURF_MODE_LINEAR: + default: + array_mode = V_02803C_ARRAY_1D_TILED_THIN1; + break; + } + tile_split = rtex->surface.tile_split; + stile_split = rtex->surface.stencil_tile_split; + macro_aspect = rtex->surface.mtilea; + bankw = rtex->surface.bankw; + bankh = rtex->surface.bankh; + tile_split = cik_tile_split(tile_split); + stile_split = cik_tile_split(stile_split); + macro_aspect = cik_macro_tile_aspect(macro_aspect); + bankw = cik_bank_wh(bankw); + bankh = cik_bank_wh(bankh); + nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks); + pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes, + rscreen->b.info.r600_num_backends); + + db_depth_info |= S_02803C_ARRAY_MODE(array_mode) | + S_02803C_PIPE_CONFIG(pipe_config) | + S_02803C_BANK_WIDTH(bankw) | + S_02803C_BANK_HEIGHT(bankh) | + S_02803C_MACRO_TILE_ASPECT(macro_aspect) | + S_02803C_NUM_BANKS(nbanks); + z_info |= S_028040_TILE_SPLIT(tile_split); + s_info |= S_028044_TILE_SPLIT(stile_split); + } else { + tile_mode_index = si_tile_mode_index(rtex, level, false); + z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); + tile_mode_index = si_tile_mode_index(rtex, level, true); + s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); + } si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) | S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer)); - si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, S_02803C_ADDR5_SWIZZLE_MASK(1)); + si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info); si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info); si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info); @@ -1752,36 +1803,240 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice)); } +#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \ + (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \ + (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \ + (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \ + (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28)) + +/* 2xMSAA + * There are two locations (-4, 4), (4, -4). */ +static uint32_t sample_locs_2x[] = { + FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), + FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), + FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), + FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), +}; +static unsigned max_dist_2x = 4; +/* 4xMSAA + * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */ +static uint32_t sample_locs_4x[] = { + FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), + FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), + FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), + FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), +}; +static unsigned max_dist_4x = 6; +/* Cayman/SI 8xMSAA */ +static uint32_t cm_sample_locs_8x[] = { + FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), + FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), + FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), + FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), + FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), + FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), + FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), + FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), +}; +static unsigned cm_max_dist_8x = 8; +/* Cayman/SI 16xMSAA */ +static uint32_t cm_sample_locs_16x[] = { + FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), + FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), + FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), + FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), + FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), + FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), + FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), + FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), + FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), + FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), + FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), + FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), + FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), + FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), + FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), + FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), +}; +static unsigned cm_max_dist_16x = 8; + +static void si_get_sample_position(struct pipe_context *ctx, + unsigned sample_count, + unsigned sample_index, + float *out_value) +{ + int offset, index; + struct { + int idx:4; + } val; + switch (sample_count) { + case 1: + default: + out_value[0] = out_value[1] = 0.5; + break; + case 2: + offset = 4 * (sample_index * 2); + val.idx = (sample_locs_2x[0] >> offset) & 0xf; + out_value[0] = (float)(val.idx + 8) / 16.0f; + val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf; + out_value[1] = (float)(val.idx + 8) / 16.0f; + break; + case 4: + offset = 4 * (sample_index * 2); + val.idx = (sample_locs_4x[0] >> offset) & 0xf; + out_value[0] = (float)(val.idx + 8) / 16.0f; + val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf; + out_value[1] = (float)(val.idx + 8) / 16.0f; + break; + case 8: + offset = 4 * (sample_index % 4 * 2); + index = (sample_index / 4) * 4; + val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf; + out_value[0] = (float)(val.idx + 8) / 16.0f; + val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf; + out_value[1] = (float)(val.idx + 8) / 16.0f; + break; + case 16: + offset = 4 * (sample_index % 4 * 2); + index = (sample_index / 4) * 4; + val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf; + out_value[0] = (float)(val.idx + 8) / 16.0f; + val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf; + out_value[1] = (float)(val.idx + 8) / 16.0f; + break; + } +} + +static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples) +{ + unsigned max_dist = 0; + + switch (nr_samples) { + default: + nr_samples = 0; + break; + case 2: + si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]); + si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]); + si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]); + si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]); + max_dist = max_dist_2x; + break; + case 4: + si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]); + si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]); + si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]); + si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]); + max_dist = max_dist_4x; + break; + case 8: + si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]); + si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]); + si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0); + si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0); + si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]); + si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]); + si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0); + si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0); + si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]); + si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]); + si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0); + si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0); + si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]); + si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]); + max_dist = cm_max_dist_8x; + break; + case 16: + si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]); + si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]); + si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]); + si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]); + si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]); + si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]); + si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]); + si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]); + si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]); + si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]); + si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]); + si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]); + si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]); + si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]); + si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]); + si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]); + max_dist = cm_max_dist_16x; + break; + } + + if (nr_samples > 1) { + unsigned log_samples = util_logbase2(nr_samples); + + si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, + S_028BDC_LAST_PIXEL(1) | + S_028BDC_EXPAND_LINE_WIDTH(1)); + si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, + S_028BE0_MSAA_NUM_SAMPLES(log_samples) | + S_028BE0_MAX_SAMPLE_DIST(max_dist) | + S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); + + si_pm4_set_reg(pm4, R_028804_DB_EQAA, + S_028804_MAX_ANCHOR_SAMPLES(log_samples) | + S_028804_PS_ITER_SAMPLES(log_samples) | + S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | + S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) | + S_028804_HIGH_QUALITY_INTERSECTIONS(1) | + S_028804_STATIC_ANCHOR_ASSOCIATIONS(1)); + } else { + si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1)); + si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0); + + si_pm4_set_reg(pm4, R_028804_DB_EQAA, + S_028804_HIGH_QUALITY_INTERSECTIONS(1) | + S_028804_STATIC_ANCHOR_ASSOCIATIONS(1)); + } +} + static void si_set_framebuffer_state(struct pipe_context *ctx, const struct pipe_framebuffer_state *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - uint32_t shader_mask, tl, br; - int tl_x, tl_y, br_x, br_y; + struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); + uint32_t tl, br; + int tl_x, tl_y, br_x, br_y, nr_samples, i; if (pm4 == NULL) return; - si_pm4_inval_fb_cache(pm4, state->nr_cbufs); - - if (state->zsbuf) - si_pm4_inval_zsbuf_cache(pm4); + if (rctx->framebuffer.nr_cbufs) { + rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | + R600_CONTEXT_FLUSH_AND_INV_CB_META; + } + if (rctx->framebuffer.zsbuf) { + rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB; + } util_copy_framebuffer_state(&rctx->framebuffer, state); /* build states */ rctx->export_16bpc = 0; - for (int i = 0; i < state->nr_cbufs; i++) { + rctx->fb_compressed_cb_mask = 0; + for (i = 0; i < state->nr_cbufs; i++) { + struct r600_texture *rtex = + (struct r600_texture*)state->cbufs[i]->texture; + si_cb(rctx, pm4, state, i); + + if (rtex->fmask.size || rtex->cmask.size) { + rctx->fb_compressed_cb_mask |= 1 << i; + } + } + for (; i < 8; i++) { + si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C, + S_028C70_FORMAT(V_028C70_COLOR_INVALID)); } + assert(!(rctx->export_16bpc & ~0xff)); si_db(rctx, pm4, state); - shader_mask = 0; - for (int i = 0; i < state->nr_cbufs; i++) { - shader_mask |= 0xf << (i * 4); - } tl_x = 0; tl_y = 0; br_x = state->width; @@ -1800,8 +2055,18 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br); si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000); si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); - si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask); - si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000); + + if (state->nr_cbufs) + nr_samples = state->cbufs[0]->texture->nr_samples; + else if (state->zsbuf) + nr_samples = state->zsbuf->texture->nr_samples; + else + nr_samples = 0; + + si_set_msaa_state(rctx, pm4, nr_samples); + rctx->fb_log_samples = util_logbase2(nr_samples); + rctx->fb_cb0_is_integer = state->nr_cbufs && + util_format_is_pure_integer(state->cbufs[0]->format); si_pm4_set_state(rctx, framebuffer, pm4); si_update_fb_rs_state(rctx); @@ -1828,17 +2093,33 @@ static INLINE void si_shader_selector_key(struct pipe_context *ctx, for (i = 0; i < rctx->vertex_elements->count; ++i) key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor; + if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0) + key->vs.ucps_enabled |= 0x2; + if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf) + key->vs.ucps_enabled |= 0x1; } else if (sel->type == PIPE_SHADER_FRAGMENT) { if (sel->fs_write_all) key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs; key->ps.export_16bpc = rctx->export_16bpc; + if (rctx->queued.named.rasterizer) { key->ps.color_two_side = rctx->queued.named.rasterizer->two_side; key->ps.flatshade = rctx->queued.named.rasterizer->flatshade; + + if (rctx->queued.named.blend) { + key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one && + rctx->queued.named.rasterizer->multisample_enable && + !rctx->fb_cb0_is_integer; + } } if (rctx->queued.named.dsa) { key->ps.alpha_func = rctx->queued.named.dsa->alpha_func; - key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref; + + /* Alpha-test should be disabled if colorbuffer 0 is integer. */ + if (rctx->framebuffer.nr_cbufs && + rctx->framebuffer.cbufs[0] && + util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format)) + key->ps.alpha_func = PIPE_FUNC_ALWAYS; } else { key->ps.alpha_func = PIPE_FUNC_ALWAYS; } @@ -1958,10 +2239,14 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state) rctx->vs_shader = sel; - if (sel && sel->current) + if (sel && sel->current) { si_pm4_bind_state(rctx, vs, sel->current->pm4); - else + rctx->b.streamout.stride_in_dw = sel->so.stride; + } else { si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4); + } + + rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE; } static void si_bind_ps_shader(struct pipe_context *ctx, void *state) @@ -1978,6 +2263,8 @@ static void si_bind_ps_shader(struct pipe_context *ctx, void *state) si_pm4_bind_state(rctx, ps, sel->current->pm4); else si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4); + + rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE; } static void si_delete_shader_selector(struct pipe_context *ctx, @@ -2031,7 +2318,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx const struct pipe_sampler_view *state) { struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); - struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; + struct r600_texture *tmp = (struct r600_texture*)texture; const struct util_format_description *desc; unsigned format, num_format; uint32_t pitch = 0; @@ -2109,7 +2396,27 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx break; default: if (first_non_void < 0) { - num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; + if (util_format_is_compressed(pipe_format)) { + switch (pipe_format) { + case PIPE_FORMAT_DXT1_SRGB: + case PIPE_FORMAT_DXT1_SRGBA: + case PIPE_FORMAT_DXT3_SRGBA: + case PIPE_FORMAT_DXT5_SRGBA: + num_format = V_008F14_IMG_NUM_FORMAT_SRGB; + break; + case PIPE_FORMAT_RGTC1_SNORM: + case PIPE_FORMAT_LATC1_SNORM: + case PIPE_FORMAT_RGTC2_SNORM: + case PIPE_FORMAT_LATC2_SNORM: + num_format = V_008F14_IMG_NUM_FORMAT_SNORM; + break; + default: + num_format = V_008F14_IMG_NUM_FORMAT_UNORM; + break; + } + } else { + num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; + } } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) { num_format = V_008F14_IMG_NUM_FORMAT_SRGB; } else { @@ -2162,6 +2469,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx va = r600_resource_va(ctx->screen, texture); va += surflevel[0].offset; + va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size; view->state[0] = va >> 8; view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | S_008F14_DATA_FORMAT(format) | @@ -2172,17 +2480,60 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | - S_008F1C_BASE_LEVEL(state->u.tex.first_level) | - S_008F1C_LAST_LEVEL(state->u.tex.last_level) | + S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ? + 0 : state->u.tex.first_level - tmp->mipmap_shift) | + S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ? + util_logbase2(texture->nr_samples) : + state->u.tex.last_level - tmp->mipmap_shift) | S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) | S_008F1C_POW2_PAD(texture->last_level > 0) | - S_008F1C_TYPE(si_tex_dim(texture->target))); + S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples))); view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | S_008F24_LAST_ARRAY(state->u.tex.last_layer)); view->state[6] = 0; view->state[7] = 0; + /* Initialize the sampler view for FMASK. */ + if (tmp->fmask.size) { + uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset; + uint32_t fmask_format; + + switch (texture->nr_samples) { + case 2: + fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2; + break; + case 4: + fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4; + break; + case 8: + fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8; + break; + default: + assert(0); + fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID; + } + + view->fmask_state[0] = va >> 8; + view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | + S_008F14_DATA_FORMAT(fmask_format) | + S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT); + view->fmask_state[2] = S_008F18_WIDTH(width - 1) | + S_008F18_HEIGHT(height - 1); + view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | + S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | + S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | + S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) | + S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) | + S_008F1C_TYPE(si_tex_dim(texture->target, 0)); + view->fmask_state[4] = S_008F20_DEPTH(depth - 1) | + S_008F20_PITCH(tmp->fmask.pitch - 1); + view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) | + S_008F24_LAST_ARRAY(state->u.tex.last_layer); + view->fmask_state[6] = 0; + view->fmask_state[7] = 0; + } + return &view->base; } @@ -2195,11 +2546,31 @@ static void si_sampler_view_destroy(struct pipe_context *ctx, FREE(resource); } +static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter) +{ + return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || + wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER || + (linear_filter && + (wrap == PIPE_TEX_WRAP_CLAMP || + wrap == PIPE_TEX_WRAP_MIRROR_CLAMP)); +} + +static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state) +{ + bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST || + state->mag_img_filter != PIPE_TEX_FILTER_NEAREST; + + return (state->border_color.ui[0] || state->border_color.ui[1] || + state->border_color.ui[2] || state->border_color.ui[3]) && + (wrap_mode_uses_border_color(state->wrap_s, linear_filter) || + wrap_mode_uses_border_color(state->wrap_t, linear_filter) || + wrap_mode_uses_border_color(state->wrap_r, linear_filter)); +} + static void *si_create_sampler_state(struct pipe_context *ctx, const struct pipe_sampler_state *state) { struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); - union util_color uc; unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; unsigned border_color_type; @@ -2207,20 +2578,10 @@ static void *si_create_sampler_state(struct pipe_context *ctx, return NULL; } - util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc); - switch (uc.ui) { - case 0x000000FF: - border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; - break; - case 0x00000000: - border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; - break; - case 0xFFFFFFFF: - border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; - break; - default: /* Use border color pointer */ + if (sampler_state_needs_border_color(state)) border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; - } + else + border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | @@ -2239,102 +2600,89 @@ static void *si_create_sampler_state(struct pipe_context *ctx, rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { - memcpy(rstate->border_color, state->border_color.f, + memcpy(rstate->border_color, state->border_color.ui, sizeof(rstate->border_color)); } return rstate; } -static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx, - unsigned count, - struct pipe_sampler_view **views, - struct r600_textures_info *samplers, - unsigned user_data_reg) +/* XXX consider moving this function to si_descriptors.c for gcc to inline + * the si_set_sampler_view calls. LTO might help too. */ +static void si_set_sampler_views(struct pipe_context *ctx, + unsigned shader, unsigned start, + unsigned count, + struct pipe_sampler_view **views) { - struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - int i, j; + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_textures_info *samplers = &rctx->samplers[shader]; + struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views; + int i; - if (!count) - goto out; + if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT) + return; - si_pm4_inval_texture_cache(pm4); + assert(start == 0); - si_pm4_sh_data_begin(pm4); for (i = 0; i < count; i++) { - pipe_sampler_view_reference( - (struct pipe_sampler_view **)&samplers->views[i], - views[i]); - if (views[i]) { - struct r600_resource_texture *rtex = - (struct r600_resource_texture*)views[i]->texture; + struct r600_texture *rtex = + (struct r600_texture*)views[i]->texture; if (rtex->is_depth && !rtex->is_flushing_texture) { samplers->depth_texture_mask |= 1 << i; } else { samplers->depth_texture_mask &= ~(1 << i); } + if (rtex->cmask.size || rtex->fmask.size) { + samplers->compressed_colortex_mask |= 1 << i; + } else { + samplers->compressed_colortex_mask &= ~(1 << i); + } + + si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state); - si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ); + if (rtex->fmask.size) { + si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i, + views[i], rviews[i]->fmask_state); + } else { + si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i, + NULL, NULL); + } } else { samplers->depth_texture_mask &= ~(1 << i); - } - - for (j = 0; j < Elements(resource[i]->state); ++j) { - si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0); + samplers->compressed_colortex_mask &= ~(1 << i); + si_set_sampler_view(rctx, shader, i, NULL, NULL); + si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i, + NULL, NULL); } } - - for (i = count; i < NUM_TEX_UNITS; i++) { - if (samplers->views[i]) - pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL); + for (; i < samplers->n_views; i++) { + samplers->depth_texture_mask &= ~(1 << i); + samplers->compressed_colortex_mask &= ~(1 << i); + si_set_sampler_view(rctx, shader, i, NULL, NULL); + si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i, + NULL, NULL); } - si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE); - -out: - rctx->ps_samplers.n_views = count; - return pm4; -} - -static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, - struct pipe_sampler_view **views) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct si_pm4_state *pm4; - - pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers, - R_00B130_SPI_SHADER_USER_DATA_VS_0); - si_pm4_set_state(rctx, vs_sampler_views, pm4); + samplers->n_views = count; + rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; } -static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, - struct pipe_sampler_view **views) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct si_pm4_state *pm4; - - pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers, - R_00B030_SPI_SHADER_USER_DATA_PS_0); - si_pm4_set_state(rctx, ps_sampler_views, pm4); -} - -static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count, - void **states, - struct r600_textures_info *samplers, - unsigned user_data_reg) +static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count, + void **states, + struct r600_textures_info *samplers, + unsigned user_data_reg) { struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); uint32_t *border_color_table = NULL; int i, j; if (!count) goto out; - si_pm4_inval_texture_cache(pm4); + rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; si_pm4_sh_data_begin(pm4); for (i = 0; i < count; i++) { @@ -2344,29 +2692,26 @@ static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned if (!rctx->border_color_table || ((rctx->border_color_offset + count - i) & C_008F3C_BORDER_COLOR_PTR)) { - si_resource_reference(&rctx->border_color_table, NULL); + r600_resource_reference(&rctx->border_color_table, NULL); rctx->border_color_offset = 0; rctx->border_color_table = - si_resource_create_custom(&rctx->screen->screen, + r600_resource_create_custom(&rctx->screen->b.b, PIPE_USAGE_STAGING, 4096 * 4 * 4); } if (!border_color_table) { border_color_table = - rctx->ws->buffer_map(rctx->border_color_table->cs_buf, - rctx->cs, + rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf, + rctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED); } for (j = 0; j < 4; j++) { - union fi border_color; - - border_color.f = rstates[i]->border_color[j]; border_color_table[4 * rctx->border_color_offset + j] = - util_le32_to_cpu(border_color.i); + util_le32_to_cpu(rstates[i]->border_color[j]); } rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR; @@ -2381,11 +2726,13 @@ static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned if (border_color_table) { uint64_t va_offset = - r600_resource_va(&rctx->screen->screen, + r600_resource_va(&rctx->screen->b.b, (void*)rctx->border_color_table); si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); - rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf); + if (rctx->b.chip_class >= CIK) + si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40); + rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf); si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ); } @@ -2396,97 +2743,65 @@ out: return pm4; } -static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) +static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states) { struct r600_context *rctx = (struct r600_context *)ctx; struct si_pm4_state *pm4; - pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers, + pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX], R_00B130_SPI_SHADER_USER_DATA_VS_0); si_pm4_set_state(rctx, vs_sampler, pm4); } -static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) +static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states) { struct r600_context *rctx = (struct r600_context *)ctx; struct si_pm4_state *pm4; - pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers, + pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT], R_00B030_SPI_SHADER_USER_DATA_PS_0); si_pm4_set_state(rctx, ps_sampler, pm4); } -static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) -{ -} -static void si_delete_sampler_state(struct pipe_context *ctx, void *state) +static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader, + unsigned start, unsigned count, + void **states) { - free(state); -} + assert(start == 0); -/* - * Constants - */ -static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, - struct pipe_constant_buffer *cb) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL; - struct si_pm4_state *pm4; - uint32_t offset; - uint64_t va; - - /* Note that the state tracker can unbind constant buffers by - * passing NULL here. - */ - if (cb == NULL || (!cb->buffer && !cb->user_buffer)) - return; - - pm4 = CALLOC_STRUCT(si_pm4_state); - si_pm4_inval_shader_cache(pm4); + switch (shader) { + case PIPE_SHADER_VERTEX: + si_bind_vs_sampler_states(ctx, count, states); + break; + case PIPE_SHADER_FRAGMENT: + si_bind_ps_sampler_states(ctx, count, states); + break; + default: + ; + } +} - if (cb->user_buffer) - r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset); - else - offset = 0; - va = r600_resource_va(ctx->screen, (void*)rbuffer); - va += offset; - si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); - si_pm4_sh_data_begin(pm4); +static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); + uint16_t mask = sample_mask; - /* Fill in a T# buffer resource description */ - si_pm4_sh_data_add(pm4, va); - si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) | - S_008F04_STRIDE(0))); - si_pm4_sh_data_add(pm4, cb->buffer_size); - si_pm4_sh_data_add(pm4, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | - S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | - S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | - S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | - S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | - S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32)); - - switch (shader) { - case PIPE_SHADER_VERTEX: - si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_CONST); - si_pm4_set_state(rctx, vs_const, pm4); - break; + if (pm4 == NULL) + return; - case PIPE_SHADER_FRAGMENT: - si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_CONST); - si_pm4_set_state(rctx, ps_const, pm4); - break; + si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16)); + si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16)); - default: - R600_ERR("unsupported %d\n", shader); - FREE(pm4); - } + si_pm4_set_state(rctx, sample_mask, pm4); +} - if (cb->buffer != &rbuffer->b.b) - si_resource_reference(&rbuffer, NULL); +static void si_delete_sampler_state(struct pipe_context *ctx, void *state) +{ + free(state); } /* @@ -2601,79 +2916,141 @@ static void si_set_polygon_stipple(struct pipe_context *ctx, static void si_texture_barrier(struct pipe_context *ctx) { struct r600_context *rctx = (struct r600_context *)ctx; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - si_pm4_inval_texture_cache(pm4); - si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs); - si_pm4_set_state(rctx, texture_barrier, pm4); + rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE | + R600_CONTEXT_FLUSH_AND_INV_CB; +} + +static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode) +{ + struct pipe_blend_state blend; + + memset(&blend, 0, sizeof(blend)); + blend.independent_blend_enable = true; + blend.rt[0].colormask = 0xf; + return si_create_blend_state_mode(&rctx->b.b, &blend, mode); +} + +static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, + struct pipe_resource *texture, + const struct pipe_surface *surf_tmpl) +{ + struct r600_texture *rtex = (struct r600_texture*)texture; + struct r600_surface *surface = CALLOC_STRUCT(r600_surface); + unsigned level = surf_tmpl->u.tex.level; + + if (surface == NULL) + return NULL; + + assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); + assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); + assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); + + pipe_reference_init(&surface->base.reference, 1); + pipe_resource_reference(&surface->base.texture, texture); + surface->base.context = pipe; + surface->base.format = surf_tmpl->format; + surface->base.width = rtex->surface.level[level].npix_x; + surface->base.height = rtex->surface.level[level].npix_y; + surface->base.texture = texture; + surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; + surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; + surface->base.u.tex.level = level; + + return &surface->base; +} + +static void r600_surface_destroy(struct pipe_context *pipe, + struct pipe_surface *surface) +{ + pipe_resource_reference(&surface->texture, NULL); + FREE(surface); +} + +static boolean si_dma_copy(struct pipe_context *ctx, + struct pipe_resource *dst, + unsigned dst_level, + unsigned dst_x, unsigned dst_y, unsigned dst_z, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box) +{ + /* XXX implement this or share evergreen_dma_blit with r600g */ + return FALSE; } void si_init_state_functions(struct r600_context *rctx) { - rctx->context.create_blend_state = si_create_blend_state; - rctx->context.bind_blend_state = si_bind_blend_state; - rctx->context.delete_blend_state = si_delete_blend_state; - rctx->context.set_blend_color = si_set_blend_color; + int i; - rctx->context.create_rasterizer_state = si_create_rs_state; - rctx->context.bind_rasterizer_state = si_bind_rs_state; - rctx->context.delete_rasterizer_state = si_delete_rs_state; + rctx->b.b.create_blend_state = si_create_blend_state; + rctx->b.b.bind_blend_state = si_bind_blend_state; + rctx->b.b.delete_blend_state = si_delete_blend_state; + rctx->b.b.set_blend_color = si_set_blend_color; - rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state; - rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state; - rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state; - rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true); - rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false); - rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true); - rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false); + rctx->b.b.create_rasterizer_state = si_create_rs_state; + rctx->b.b.bind_rasterizer_state = si_bind_rs_state; + rctx->b.b.delete_rasterizer_state = si_delete_rs_state; - rctx->context.set_clip_state = si_set_clip_state; - rctx->context.set_scissor_state = si_set_scissor_state; - rctx->context.set_viewport_state = si_set_viewport_state; - rctx->context.set_stencil_ref = si_set_pipe_stencil_ref; + rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state; + rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state; + rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state; - rctx->context.set_framebuffer_state = si_set_framebuffer_state; + for (i = 0; i < 8; i++) { + rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i); + rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i); + rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i); + } + rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0); + rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE); + rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS); - rctx->context.create_vs_state = si_create_vs_state; - rctx->context.create_fs_state = si_create_fs_state; - rctx->context.bind_vs_state = si_bind_vs_shader; - rctx->context.bind_fs_state = si_bind_ps_shader; - rctx->context.delete_vs_state = si_delete_vs_shader; - rctx->context.delete_fs_state = si_delete_ps_shader; + rctx->b.b.set_clip_state = si_set_clip_state; + rctx->b.b.set_scissor_states = si_set_scissor_states; + rctx->b.b.set_viewport_states = si_set_viewport_states; + rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref; - rctx->context.create_sampler_state = si_create_sampler_state; - rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler; - rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler; - rctx->context.delete_sampler_state = si_delete_sampler_state; + rctx->b.b.set_framebuffer_state = si_set_framebuffer_state; + rctx->b.b.get_sample_position = si_get_sample_position; - rctx->context.create_sampler_view = si_create_sampler_view; - rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view; - rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view; - rctx->context.sampler_view_destroy = si_sampler_view_destroy; + rctx->b.b.create_vs_state = si_create_vs_state; + rctx->b.b.create_fs_state = si_create_fs_state; + rctx->b.b.bind_vs_state = si_bind_vs_shader; + rctx->b.b.bind_fs_state = si_bind_ps_shader; + rctx->b.b.delete_vs_state = si_delete_vs_shader; + rctx->b.b.delete_fs_state = si_delete_ps_shader; - rctx->context.set_sample_mask = si_set_sample_mask; + rctx->b.b.create_sampler_state = si_create_sampler_state; + rctx->b.b.bind_sampler_states = si_bind_sampler_states; + rctx->b.b.delete_sampler_state = si_delete_sampler_state; - rctx->context.set_constant_buffer = si_set_constant_buffer; + rctx->b.b.create_sampler_view = si_create_sampler_view; + rctx->b.b.set_sampler_views = si_set_sampler_views; + rctx->b.b.sampler_view_destroy = si_sampler_view_destroy; - rctx->context.create_vertex_elements_state = si_create_vertex_elements; - rctx->context.bind_vertex_elements_state = si_bind_vertex_elements; - rctx->context.delete_vertex_elements_state = si_delete_vertex_element; - rctx->context.set_vertex_buffers = si_set_vertex_buffers; - rctx->context.set_index_buffer = si_set_index_buffer; + rctx->b.b.set_sample_mask = si_set_sample_mask; - rctx->context.create_stream_output_target = si_create_so_target; - rctx->context.stream_output_target_destroy = si_so_target_destroy; - rctx->context.set_stream_output_targets = si_set_so_targets; + rctx->b.b.create_vertex_elements_state = si_create_vertex_elements; + rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements; + rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element; + rctx->b.b.set_vertex_buffers = si_set_vertex_buffers; + rctx->b.b.set_index_buffer = si_set_index_buffer; - rctx->context.texture_barrier = si_texture_barrier; - rctx->context.set_polygon_stipple = si_set_polygon_stipple; + rctx->b.b.texture_barrier = si_texture_barrier; + rctx->b.b.set_polygon_stipple = si_set_polygon_stipple; + rctx->b.b.create_surface = r600_create_surface; + rctx->b.b.surface_destroy = r600_surface_destroy; + rctx->b.dma_copy = si_dma_copy; - rctx->context.draw_vbo = si_draw_vbo; + rctx->b.b.draw_vbo = si_draw_vbo; } void si_init_config(struct r600_context *rctx) { - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx); + + if (pm4 == NULL) + return; si_cmd_context_control(pm4); @@ -2694,39 +3071,61 @@ void si_init_config(struct r600_context *rctx) si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0); si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); + si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); - si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, - S_028AA8_SWITCH_ON_EOP(1) | - S_028AA8_PARTIAL_VS_WAVE_ON(1) | - S_028AA8_PRIMGROUP_SIZE(63)); + if (rctx->b.chip_class == SI) { + si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, + S_028AA8_SWITCH_ON_EOP(1) | + S_028AA8_PARTIAL_VS_WAVE_ON(1) | + S_028AA8_PRIMGROUP_SIZE(63)); + } si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); - si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | - S_008A14_CLIP_VTX_REORDER_ENA(1)); + if (rctx->b.chip_class < CIK) + si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | + S_008A14_CLIP_VTX_REORDER_ENA(1)); si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); - si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000); - si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); - switch (rctx->screen->family) { - case CHIP_TAHITI: - case CHIP_PITCAIRN: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a); - break; - case CHIP_VERDE: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a); - break; - case CHIP_OLAND: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082); - break; - default: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); - break; + if (rctx->b.chip_class >= CIK) { + switch (rctx->screen->b.family) { + case CHIP_BONAIRE: + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012); + si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); + break; + case CHIP_KAVERI: + /* XXX todo */ + case CHIP_KABINI: + /* XXX todo */ + default: + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); + si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); + break; + } + } else { + switch (rctx->screen->b.family) { + case CHIP_TAHITI: + case CHIP_PITCAIRN: + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a); + break; + case CHIP_VERDE: + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a); + break; + case CHIP_OLAND: + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082); + break; + case CHIP_HAINAN: + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); + break; + default: + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); + break; + } } si_pm4_set_state(rctx, init, pm4);