X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state.c;h=f698c59d87a8bb7a86fb6b1faa9051644bf87cfc;hb=c12ffb30b4a53eda55ef8f541b760c309c488e66;hp=5de31c03192c51996db702508af60ae4bbf6d056;hpb=4eb0ccf9e7902a0b1c9b691fa37852f31cb2befc;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 5de31c03192..f698c59d87a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -29,24 +29,49 @@ #include "sid.h" #include "radeon/r600_cs.h" +#include "util/u_dual_blend.h" #include "util/u_format.h" #include "util/u_format_s3tc.h" #include "util/u_memory.h" #include "util/u_pstipple.h" -static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem, - void (*emit)(struct si_context *ctx, struct r600_atom *state), - unsigned num_dw) +/* Initialize an external atom (owned by ../radeon). */ +static void +si_init_external_atom(struct si_context *sctx, struct r600_atom *atom, + struct r600_atom **list_elem) +{ + atom->id = list_elem - sctx->atoms.array + 1; + *list_elem = atom; +} + +/* Initialize an atom owned by radeonsi. */ +void si_init_atom(struct si_context *sctx, struct r600_atom *atom, + struct r600_atom **list_elem, + void (*emit_func)(struct si_context *ctx, struct r600_atom *state)) { - atom->emit = (void*)emit; - atom->num_dw = num_dw; - atom->dirty = false; + atom->emit = (void*)emit_func; + atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */ *list_elem = atom; } +unsigned si_array_mode(unsigned mode) +{ + switch (mode) { + case RADEON_SURF_MODE_LINEAR_ALIGNED: + return V_009910_ARRAY_LINEAR_ALIGNED; + case RADEON_SURF_MODE_1D: + return V_009910_ARRAY_1D_TILED_THIN1; + case RADEON_SURF_MODE_2D: + return V_009910_ARRAY_2D_TILED_THIN1; + default: + case RADEON_SURF_MODE_LINEAR: + return V_009910_ARRAY_LINEAR_GENERAL; + } +} + uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex) { - if (sscreen->b.chip_class == CIK && + if (sscreen->b.chip_class >= CIK && sscreen->b.info.cik_macrotile_mode_array_valid) { unsigned index, tileb; @@ -218,27 +243,33 @@ static unsigned si_pack_float_12p4(float x) * - The COLOR1 format isn't INVALID because of possible dual-source blending, * so COLOR1 is enabled pretty much all the time. * So CB_TARGET_MASK is the only register that can disable COLOR1. + * + * Another reason is to avoid a hang with dual source blending. */ -static void si_update_fb_blend_state(struct si_context *sctx) +static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom) { - struct si_pm4_state *pm4; + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; struct si_state_blend *blend = sctx->queued.named.blend; uint32_t mask = 0, i; - if (blend == NULL) - return; - - pm4 = CALLOC_STRUCT(si_pm4_state); - if (pm4 == NULL) - return; - for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) if (sctx->framebuffer.state.cbufs[i]) mask |= 0xf << (4*i); - mask &= blend->cb_target_mask; - si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); - si_pm4_set_state(sctx, fb_blend, pm4); + if (blend) + mask &= blend->cb_target_mask; + + /* Avoid a hang that happens when dual source blending is enabled + * but there is not enough color outputs. This is undefined behavior, + * so disable color writes completely. + * + * Reproducible with Unigine Heaven 4.0 and drirc missing. + */ + if (blend->dual_src_blend && + (sctx->ps_shader->ps_colors_written & 0x3) != 0x3) + mask = 0; + + radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask); } /* @@ -328,6 +359,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx, return NULL; blend->alpha_to_one = state->alpha_to_one; + blend->dual_src_blend = util_blend_state_is_dual(state, 0); if (state->logicop_enable) { color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); @@ -398,7 +430,7 @@ static void si_bind_blend_state(struct pipe_context *ctx, void *state) { struct si_context *sctx = (struct si_context *)ctx; si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state); - si_update_fb_blend_state(sctx); + si_mark_atom_dirty(sctx, &sctx->cb_target_mask); } static void si_delete_blend_state(struct pipe_context *ctx, void *state) @@ -411,17 +443,20 @@ static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state) { struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - if (pm4 == NULL) - return; + if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0) + return; + + sctx->blend_color.state = *state; + si_mark_atom_dirty(sctx, &sctx->blend_color.atom); +} - si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0])); - si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1])); - si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); - si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); +static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; - si_pm4_set_state(sctx, blend_color, pm4); + radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4); + radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4); } /* @@ -432,22 +467,13 @@ static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state) { struct si_context *sctx = (struct si_context *)ctx; - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); struct pipe_constant_buffer cb; - if (pm4 == NULL) + if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0) return; - for (int i = 0; i < 6; i++) { - si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16, - fui(state->ucp[i][0])); - si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16, - fui(state->ucp[i][1])); - si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16, - fui(state->ucp[i][2])); - si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16, - fui(state->ucp[i][3])); - } + sctx->clip_state.state = *state; + si_mark_atom_dirty(sctx, &sctx->clip_state.atom); cb.buffer = NULL; cb.user_buffer = state->ucp; @@ -455,8 +481,14 @@ static void si_set_clip_state(struct pipe_context *ctx, cb.buffer_size = 4*4*8; ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb); pipe_resource_reference(&cb.buffer, NULL); +} - si_pm4_set_state(sctx, clip, pm4); +static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + + radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4); + radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4); } #define SIX_BITS 0x3F @@ -470,18 +502,21 @@ static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) unsigned clipdist_mask = info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask; - r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, + radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) | S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) | S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) | + S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) | S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) | S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize || info->writes_edgeflag || - info->writes_layer) | + info->writes_layer || + info->writes_viewport_index) | + S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) | (sctx->queued.named.rasterizer->clip_plane_enable & clipdist_mask)); - r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, + radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, sctx->queued.named.rasterizer->pa_cl_clip_cntl | (clipdist_mask ? 0 : sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) | @@ -494,20 +529,50 @@ static void si_set_scissor_states(struct pipe_context *ctx, const struct pipe_scissor_state *state) { struct si_context *sctx = (struct si_context *)ctx; - struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor); - struct si_pm4_state *pm4 = &scissor->pm4; + int i; - if (scissor == NULL) + for (i = 0; i < num_scissors; i++) + sctx->scissors.states[start_slot + i] = state[i]; + + sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot; + si_mark_atom_dirty(sctx, &sctx->scissors.atom); +} + +static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + struct pipe_scissor_state *states = sctx->scissors.states; + unsigned mask = sctx->scissors.dirty_mask; + + /* The simple case: Only 1 viewport is active. */ + if (mask & 1 && + !si_get_vs_info(sctx)->writes_viewport_index) { + radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2); + radeon_emit(cs, S_028250_TL_X(states[0].minx) | + S_028250_TL_Y(states[0].miny) | + S_028250_WINDOW_OFFSET_DISABLE(1)); + radeon_emit(cs, S_028254_BR_X(states[0].maxx) | + S_028254_BR_Y(states[0].maxy)); + sctx->scissors.dirty_mask &= ~1; /* clear one bit */ return; + } - scissor->scissor = *state; - si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, - S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) | - S_028250_WINDOW_OFFSET_DISABLE(1)); - si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, - S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy)); + while (mask) { + int start, count, i; - si_pm4_set_state(sctx, scissor, scissor); + u_bit_scan_consecutive_range(&mask, &start, &count); + + radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + + start * 4 * 2, count * 2); + for (i = start; i < start+count; i++) { + radeon_emit(cs, S_028250_TL_X(states[i].minx) | + S_028250_TL_Y(states[i].miny) | + S_028250_WINDOW_OFFSET_DISABLE(1)); + radeon_emit(cs, S_028254_BR_X(states[i].maxx) | + S_028254_BR_Y(states[i].maxy)); + } + } + sctx->scissors.dirty_mask = 0; } static void si_set_viewport_states(struct pipe_context *ctx, @@ -516,68 +581,76 @@ static void si_set_viewport_states(struct pipe_context *ctx, const struct pipe_viewport_state *state) { struct si_context *sctx = (struct si_context *)ctx; - struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); - struct si_pm4_state *pm4 = &viewport->pm4; + int i; + + for (i = 0; i < num_viewports; i++) + sctx->viewports.states[start_slot + i] = state[i]; + + sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot; + si_mark_atom_dirty(sctx, &sctx->viewports.atom); +} - if (viewport == NULL) +static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + struct pipe_viewport_state *states = sctx->viewports.states; + unsigned mask = sctx->viewports.dirty_mask; + + /* The simple case: Only 1 viewport is active. */ + if (mask & 1 && + !si_get_vs_info(sctx)->writes_viewport_index) { + radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6); + radeon_emit(cs, fui(states[0].scale[0])); + radeon_emit(cs, fui(states[0].translate[0])); + radeon_emit(cs, fui(states[0].scale[1])); + radeon_emit(cs, fui(states[0].translate[1])); + radeon_emit(cs, fui(states[0].scale[2])); + radeon_emit(cs, fui(states[0].translate[2])); + sctx->viewports.dirty_mask &= ~1; /* clear one bit */ return; + } - viewport->viewport = *state; - si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); - si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); - si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); - si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); - si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); - si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); + while (mask) { + int start, count, i; - si_pm4_set_state(sctx, viewport, viewport); + u_bit_scan_consecutive_range(&mask, &start, &count); + + radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE + + start * 4 * 6, count * 6); + for (i = start; i < start+count; i++) { + radeon_emit(cs, fui(states[i].scale[0])); + radeon_emit(cs, fui(states[i].translate[0])); + radeon_emit(cs, fui(states[i].scale[1])); + radeon_emit(cs, fui(states[i].translate[1])); + radeon_emit(cs, fui(states[i].scale[2])); + radeon_emit(cs, fui(states[i].translate[2])); + } + } + sctx->viewports.dirty_mask = 0; } /* * inferred state between framebuffer and rasterizer */ -static void si_update_fb_rs_state(struct si_context *sctx) +static void si_update_poly_offset_state(struct si_context *sctx) { struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; - struct si_pm4_state *pm4; - float offset_units; if (!rs || !sctx->framebuffer.state.zsbuf) return; - offset_units = sctx->queued.named.rasterizer->offset_units; switch (sctx->framebuffer.state.zsbuf->texture->format) { - case PIPE_FORMAT_S8_UINT_Z24_UNORM: - case PIPE_FORMAT_X8Z24_UNORM: - case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_UINT: - offset_units *= 2.0f; + case PIPE_FORMAT_Z16_UNORM: + si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]); + break; + default: /* 24-bit */ + si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]); break; case PIPE_FORMAT_Z32_FLOAT: case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: - offset_units *= 1.0f; - break; - case PIPE_FORMAT_Z16_UNORM: - offset_units *= 4.0f; + si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]); break; - default: - return; } - - pm4 = CALLOC_STRUCT(si_pm4_state); - - if (pm4 == NULL) - return; - - /* FIXME some of those reg can be computed with cso */ - si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, - fui(sctx->queued.named.rasterizer->offset_scale)); - si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); - si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, - fui(sctx->queued.named.rasterizer->offset_scale)); - si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); - - si_pm4_set_state(sctx, fb_rs, pm4); } /* @@ -604,8 +677,7 @@ static void *si_create_rs_state(struct pipe_context *ctx, { struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); struct si_pm4_state *pm4 = &rs->pm4; - unsigned tmp; - unsigned prov_vtx = 1, polygon_dual_mode; + unsigned tmp, i; float psize_min, psize_max; if (rs == NULL) { @@ -617,29 +689,14 @@ static void *si_create_rs_state(struct pipe_context *ctx, rs->clip_plane_enable = state->clip_plane_enable; rs->line_stipple_enable = state->line_stipple_enable; rs->poly_stipple_enable = state->poly_stipple_enable; - - polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || - state->fill_back != PIPE_POLYGON_MODE_FILL); - - if (state->flatshade_first) - prov_vtx = 0; + rs->line_smooth = state->line_smooth; + rs->poly_smooth = state->poly_smooth; rs->flatshade = state->flatshade; rs->sprite_coord_enable = state->sprite_coord_enable; rs->pa_sc_line_stipple = state->line_stipple_enable ? S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; - rs->pa_su_sc_mode_cntl = - S_028814_PROVOKING_VTX_LAST(prov_vtx) | - S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | - S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | - S_028814_FACE(!state->front_ccw) | - S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) | - S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) | - S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) | - S_028814_POLY_MODE(polygon_dual_mode) | - S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | - S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); rs->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) | S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) | @@ -648,22 +705,14 @@ static void *si_create_rs_state(struct pipe_context *ctx, S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); - /* offset */ - rs->offset_units = state->offset_units; - rs->offset_scale = state->offset_scale * 12.0f; - - tmp = S_0286D4_FLAT_SHADE_ENA(1); - if (state->sprite_coord_enable) { - tmp |= S_0286D4_PNT_SPRITE_ENA(1) | - S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | - S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | - S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | - S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1); - if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { - tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); - } - } - si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp); + si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, + S_0286D4_FLAT_SHADE_ENA(1) | + S_0286D4_PNT_SPRITE_ENA(1) | + S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | + S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | + S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | + S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) | + S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT)); /* point size 12.4 fixed point */ tmp = (unsigned)(state->point_size * 8.0); @@ -686,7 +735,9 @@ static void *si_create_rs_state(struct pipe_context *ctx, si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | - S_028A48_MSAA_ENABLE(state->multisample) | + S_028A48_MSAA_ENABLE(state->multisample || + state->poly_smooth || + state->line_smooth) | S_028A48_VPORT_SCISSOR_ENABLE(state->scissor)); si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, @@ -694,6 +745,46 @@ static void *si_create_rs_state(struct pipe_context *ctx, S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH)); si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); + si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, + S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) | + S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | + S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | + S_028814_FACE(!state->front_ccw) | + S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) | + S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) | + S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) | + S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL || + state->fill_back != PIPE_POLYGON_MODE_FILL) | + S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | + S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back))); + + /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */ + for (i = 0; i < 3; i++) { + struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i]; + float offset_units = state->offset_units; + float offset_scale = state->offset_scale * 16.0f; + + switch (i) { + case 0: /* 16-bit zbuffer */ + offset_units *= 4.0f; + break; + case 1: /* 24-bit zbuffer */ + offset_units *= 2.0f; + break; + case 2: /* 32-bit zbuffer */ + offset_units *= 1.0f; + break; + } + + si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, + fui(offset_scale)); + si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, + fui(offset_units)); + si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, + fui(offset_scale)); + si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, + fui(offset_units)); + } return rs; } @@ -708,63 +799,55 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state) if (state == NULL) return; - // TODO - sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; - sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; - if (sctx->framebuffer.nr_samples > 1 && (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) - sctx->db_render_state.dirty = true; + si_mark_atom_dirty(sctx, &sctx->db_render_state); si_pm4_bind_state(sctx, rasterizer, rs); - si_update_fb_rs_state(sctx); + si_update_poly_offset_state(sctx); - sctx->clip_regs.dirty = true; - sctx->last_rast_prim = -1; /* reset this so that it gets updated */ + si_mark_atom_dirty(sctx, &sctx->clip_regs); } static void si_delete_rs_state(struct pipe_context *ctx, void *state) { struct si_context *sctx = (struct si_context *)ctx; + + if (sctx->queued.named.rasterizer == state) + si_pm4_bind_state(sctx, poly_offset, NULL); si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state); } /* * infeered state between dsa and stencil ref */ -static void si_update_dsa_stencil_ref(struct si_context *sctx) +static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom) { - struct si_pm4_state *pm4; - struct pipe_stencil_ref *ref = &sctx->stencil_ref; - struct si_state_dsa *dsa = sctx->queued.named.dsa; - - if (!dsa) - return; - - pm4 = CALLOC_STRUCT(si_pm4_state); - if (pm4 == NULL) - return; - - si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK, - S_028430_STENCILTESTVAL(ref->ref_value[0]) | - S_028430_STENCILMASK(dsa->valuemask[0]) | - S_028430_STENCILWRITEMASK(dsa->writemask[0]) | - S_028430_STENCILOPVAL(1)); - si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF, - S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | - S_028434_STENCILMASK_BF(dsa->valuemask[1]) | - S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) | - S_028434_STENCILOPVAL_BF(1)); + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + struct pipe_stencil_ref *ref = &sctx->stencil_ref.state; + struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part; - si_pm4_set_state(sctx, dsa_stencil_ref, pm4); + radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2); + radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) | + S_028430_STENCILMASK(dsa->valuemask[0]) | + S_028430_STENCILWRITEMASK(dsa->writemask[0]) | + S_028430_STENCILOPVAL(1)); + radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | + S_028434_STENCILMASK_BF(dsa->valuemask[1]) | + S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) | + S_028434_STENCILOPVAL_BF(1)); } -static void si_set_pipe_stencil_ref(struct pipe_context *ctx, - const struct pipe_stencil_ref *state) +static void si_set_stencil_ref(struct pipe_context *ctx, + const struct pipe_stencil_ref *state) { struct si_context *sctx = (struct si_context *)ctx; - sctx->stencil_ref = *state; - si_update_dsa_stencil_ref(sctx); + + if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0) + return; + + sctx->stencil_ref.state = *state; + si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom); } @@ -811,14 +894,15 @@ static void *si_create_dsa_state(struct pipe_context *ctx, return NULL; } - dsa->valuemask[0] = state->stencil[0].valuemask; - dsa->valuemask[1] = state->stencil[1].valuemask; - dsa->writemask[0] = state->stencil[0].writemask; - dsa->writemask[1] = state->stencil[1].writemask; + dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask; + dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask; + dsa->stencil_ref.writemask[0] = state->stencil[0].writemask; + dsa->stencil_ref.writemask[1] = state->stencil[1].writemask; db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | - S_028800_ZFUNC(state->depth.func); + S_028800_ZFUNC(state->depth.func) | + S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test); /* stencil */ if (state->stencil[0].enabled) { @@ -847,9 +931,12 @@ static void *si_create_dsa_state(struct pipe_context *ctx, dsa->alpha_func = PIPE_FUNC_ALWAYS; } - /* misc */ si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); + if (state->depth.bounds_test) { + si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min)); + si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max)); + } return dsa; } @@ -863,7 +950,12 @@ static void si_bind_dsa_state(struct pipe_context *ctx, void *state) return; si_pm4_bind_state(sctx, dsa, dsa); - si_update_dsa_stencil_ref(sctx); + + if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part, + sizeof(struct si_dsa_stencil_ref_part)) != 0) { + sctx->stencil_ref.dsa_part = dsa->stencil_ref; + si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom); + } } static void si_delete_dsa_state(struct pipe_context *ctx, void *state) @@ -885,7 +977,7 @@ static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable) { struct si_context *sctx = (struct si_context*)ctx; - sctx->db_render_state.dirty = true; + si_mark_atom_dirty(sctx, &sctx->db_render_state); } static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state) @@ -894,7 +986,7 @@ static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *s struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; unsigned db_shader_control; - r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2); + radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2); /* DB_RENDER_CONTROL */ if (sctx->dbcb_depth_copy_enabled || @@ -939,21 +1031,26 @@ static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *s /* DB_RENDER_OVERRIDE2 */ if (sctx->db_depth_disable_expclear) { - r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, + radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1)); } else { - r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0); + radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0); } - db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) | - S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) | + db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) | sctx->ps_db_shader_control; + /* Bug workaround for smoothing (overrasterization) on SI. */ + if (sctx->b.chip_class == SI && sctx->smoothing_enabled) + db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z); + else + db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); + /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */ if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable)) db_shader_control &= C_02880C_MASK_EXPORT_ENABLE; - r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, + radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, db_shader_control); } @@ -1149,7 +1246,9 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, int first_non_void) { struct si_screen *sscreen = (struct si_screen*)screen; - bool enable_s3tc = sscreen->b.info.drm_minor >= 31; + bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 && + sscreen->b.info.drm_minor >= 31) || + sscreen->b.info.drm_major == 3; boolean uniform = TRUE; int i; @@ -1192,7 +1291,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, } if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { - if (!enable_s3tc) + if (!enable_compressed_formats) goto out_unknown; switch (format) { @@ -1212,7 +1311,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, } if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) { - if (!enable_s3tc) + if (!enable_compressed_formats) goto out_unknown; switch (format) { @@ -1241,8 +1340,7 @@ static uint32_t si_translate_texformat(struct pipe_screen *screen, } if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { - - if (!enable_s3tc) + if (!enable_compressed_formats) goto out_unknown; if (!util_format_s3tc_enabled) { @@ -1598,7 +1696,6 @@ boolean si_is_format_supported(struct pipe_screen *screen, unsigned sample_count, unsigned usage) { - struct si_screen *sscreen = (struct si_screen *)screen; unsigned retval = 0; if (target >= PIPE_MAX_TEXTURE_TYPES) { @@ -1610,8 +1707,7 @@ boolean si_is_format_supported(struct pipe_screen *screen, return FALSE; if (sample_count > 1) { - /* 2D tiling on CIK is supported since DRM 2.35.0 */ - if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35) + if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE)) return FALSE; switch (sample_count) { @@ -1818,6 +1914,9 @@ static void si_initialize_color_surface(struct si_context *sctx, surf->cb_color_info = color_info; surf->cb_color_attrib = color_attrib; + if (sctx->b.chip_class >= VI) + surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1); + if (rtex->fmask.size) { surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8; surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max); @@ -1855,7 +1954,7 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_screen *sscreen = sctx->screen; struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; unsigned level = surf->base.u.tex.level; - struct radeon_surface_level *levelinfo = &rtex->surface.level[level]; + struct radeon_surf_level *levelinfo = &rtex->surface.level[level]; unsigned format, tile_mode_index, array_mode; unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config; uint32_t z_info, s_info, db_depth_info; @@ -1951,12 +2050,6 @@ static void si_init_depth_surface(struct si_context *sctx, z_info |= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1); - /* This is optimal for the clear value of 1.0 and using - * the LESS and LEQUAL test functions. Set this to 0 - * for the opposite case. This can only be changed when - * clearing. */ - z_info |= S_028040_ZRANGE_PRECISION(1); - /* Use all of the htile_buffer for depth, because we don't * use HTILE for stencil because of FAST_STENCIL_DISABLE. */ s_info |= S_028044_TILE_STENCIL_DISABLE(1); @@ -2011,6 +2104,13 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, SI_CONTEXT_INV_TC_L2 | SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER; + /* Take the maximum of the old and new count. If the new count is lower, + * dirtying is needed to disable the unbound colorbuffers. + */ + sctx->framebuffer.dirty_cbufs |= + (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1; + sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf; + util_copy_framebuffer_state(&sctx->framebuffer.state, state); sctx->framebuffer.export_16bpc = 0; @@ -2021,7 +2121,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, util_format_is_pure_integer(state->cbufs[0]->format); if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer) - sctx->db_render_state.dirty = true; + si_mark_atom_dirty(sctx, &sctx->db_render_state); for (i = 0; i < state->nr_cbufs; i++) { if (!state->cbufs[i]) @@ -2041,6 +2141,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (rtex->fmask.size && rtex->cmask.size) { sctx->framebuffer.compressed_cb_mask |= 1 << i; } + r600_context_add_resource_size(ctx, surf->base.texture); } /* Set the 16BPC export for possible dual-src blending. */ if (i == 1 && surf && surf->export_16bpc) { @@ -2055,20 +2156,16 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (!surf->depth_initialized) { si_init_depth_surface(sctx, surf); } + r600_context_add_resource_size(ctx, surf->base.texture); } - si_update_fb_rs_state(sctx); - si_update_fb_blend_state(sctx); - - sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3; - sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4; - sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */ - sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */ - sctx->framebuffer.atom.dirty = true; + si_update_poly_offset_state(sctx); + si_mark_atom_dirty(sctx, &sctx->cb_target_mask); + si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); if (sctx->framebuffer.nr_samples != old_nr_samples) { - sctx->msaa_config.dirty = true; - sctx->db_render_state.dirty = true; + si_mark_atom_dirty(sctx, &sctx->msaa_config); + si_mark_atom_dirty(sctx, &sctx->db_render_state); /* Set sample locations as fragment shader constants. */ switch (sctx->framebuffer.nr_samples) { @@ -2093,6 +2190,19 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4; ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT, SI_DRIVER_STATE_CONST_BUF, &constbuf); + + /* Smoothing (only possible with nr_samples == 1) uses the same + * sample locations as the MSAA it simulates. + * + * Therefore, don't update the sample locations when + * transitioning from no AA to smoothing-equivalent AA, and + * vice versa. + */ + if ((sctx->framebuffer.nr_samples != 1 || + old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) && + (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES || + old_nr_samples != 1)) + si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs); } } @@ -2106,74 +2216,83 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom /* Colorbuffers. */ for (i = 0; i < nr_cbufs; i++) { + if (!(sctx->framebuffer.dirty_cbufs & (1 << i))) + continue; + cb = (struct r600_surface*)state->cbufs[i]; if (!cb) { - r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, + radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, S_028C70_FORMAT(V_028C70_COLOR_INVALID)); continue; } tex = (struct r600_texture *)cb->base.texture; - r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, &tex->resource, RADEON_USAGE_READWRITE, tex->surface.nsamples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER); if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) { - r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, tex->cmask_buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_COLOR_META); } - r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13); + radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, + sctx->b.chip_class >= VI ? 14 : 13); radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */ radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */ radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */ radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */ radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */ radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */ - radeon_emit(cs, 0); /* R_028C78 unused */ + radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */ radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */ radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */ radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */ radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */ + + if (sctx->b.chip_class >= VI) + radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */ } /* set CB_COLOR1_INFO for possible dual-src blending */ - if (i == 1 && state->cbufs[0]) { - r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, + if (i == 1 && state->cbufs[0] && + sctx->framebuffer.dirty_cbufs & (1 << 0)) { + radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, cb->cb_color_info | tex->cb_color_info); i++; } - for (; i < 8 ; i++) { - r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); - } + for (; i < 8 ; i++) + if (sctx->framebuffer.dirty_cbufs & (1 << i)) + radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); /* ZS buffer. */ - if (state->zsbuf) { + if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) { struct r600_surface *zb = (struct r600_surface*)state->zsbuf; struct r600_texture *rtex = (struct r600_texture*)zb->base.texture; - r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, &rtex->resource, RADEON_USAGE_READWRITE, zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA : RADEON_PRIO_DEPTH_BUFFER); if (zb->db_htile_data_base) { - r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META); } - r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); - r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); + radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); + radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); - r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9); + radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9); radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */ - radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */ + radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */ + S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0)); radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */ radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ @@ -2182,34 +2301,44 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */ radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */ - r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface); - r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); - r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, + radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface); + radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); + radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, zb->pa_su_poly_offset_db_fmt_cntl); - } else { - r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); + } else if (sctx->framebuffer.dirty_zsbuf) { + radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */ radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */ } /* Framebuffer dimensions. */ /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */ - r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, + radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, S_028208_BR_X(state->width) | S_028208_BR_Y(state->height)); - cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples); + sctx->framebuffer.dirty_cbufs = 0; + sctx->framebuffer.dirty_zsbuf = false; +} + +static void si_emit_msaa_sample_locs(struct si_context *sctx, + struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + unsigned nr_samples = sctx->framebuffer.nr_samples; + + cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples : + SI_NUM_SMOOTH_AA_SAMPLES); } -static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom) +static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom) { - struct si_context *sctx = (struct si_context *)rctx; struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples, - sctx->ps_iter_samples); + sctx->ps_iter_samples, + sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0); } -const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */ static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples) { @@ -2221,27 +2350,40 @@ static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples) sctx->ps_iter_samples = min_samples; if (sctx->framebuffer.nr_samples > 1) - sctx->msaa_config.dirty = true; + si_mark_atom_dirty(sctx, &sctx->msaa_config); } /* * Samplers */ -static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx, - struct pipe_resource *texture, - const struct pipe_sampler_view *state) +/** + * Create a sampler view. + * + * @param ctx context + * @param texture texture + * @param state sampler view template + * @param width0 width0 override (for compressed textures as int) + * @param height0 height0 override (for compressed textures as int) + * @param force_level set the base address to the level (for compressed textures) + */ +struct pipe_sampler_view * +si_create_sampler_view_custom(struct pipe_context *ctx, + struct pipe_resource *texture, + const struct pipe_sampler_view *state, + unsigned width0, unsigned height0, + unsigned force_level) { struct si_context *sctx = (struct si_context*)ctx; struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view); struct r600_texture *tmp = (struct r600_texture*)texture; const struct util_format_description *desc; - unsigned format, num_format; + unsigned format, num_format, base_level, first_level, last_level; uint32_t pitch = 0; unsigned char state_swizzle[4], swizzle[4]; unsigned height, depth, width; enum pipe_format pipe_format = state->format; - struct radeon_surface_level *surflevel; + struct radeon_surf_level *surflevel; int first_non_void; uint64_t va; @@ -2269,7 +2411,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx /* Buffer resource. */ if (texture->target == PIPE_BUFFER) { - unsigned stride; + unsigned stride, num_records; desc = util_format_description(state->format); first_non_void = util_format_get_first_non_void_channel(state->format); @@ -2278,10 +2420,16 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); + num_records = state->u.buf.last_element + 1 - state->u.buf.first_element; + num_records = MIN2(num_records, texture->width0 / stride); + + if (sctx->b.chip_class >= VI) + num_records *= stride; + view->state[4] = va; view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride); - view->state[6] = state->u.buf.last_element + 1 - state->u.buf.first_element; + view->state[6] = num_records; view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | @@ -2409,13 +2557,25 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx format = 0; } - /* not supported any more */ - //endian = si_colorformat_endian_swap(format); + base_level = 0; + first_level = state->u.tex.first_level; + last_level = state->u.tex.last_level; + width = width0; + height = height0; + depth = texture->depth0; + + if (force_level) { + assert(force_level == first_level && + force_level == last_level); + base_level = force_level; + first_level = 0; + last_level = 0; + width = u_minify(width, force_level); + height = u_minify(height, force_level); + depth = u_minify(depth, force_level); + } - width = surflevel[0].npix_x; - height = surflevel[0].npix_y; - depth = surflevel[0].npix_z; - pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format); + pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format); if (texture->target == PIPE_TEXTURE_1D_ARRAY) { height = 1; @@ -2425,8 +2585,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY) depth = texture->array_size / 6; - va = tmp->resource.gpu_address + surflevel[0].offset; - va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size; + va = tmp->resource.gpu_address + surflevel[base_level].offset; view->state[0] = va >> 8; view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | @@ -2439,11 +2598,11 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ? - 0 : state->u.tex.first_level - tmp->mipmap_shift) | + 0 : first_level) | S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ? util_logbase2(texture->nr_samples) : - state->u.tex.last_level - tmp->mipmap_shift) | - S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) | + last_level) | + S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) | S_008F1C_POW2_PAD(texture->last_level > 0) | S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples))); view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); @@ -2495,6 +2654,16 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx return &view->base; } +static struct pipe_sampler_view * +si_create_sampler_view(struct pipe_context *ctx, + struct pipe_resource *texture, + const struct pipe_sampler_view *state) +{ + return si_create_sampler_view_custom(ctx, texture, state, + texture ? texture->width0 : 0, + texture ? texture->height0 : 0, 0); +} + static void si_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state) { @@ -2531,18 +2700,63 @@ static bool sampler_state_needs_border_color(const struct pipe_sampler_state *st static void *si_create_sampler_state(struct pipe_context *ctx, const struct pipe_sampler_state *state) { + struct si_context *sctx = (struct si_context *)ctx; struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state); unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; - unsigned border_color_type; + unsigned border_color_type, border_color_index = 0; if (rstate == NULL) { return NULL; } - if (sampler_state_needs_border_color(state)) - border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; - else + if (!sampler_state_needs_border_color(state)) border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; + else if (state->border_color.f[0] == 0 && + state->border_color.f[1] == 0 && + state->border_color.f[2] == 0 && + state->border_color.f[3] == 0) + border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; + else if (state->border_color.f[0] == 0 && + state->border_color.f[1] == 0 && + state->border_color.f[2] == 0 && + state->border_color.f[3] == 1) + border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; + else if (state->border_color.f[0] == 1 && + state->border_color.f[1] == 1 && + state->border_color.f[2] == 1 && + state->border_color.f[3] == 1) + border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; + else { + int i; + + border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; + + /* Check if the border has been uploaded already. */ + for (i = 0; i < sctx->border_color_count; i++) + if (memcmp(&sctx->border_color_table[i], &state->border_color, + sizeof(state->border_color)) == 0) + break; + + if (i >= SI_MAX_BORDER_COLORS) { + /* Getting 4096 unique border colors is very unlikely. */ + fprintf(stderr, "radeonsi: The border color table is full. " + "Any new border colors will be just black. " + "Please file a bug.\n"); + border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; + } else { + if (i == sctx->border_color_count) { + /* Upload a new border color. */ + memcpy(&sctx->border_color_table[i], &state->border_color, + sizeof(state->border_color)); + util_memcpy_cpu_to_le32(&sctx->border_color_map[i], + &state->border_color, + sizeof(state->border_color)); + sctx->border_color_count++; + } + + border_color_index = i; + } + } rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | @@ -2557,104 +2771,30 @@ static void *si_create_sampler_state(struct pipe_context *ctx, S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) | S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) | S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); - rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); - - if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { - memcpy(rstate->border_color, state->border_color.ui, - sizeof(rstate->border_color)); - } - + rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) | + S_008F3C_BORDER_COLOR_TYPE(border_color_type); return rstate; } -/* Upload border colors and update the pointers in resource descriptors. - * There can only be 4096 border colors per context. - * - * XXX: This is broken if the buffer gets reallocated. - */ -static void si_set_border_colors(struct si_context *sctx, unsigned count, - void **states) -{ - struct si_sampler_state **rstates = (struct si_sampler_state **)states; - uint32_t *border_color_table = NULL; - int i, j; - - for (i = 0; i < count; i++) { - if (rstates[i] && - G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) == - V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { - if (!sctx->border_color_table || - ((sctx->border_color_offset + count - i) & - C_008F3C_BORDER_COLOR_PTR)) { - r600_resource_reference(&sctx->border_color_table, NULL); - sctx->border_color_offset = 0; - - sctx->border_color_table = - si_resource_create_custom(&sctx->screen->b.b, - PIPE_USAGE_DYNAMIC, - 4096 * 4 * 4); - } - - if (!border_color_table) { - border_color_table = - sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf, - sctx->b.rings.gfx.cs, - PIPE_TRANSFER_WRITE | - PIPE_TRANSFER_UNSYNCHRONIZED); - } - - for (j = 0; j < 4; j++) { - border_color_table[4 * sctx->border_color_offset + j] = - util_le32_to_cpu(rstates[i]->border_color[j]); - } - - rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR; - rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++); - } - } - - if (border_color_table) { - struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - - uint64_t va_offset = sctx->border_color_table->gpu_address; - - si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); - if (sctx->b.chip_class >= CIK) - si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40); - si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ, - RADEON_PRIO_SHADER_DATA); - si_pm4_set_state(sctx, ta_bordercolor_base, pm4); - } -} - -static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader, - unsigned start, unsigned count, - void **states) +static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) { struct si_context *sctx = (struct si_context *)ctx; - if (!count || shader >= SI_NUM_SHADERS) + if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask) return; - si_set_border_colors(sctx, count, states); - si_set_sampler_descriptors(sctx, shader, start, count, states); + sctx->sample_mask.sample_mask = sample_mask; + si_mark_atom_dirty(sctx, &sctx->sample_mask.atom); } -static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) +static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask); - struct si_pm4_state *pm4 = &state->pm4; - uint16_t mask = sample_mask; - - if (state == NULL) - return; - - state->sample_mask = mask; - si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16)); - si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16)); + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + unsigned mask = sctx->sample_mask.sample_mask; - si_pm4_set_state(sctx, sample_mask, state); + radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2); + radeon_emit(cs, mask | (mask << 16)); + radeon_emit(cs, mask | (mask << 16)); } static void si_delete_sampler_state(struct pipe_context *ctx, void *state) @@ -2673,7 +2813,7 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); int i; - assert(count < PIPE_MAX_ATTRIBS); + assert(count < SI_MAX_ATTRIBS); if (!v) return NULL; @@ -2737,6 +2877,7 @@ static void si_set_vertex_buffers(struct pipe_context *ctx, pipe_resource_reference(&dsti->buffer, src->buffer); dsti->buffer_offset = src->buffer_offset; dsti->stride = src->stride; + r600_context_add_resource_size(ctx, src->buffer); } } else { for (i = 0; i < count; i++) { @@ -2754,6 +2895,7 @@ static void si_set_index_buffer(struct pipe_context *ctx, if (ib) { pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer); memcpy(&sctx->index_buffer, ib, sizeof(*ib)); + r600_context_add_resource_size(ctx, ib->buffer); } else { pipe_resource_reference(&sctx->index_buffer.buffer, NULL); } @@ -2817,6 +2959,30 @@ static void si_set_polygon_stipple(struct pipe_context *ctx, } } +static void si_set_tess_state(struct pipe_context *ctx, + const float default_outer_level[4], + const float default_inner_level[2]) +{ + struct si_context *sctx = (struct si_context *)ctx; + struct pipe_constant_buffer cb; + float array[8]; + + memcpy(array, default_outer_level, sizeof(float) * 4); + memcpy(array+4, default_inner_level, sizeof(float) * 2); + + cb.buffer = NULL; + cb.user_buffer = NULL; + cb.buffer_size = sizeof(array); + + si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer, + (void*)array, sizeof(array), + &cb.buffer_offset); + + ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL, + SI_DRIVER_STATE_CONST_BUF, &cb); + pipe_resource_reference(&cb.buffer, NULL); +} + static void si_texture_barrier(struct pipe_context *ctx) { struct si_context *sctx = (struct si_context *)ctx; @@ -2839,14 +3005,29 @@ static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw, bool include_draw_vbo) { - si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo); + si_need_cs_space((struct si_context*)ctx); } +static void si_init_config(struct si_context *sctx); + void si_init_state_functions(struct si_context *sctx) { - si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0); - si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10); - si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6); + si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin); + si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable); + + si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush); + si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state); + si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs); + si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state); + si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config); + si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask); + si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask); + si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color); + si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs); + si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state); + si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors); + si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports); + si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref); sctx->b.b.create_blend_state = si_create_blend_state; sctx->b.b.bind_blend_state = si_bind_blend_state; @@ -2869,13 +3050,12 @@ void si_init_state_functions(struct si_context *sctx) sctx->b.b.set_clip_state = si_set_clip_state; sctx->b.b.set_scissor_states = si_set_scissor_states; sctx->b.b.set_viewport_states = si_set_viewport_states; - sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref; + sctx->b.b.set_stencil_ref = si_set_stencil_ref; sctx->b.b.set_framebuffer_state = si_set_framebuffer_state; sctx->b.b.get_sample_position = cayman_get_sample_position; sctx->b.b.create_sampler_state = si_create_sampler_state; - sctx->b.b.bind_sampler_states = si_bind_sampler_states; sctx->b.b.delete_sampler_state = si_delete_sampler_state; sctx->b.b.create_sampler_view = si_create_sampler_view; @@ -2892,30 +3072,43 @@ void si_init_state_functions(struct si_context *sctx) sctx->b.b.texture_barrier = si_texture_barrier; sctx->b.b.set_polygon_stipple = si_set_polygon_stipple; sctx->b.b.set_min_samples = si_set_min_samples; + sctx->b.b.set_tess_state = si_set_tess_state; - sctx->b.dma_copy = si_dma_copy; sctx->b.set_occlusion_query_state = si_set_occlusion_query_state; sctx->b.need_gfx_cs_space = si_need_gfx_cs_space; sctx->b.b.draw_vbo = si_draw_vbo; + + if (sctx->b.chip_class >= CIK) { + sctx->b.dma_copy = cik_sdma_copy; + } else { + sctx->b.dma_copy = si_dma_copy; + } + + si_init_config(sctx); } static void si_write_harvested_raster_configs(struct si_context *sctx, struct si_pm4_state *pm4, - unsigned raster_config) + unsigned raster_config, + unsigned raster_config_1) { unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1); unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1); unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; - unsigned num_rb = sctx->screen->b.info.r600_num_backends; - unsigned rb_per_pkr = num_rb / num_se / sh_per_se; + unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16); + unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2); unsigned rb_per_se = num_rb / num_se; - unsigned se0_mask = (1 << rb_per_se) - 1; - unsigned se1_mask = se0_mask << rb_per_se; + unsigned se_mask[4]; unsigned se; - assert(num_se == 1 || num_se == 2); + se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; + se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; + se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; + se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; + + assert(num_se == 1 || num_se == 2 || num_se == 4); assert(sh_per_se == 1 || sh_per_se == 2); assert(rb_per_pkr == 1 || rb_per_pkr == 2); @@ -2923,17 +3116,16 @@ si_write_harvested_raster_configs(struct si_context *sctx, * fields are for, so I'm leaving them as their default * values. */ - se0_mask &= rb_mask; - se1_mask &= rb_mask; - if (num_se == 2 && (!se0_mask || !se1_mask)) { - raster_config &= C_028350_SE_MAP; + if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || + (!se_mask[2] && !se_mask[3]))) { + raster_config_1 &= C_028354_SE_PAIR_MAP; - if (!se0_mask) { - raster_config |= - S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3); + if (!se_mask[0] && !se_mask[1]) { + raster_config_1 |= + S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3); } else { - raster_config |= - S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0); + raster_config_1 |= + S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0); } } @@ -2941,10 +3133,23 @@ si_write_harvested_raster_configs(struct si_context *sctx, unsigned raster_config_se = raster_config; unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); unsigned pkr1_mask = pkr0_mask << rb_per_pkr; + int idx = (se / 2) * 2; + + if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { + raster_config_se &= C_028350_SE_MAP; + + if (!se_mask[idx]) { + raster_config_se |= + S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3); + } else { + raster_config_se |= + S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0); + } + } pkr0_mask &= rb_mask; pkr1_mask &= rb_mask; - if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) { + if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { raster_config_se &= C_028350_PKR_MAP; if (!pkr0_mask) { @@ -2956,7 +3161,7 @@ si_write_harvested_raster_configs(struct si_context *sctx, } } - if (rb_per_pkr == 2) { + if (rb_per_se >= 2) { unsigned rb0_mask = 1 << (se * rb_per_se); unsigned rb1_mask = rb0_mask << 1; @@ -2974,7 +3179,7 @@ si_write_harvested_raster_configs(struct si_context *sctx, } } - if (sh_per_se == 2) { + if (rb_per_se > 2) { rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); rb1_mask = rb0_mask << 1; rb0_mask &= rb_mask; @@ -2993,54 +3198,51 @@ si_write_harvested_raster_configs(struct si_context *sctx, } } - si_pm4_set_reg(pm4, GRBM_GFX_INDEX, - SE_INDEX(se) | SH_BROADCAST_WRITES | - INSTANCE_BROADCAST_WRITES); + /* GRBM_GFX_INDEX is privileged on VI */ + if (sctx->b.chip_class <= CIK) + si_pm4_set_reg(pm4, GRBM_GFX_INDEX, + SE_INDEX(se) | SH_BROADCAST_WRITES | + INSTANCE_BROADCAST_WRITES); si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); + if (sctx->b.chip_class >= CIK) + si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } - si_pm4_set_reg(pm4, GRBM_GFX_INDEX, - SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | - INSTANCE_BROADCAST_WRITES); + /* GRBM_GFX_INDEX is privileged on VI */ + if (sctx->b.chip_class <= CIK) + si_pm4_set_reg(pm4, GRBM_GFX_INDEX, + SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | + INSTANCE_BROADCAST_WRITES); } -void si_init_config(struct si_context *sctx) +static void si_init_config(struct si_context *sctx) { + unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16); + unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; + unsigned raster_config, raster_config_1; + uint64_t border_color_va = sctx->border_color_buffer->gpu_address; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + int i; if (pm4 == NULL) return; - si_cmd_context_control(pm4); - - si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); - si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); - si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); - si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); - si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); - si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); - si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); + si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL); + si_pm4_cmd_add(pm4, 0x80000000); + si_pm4_cmd_add(pm4, 0x80000000); + si_pm4_cmd_end(pm4, false); + + si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); + si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); /* FIXME calculate these values somehow ??? */ si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80); si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40); si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2); - si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); - si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0); si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); - si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0); - si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0); - si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0); - si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0); - si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0); si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); @@ -3053,62 +3255,83 @@ void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); - if (sctx->b.chip_class >= CIK) { - switch (sctx->screen->b.family) { - case CHIP_BONAIRE: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012); - si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0); - break; - case CHIP_HAWAII: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a); - si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e); - break; - case CHIP_KAVERI: - /* XXX todo */ - case CHIP_KABINI: - /* XXX todo */ - case CHIP_MULLINS: - /* XXX todo */ - default: - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0); - si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0); - break; - } - } else { - unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; - unsigned num_rb = sctx->screen->b.info.r600_num_backends; - unsigned raster_config; - - switch (sctx->screen->b.family) { - case CHIP_TAHITI: - case CHIP_PITCAIRN: - raster_config = 0x2a00126a; - break; - case CHIP_VERDE: - raster_config = 0x0000124a; - break; - case CHIP_OLAND: - raster_config = 0x00000082; - break; - case CHIP_HAINAN: - raster_config = 0; - break; - default: - fprintf(stderr, - "radeonsi: Unknown GPU, using 0 for raster_config\n"); - raster_config = 0; - break; - } + for (i = 0; i < 16; i++) { + si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0); + si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0)); + } - /* Always use the default config when all backends are enabled - * (or when we failed to determine the enabled backends). - */ - if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { - si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, - raster_config); - } else { - si_write_harvested_raster_configs(sctx, pm4, raster_config); - } + switch (sctx->screen->b.family) { + case CHIP_TAHITI: + case CHIP_PITCAIRN: + raster_config = 0x2a00126a; + raster_config_1 = 0x00000000; + break; + case CHIP_VERDE: + raster_config = 0x0000124a; + raster_config_1 = 0x00000000; + break; + case CHIP_OLAND: + raster_config = 0x00000082; + raster_config_1 = 0x00000000; + break; + case CHIP_HAINAN: + raster_config = 0x00000000; + raster_config_1 = 0x00000000; + break; + case CHIP_BONAIRE: + raster_config = 0x16000012; + raster_config_1 = 0x00000000; + break; + case CHIP_HAWAII: + raster_config = 0x3a00161a; + raster_config_1 = 0x0000002e; + break; + case CHIP_FIJI: + /* Fiji should be same as Hawaii, but that causes corruption in some cases */ + raster_config = 0x16000012; /* 0x3a00161a */ + raster_config_1 = 0x0000002a; /* 0x0000002e */ + break; + case CHIP_TONGA: + raster_config = 0x16000012; + raster_config_1 = 0x0000002a; + break; + case CHIP_ICELAND: + raster_config = 0x00000002; + raster_config_1 = 0x00000000; + break; + case CHIP_CARRIZO: + raster_config = 0x00000002; + raster_config_1 = 0x00000000; + break; + case CHIP_KAVERI: + /* KV should be 0x00000002, but that causes problems with radeon */ + raster_config = 0x00000000; /* 0x00000002 */ + raster_config_1 = 0x00000000; + break; + case CHIP_KABINI: + case CHIP_MULLINS: + raster_config = 0x00000000; + raster_config_1 = 0x00000000; + break; + default: + fprintf(stderr, + "radeonsi: Unknown GPU, using 0 for raster_config\n"); + raster_config = 0x00000000; + raster_config_1 = 0x00000000; + break; + } + + /* Always use the default config when all backends are enabled + * (or when we failed to determine the enabled backends). + */ + if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, + raster_config); + if (sctx->b.chip_class >= CIK) + si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, + raster_config_1); + } else { + si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); } si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); @@ -3123,15 +3346,11 @@ void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */ si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); - si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0); - si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, fui(1.0)); si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0); si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0)); si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0)); si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0)); si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0)); - si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0); - si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0); si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0); si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); @@ -3150,10 +3369,28 @@ void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); if (sctx->b.chip_class >= CIK) { + si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc)); + si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0); + si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe)); + si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff)); si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff)); si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0)); si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff)); } + if (sctx->b.chip_class >= VI) { + si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL, + S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1)); + si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30); + si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32); + } + + si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); + if (sctx->b.chip_class >= CIK) + si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40); + si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ, + RADEON_PRIO_SHADER_DATA); + + si_pm4_upload_indirect_buffer(sctx, pm4); sctx->init_config = pm4; }