X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state.h;h=fbc0d231226d3e18cb8d9581da160ea02f042089;hb=40b9812a761ce0745d9e17b92fd0abd27eb86bd7;hp=5e945ec25e074368ea26ebefc9c9cf2361bd1b85;hpb=7773c7109c9a3b31767fab012183f64b932264a7;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 5e945ec25e0..fbc0d231226 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -27,12 +27,13 @@ #ifndef SI_STATE_H #define SI_STATE_H -#include "radeonsi_pm4.h" +#include "si_pm4.h" +#include "../radeon/r600_pipe_common.h" struct si_state_blend { struct si_pm4_state pm4; uint32_t cb_target_mask; - uint32_t cb_color_control; + bool alpha_to_one; }; struct si_state_viewport { @@ -43,19 +44,23 @@ struct si_state_viewport { struct si_state_rasterizer { struct si_pm4_state pm4; bool flatshade; + bool two_side; + bool multisample_enable; + bool line_stipple_enable; unsigned sprite_coord_enable; unsigned pa_sc_line_stipple; unsigned pa_su_sc_mode_cntl; unsigned pa_cl_clip_cntl; unsigned pa_cl_vs_out_cntl; + unsigned clip_plane_enable; float offset_units; float offset_scale; }; struct si_state_dsa { struct si_pm4_state pm4; - unsigned alpha_ref; - unsigned db_render_override; + float alpha_ref; + unsigned alpha_func; unsigned db_render_control; uint8_t valuemask[2]; uint8_t writemask[2]; @@ -70,11 +75,11 @@ struct si_vertex_element union si_state { struct { - struct si_pm4_state *sync; struct si_pm4_state *init; struct si_state_blend *blend; struct si_pm4_state *blend_color; struct si_pm4_state *clip; + struct si_pm4_state *sample_mask; struct si_pm4_state *scissor; struct si_state_viewport *viewport; struct si_pm4_state *framebuffer; @@ -83,83 +88,158 @@ union si_state { struct si_pm4_state *fb_rs; struct si_pm4_state *fb_blend; struct si_pm4_state *dsa_stencil_ref; + struct si_pm4_state *es; + struct si_pm4_state *gs; + struct si_pm4_state *gs_rings; + struct si_pm4_state *gs_sampler; + struct si_pm4_state *gs_onoff; struct si_pm4_state *vs; - struct si_pm4_state *vs_const; + struct si_pm4_state *vs_sampler; struct si_pm4_state *ps; - struct si_pm4_state *ps_sampler_views; struct si_pm4_state *ps_sampler; - struct si_pm4_state *ps_const; struct si_pm4_state *spi; struct si_pm4_state *vertex_buffers; - struct si_pm4_state *texture_barrier; struct si_pm4_state *draw_info; struct si_pm4_state *draw; } named; struct si_pm4_state *array[0]; }; +#define NUM_TEX_UNITS 16 + +/* User sampler views: 0..15 + * FMASK sampler views: 16..31 (no sampler states) + */ +#define FMASK_TEX_OFFSET NUM_TEX_UNITS +#define NUM_SAMPLER_VIEWS (FMASK_TEX_OFFSET+NUM_TEX_UNITS) +#define NUM_SAMPLER_STATES NUM_TEX_UNITS + +#define NUM_PIPE_CONST_BUFFERS 16 +#define NUM_CONST_BUFFERS (NUM_PIPE_CONST_BUFFERS + 1) + +#define SI_RING_ESGS 0 +#define SI_RING_GSVS 1 + +/* This represents resource descriptors in memory, such as buffer resources, + * image resources, and sampler states. + */ +struct si_descriptors { + struct r600_atom atom; + + /* The size of one resource descriptor. */ + unsigned element_dw_size; + /* The maximum number of resource descriptors. */ + unsigned num_elements; + + /* The buffer where resource descriptors are stored. */ + struct r600_resource *buffer; + + /* The i-th bit is set if that element is dirty (changed but not emitted). */ + unsigned dirty_mask; + /* The i-th bit is set if that element is enabled (non-NULL resource). */ + unsigned enabled_mask; + + /* We can't update descriptors directly because the GPU might be + * reading them at the same time, so we have to update them + * in a copy-on-write manner. Each such copy is called a context, + * which is just another array descriptors in the same buffer. */ + unsigned current_context_id; + /* The size of a context, should be equal to 4*element_dw_size*num_elements. */ + unsigned context_size; + + /* The shader userdata register where the 64-bit pointer to the descriptor + * array will be stored. */ + unsigned shader_userdata_reg; +}; + +struct si_sampler_views { + struct si_descriptors desc; + struct pipe_sampler_view *views[NUM_SAMPLER_VIEWS]; + uint32_t *desc_data[NUM_SAMPLER_VIEWS]; +}; + +struct si_buffer_resources { + struct si_descriptors desc; + unsigned num_buffers; + enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */ + struct pipe_resource **buffers; /* this has num_buffers elements */ + uint32_t *desc_storage; /* this has num_buffers*4 elements */ + uint32_t **desc_data; /* an array of pointers pointing to desc_storage */ +}; + #define si_pm4_block_idx(member) \ (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *)) -#define si_pm4_state_changed(rctx, member) \ - ((rctx)->queued.named.member != (rctx)->emitted.named.member) +#define si_pm4_state_changed(sctx, member) \ + ((sctx)->queued.named.member != (sctx)->emitted.named.member) -#define si_pm4_bind_state(rctx, member, value) \ +#define si_pm4_bind_state(sctx, member, value) \ do { \ - (rctx)->queued.named.member = (value); \ + (sctx)->queued.named.member = (value); \ } while(0) -#define si_pm4_delete_state(rctx, member, value) \ +#define si_pm4_delete_state(sctx, member, value) \ do { \ - if ((rctx)->queued.named.member == (value)) { \ - (rctx)->queued.named.member = NULL; \ + if ((sctx)->queued.named.member == (value)) { \ + (sctx)->queued.named.member = NULL; \ } \ - si_pm4_free_state(rctx, (struct si_pm4_state *)(value), \ + si_pm4_free_state(sctx, (struct si_pm4_state *)(value), \ si_pm4_block_idx(member)); \ } while(0) -#define si_pm4_set_state(rctx, member, value) \ +#define si_pm4_set_state(sctx, member, value) \ do { \ - if ((rctx)->queued.named.member != (value)) { \ - si_pm4_free_state(rctx, \ - (struct si_pm4_state *)(rctx)->queued.named.member, \ + if ((sctx)->queued.named.member != (value)) { \ + si_pm4_free_state(sctx, \ + (struct si_pm4_state *)(sctx)->queued.named.member, \ si_pm4_block_idx(member)); \ - (rctx)->queued.named.member = (value); \ + (sctx)->queued.named.member = (value); \ } \ } while(0) +/* si_descriptors.c */ +void si_set_sampler_view(struct si_context *sctx, unsigned shader, + unsigned slot, struct pipe_sampler_view *view, + unsigned *view_desc); +void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot, + struct pipe_constant_buffer *input, + unsigned stride, unsigned num_records, + bool add_tid, bool swizzle, + unsigned element_size, unsigned index_stride); +void si_init_all_descriptors(struct si_context *sctx); +void si_release_all_descriptors(struct si_context *sctx); +void si_all_descriptors_begin_new_cs(struct si_context *sctx); +void si_copy_buffer(struct si_context *sctx, + struct pipe_resource *dst, struct pipe_resource *src, + uint64_t dst_offset, uint64_t src_offset, unsigned size); +void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer, + const uint8_t *ptr, unsigned size, uint32_t *const_offset); + /* si_state.c */ struct si_pipe_shader_selector; -bool si_is_format_supported(struct pipe_screen *screen, - enum pipe_format format, - enum pipe_texture_target target, - unsigned sample_count, - unsigned usage); +boolean si_is_format_supported(struct pipe_screen *screen, + enum pipe_format format, + enum pipe_texture_target target, + unsigned sample_count, + unsigned usage); int si_shader_select(struct pipe_context *ctx, - struct si_pipe_shader_selector *sel, - unsigned *dirty); -void si_init_state_functions(struct r600_context *rctx); -void si_init_config(struct r600_context *rctx); - -/* si_state_streamout.c */ -struct pipe_stream_output_target * -si_create_so_target(struct pipe_context *ctx, - struct pipe_resource *buffer, - unsigned buffer_offset, - unsigned buffer_size); -void si_so_target_destroy(struct pipe_context *ctx, - struct pipe_stream_output_target *target); -void si_set_so_targets(struct pipe_context *ctx, - unsigned num_targets, - struct pipe_stream_output_target **targets, - unsigned append_bitmask); + struct si_pipe_shader_selector *sel); +void si_init_state_functions(struct si_context *sctx); +void si_init_config(struct si_context *sctx); /* si_state_draw.c */ +extern const struct r600_atom si_atom_cache_flush; +void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom); void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo); /* si_commands.c */ void si_cmd_context_control(struct si_pm4_state *pm4); +void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size, + uint64_t index_base, uint32_t index_count, + uint32_t initiator, bool predicate); +void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count, + uint32_t initiator, bool predicate); void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl); #endif