X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state_draw.c;h=52ecf264ecb55317367daf9dbd836af9a249fdd7;hb=2f2d1b3d9b090aeba316d6c425c23e92340b5502;hp=e4045cd85a6b43d5d828075466f2ae6ea3f569b4;hpb=8afde9fa23db6ac1802f7a2c74123f10db96f552;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index e4045cd85a6..52ecf264ecb 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -54,7 +54,7 @@ static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *s return; va = r600_resource_va(ctx->screen, (void *)shader->bo); - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0; @@ -76,7 +76,6 @@ static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *s si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES, S_00B32C_USER_SGPR(num_user_sgprs)); - si_pm4_bind_state(sctx, es, shader->pm4); sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE; } @@ -130,7 +129,7 @@ static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *s si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize); va = r600_resource_va(ctx->screen, (void *)shader->bo); - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8); si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40); @@ -149,7 +148,6 @@ static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *s si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, S_00B22C_USER_SGPR(num_user_sgprs)); - si_pm4_bind_state(sctx, gs, shader->pm4); sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE; } @@ -168,7 +166,7 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s return; va = r600_resource_va(ctx->screen, (void *)shader->bo); - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0; @@ -226,7 +224,6 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) | S_00B12C_SO_EN(!!shader->selector->so.num_outputs)); - si_pm4_bind_state(sctx, vs, shader->pm4); sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE; } @@ -234,9 +231,9 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s { struct si_context *sctx = (struct si_context *)ctx; struct si_pm4_state *pm4; - unsigned i, exports_ps, spi_ps_in_control, db_shader_control; + unsigned i, spi_ps_in_control, db_shader_control; unsigned num_sgprs, num_user_sgprs; - unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format; + unsigned spi_baryc_cntl = 0, spi_ps_input_ena; uint64_t va; si_pm4_delete_state(sctx, ps, shader->pm4); @@ -246,7 +243,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s return; db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) | - S_02880C_ALPHA_TO_MASK_DISABLE(sctx->fb_cb0_is_integer); + S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer); for (i = 0; i < shader->shader.ninput; i++) { switch (shader->shader.input[i].name) { @@ -267,26 +264,11 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s } } - for (i = 0; i < shader->shader.noutput; i++) { - if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION) - db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); - if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL) - db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1); - } + db_shader_control |= shader->db_shader_control; + if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS) db_shader_control |= S_02880C_KILL_ENABLE(1); - exports_ps = 0; - for (i = 0; i < shader->shader.noutput; i++) { - if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION || - shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL) - exports_ps |= 1; - } - if (!exports_ps) { - /* always at least export 1 component per pixel */ - exports_ps = 2; - } - spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) | S_0286D8_BC_OPTIMIZE_DISABLE(1); @@ -306,19 +288,13 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena); si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control); - if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control)) - spi_shader_z_format = V_028710_SPI_SHADER_32_GR; - else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control)) - spi_shader_z_format = V_028710_SPI_SHADER_32_R; - else - spi_shader_z_format = 0; - si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format); + si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format); si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, shader->spi_shader_col_format); si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask); va = r600_resource_va(ctx->screen, (void *)shader->bo); - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40); @@ -340,9 +316,8 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control); - shader->cb0_is_integer = sctx->fb_cb0_is_integer; + shader->cb0_is_integer = sctx->framebuffer.cb0_is_integer; shader->sprite_coord_enable = sctx->sprite_coord_enable; - si_pm4_bind_state(sctx, ps, shader->pm4); sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE; } @@ -430,15 +405,18 @@ static bool si_update_draw_info_state(struct si_context *sctx, /* If the WD switch is false, the IA switch must be false too. */ bool ia_switch_on_eop = wd_switch_on_eop; - si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, + si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX, + ib->index_size == 4 ? 0xFC000000 : 0xFC00); + + si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE); + si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */ + si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */ S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63) | S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop)); - si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX, - ib->index_size == 4 ? 0xFC000000 : 0xFC00); - - si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim); + si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */ + si_pm4_cmd_end(pm4, false); } else { si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim); } @@ -552,13 +530,13 @@ static void si_init_gs_rings(struct si_context *sctx) sctx->esgs_ring.buffer = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM, - PIPE_USAGE_STATIC, size); + PIPE_USAGE_DEFAULT, size); sctx->esgs_ring.buffer_size = size; size = 64 * 1024 * 1024; sctx->gsvs_ring.buffer = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM, - PIPE_USAGE_STATIC, size); + PIPE_USAGE_DEFAULT, size); sctx->gsvs_ring.buffer_size = size; if (sctx->b.chip_class >= CIK) { @@ -573,18 +551,20 @@ static void si_init_gs_rings(struct si_context *sctx) sctx->gsvs_ring.buffer_size / 256); } - si_set_ring_buffer(&sctx->b.b, SI_SHADER_EXPORT, 0, &sctx->esgs_ring, - 0, sctx->esgs_ring.buffer_size, true, true, 4, 64); - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, 0, &sctx->esgs_ring, - 0, sctx->esgs_ring.buffer_size, false, false, 0, 0); - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, 0, &sctx->gsvs_ring, - 0, sctx->gsvs_ring.buffer_size, false, false, 0, 0); + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS, + &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size, + true, true, 4, 64); + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS, + &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size, + false, false, 0, 0); + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS, + &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size, + false, false, 0, 0); } static void si_update_derived_state(struct si_context *sctx) { struct pipe_context * ctx = (struct pipe_context*)sctx; - unsigned vs_dirty = 0, ps_dirty = 0; if (!sctx->blitter->running) { /* Flush depth textures which need to be flushed. */ @@ -599,33 +579,25 @@ static void si_update_derived_state(struct si_context *sctx) } if (sctx->gs_shader) { - unsigned es_dirty = 0, gs_dirty = 0; - - si_shader_select(ctx, sctx->gs_shader, &gs_dirty); + si_shader_select(ctx, sctx->gs_shader); if (!sctx->gs_shader->current->pm4) { si_pipe_shader_gs(ctx, sctx->gs_shader->current); si_pipe_shader_vs(ctx, sctx->gs_shader->current->gs_copy_shader); - gs_dirty = 0; } - if (gs_dirty) { - si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4); - si_pm4_bind_state(sctx, vs, - sctx->gs_shader->current->gs_copy_shader->pm4); - } + si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4); + si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4); + + sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride; - si_shader_select(ctx, sctx->vs_shader, &es_dirty); + si_shader_select(ctx, sctx->vs_shader); - if (!sctx->vs_shader->current->pm4) { + if (!sctx->vs_shader->current->pm4) si_pipe_shader_es(ctx, sctx->vs_shader->current); - es_dirty = 0; - } - if (es_dirty) { - si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4); - } + si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4); if (!sctx->gs_rings) si_init_gs_rings(sctx); @@ -633,7 +605,8 @@ static void si_update_derived_state(struct si_context *sctx) sctx->b.flags |= R600_CONTEXT_VGT_FLUSH; si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings); - si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, 1, &sctx->gsvs_ring, + si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS, + &sctx->gsvs_ring, sctx->gs_shader->current->shader.gs_max_out_vertices * sctx->gs_shader->current->shader.noutput * 16, 64, true, true, 4, 16); @@ -648,16 +621,14 @@ static void si_update_derived_state(struct si_context *sctx) } si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on); } else { - si_shader_select(ctx, sctx->vs_shader, &vs_dirty); + si_shader_select(ctx, sctx->vs_shader); - if (!sctx->vs_shader->current->pm4) { + if (!sctx->vs_shader->current->pm4) si_pipe_shader_vs(ctx, sctx->vs_shader->current); - vs_dirty = 0; - } - if (vs_dirty) { - si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4); - } + si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4); + + sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride; if (!sctx->gs_off) { sctx->gs_off = si_pm4_alloc_state(sctx); @@ -671,20 +642,13 @@ static void si_update_derived_state(struct si_context *sctx) si_pm4_bind_state(sctx, es, NULL); } - si_shader_select(ctx, sctx->ps_shader, &ps_dirty); + si_shader_select(ctx, sctx->ps_shader); - if (!sctx->ps_shader->current->pm4) { - si_pipe_shader_ps(ctx, sctx->ps_shader->current); - ps_dirty = 0; - } - if (sctx->ps_shader->current->cb0_is_integer != sctx->fb_cb0_is_integer) { + if (!sctx->ps_shader->current->pm4 || + sctx->ps_shader->current->cb0_is_integer != sctx->framebuffer.cb0_is_integer) si_pipe_shader_ps(ctx, sctx->ps_shader->current); - ps_dirty = 0; - } - if (ps_dirty) { - si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4); - } + si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4); if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) { /* XXX: Emitting the PS state even when only the VS changed @@ -746,7 +710,8 @@ static void si_vertex_buffer_update(struct si_context *sctx) si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]); if (!bound[ve->vertex_buffer_index]) { - si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ, + RADEON_PRIO_SHADER_BUFFER_RO); bound[ve->vertex_buffer_index] = true; } } @@ -772,14 +737,14 @@ static void si_state_draw(struct si_context *sctx, if (sctx->b.chip_class >= CIK) { si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL, S_028004_PERFECT_ZPASS_COUNTS(1) | - S_028004_SAMPLE_RATE(sctx->fb_log_samples) | + S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) | S_028004_ZPASS_ENABLE(1) | S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1)); } else { si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL, S_028004_PERFECT_ZPASS_COUNTS(1) | - S_028004_SAMPLE_RATE(sctx->fb_log_samples)); + S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples)); } } @@ -802,7 +767,8 @@ static void si_state_draw(struct si_context *sctx, si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */ si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); si_pm4_cmd_add(pm4, 0); /* unused */ - si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ, + RADEON_PRIO_MIN); si_pm4_cmd_end(pm4, true); } @@ -828,7 +794,8 @@ static void si_state_draw(struct si_context *sctx, va = r600_resource_va(&sctx->screen->b.b, ib->buffer); va += ib->offset; - si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ); + si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ, + RADEON_PRIO_MIN); si_cmd_draw_index_2(pm4, max_size, va, info->count, V_0287F0_DI_SRC_SEL_DMA, sctx->b.predicate_drawing); @@ -979,7 +946,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) /* Check flush flags. */ if (sctx->b.flags) - sctx->atoms.cache_flush->dirty = true; + sctx->atoms.s.cache_flush->dirty = true; si_need_cs_space(sctx, 0, TRUE); @@ -1001,20 +968,20 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) #endif /* Set the depth buffer as dirty. */ - if (sctx->framebuffer.zsbuf) { - struct pipe_surface *surf = sctx->framebuffer.zsbuf; + if (sctx->framebuffer.state.zsbuf) { + struct pipe_surface *surf = sctx->framebuffer.state.zsbuf; struct r600_texture *rtex = (struct r600_texture *)surf->texture; rtex->dirty_level_mask |= 1 << surf->u.tex.level; } - if (sctx->fb_compressed_cb_mask) { + if (sctx->framebuffer.compressed_cb_mask) { struct pipe_surface *surf; struct r600_texture *rtex; - unsigned mask = sctx->fb_compressed_cb_mask; + unsigned mask = sctx->framebuffer.compressed_cb_mask; do { unsigned i = u_bit_scan(&mask); - surf = sctx->framebuffer.cbufs[i]; + surf = sctx->framebuffer.state.cbufs[i]; rtex = (struct r600_texture*)surf->texture; rtex->dirty_level_mask |= 1 << surf->u.tex.level;