X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state_draw.c;h=9a80bd813272f36068affdb1e5b4b0957beb121a;hb=c252273f98fbad8fac123ec69f331bf6749cf178;hp=9cb4274115359970adc8e9fd5b00eb7fd9c21920;hpb=0a3b5a0232cef1598ff0417e588a2d32e81d4f6a;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 9cb42741153..9a80bd81327 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1,5 +1,6 @@ /* * Copyright 2012 Advanced Micro Devices, Inc. + * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,14 +20,9 @@ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Christian König */ -#include "si_pipe.h" -#include "radeon/r600_cs.h" -#include "sid.h" +#include "si_build_pm4.h" #include "gfx9d.h" #include "util/u_index_modify.h" @@ -36,6 +32,9 @@ #include "ac_debug.h" +/* special primitive types */ +#define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX + static unsigned si_conv_pipe_prim(unsigned mode) { static const unsigned prim_conv[] = { @@ -54,37 +53,12 @@ static unsigned si_conv_pipe_prim(unsigned mode) [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ, [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ, [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH, - [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST + [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST }; assert(mode < ARRAY_SIZE(prim_conv)); return prim_conv[mode]; } -static unsigned si_conv_prim_to_gs_out(unsigned mode) -{ - static const int prim_conv[] = { - [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST, - [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, - [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, - [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, - [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, - [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, - [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, - [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, - [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, - [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, - [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, - [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, - [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, - [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, - [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST, - [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP - }; - assert(mode < ARRAY_SIZE(prim_conv)); - - return prim_conv[mode]; -} - /** * This calculates the LDS size for tessellation shaders (VS, TCS, TES). * LS.LDS_SIZE is shared by all 3 shader stages. @@ -92,11 +66,11 @@ static unsigned si_conv_prim_to_gs_out(unsigned mode) * The information about LDS and other non-compile-time parameters is then * written to userdata SGPRs. */ -static void si_emit_derived_tess_state(struct si_context *sctx, +static bool si_emit_derived_tess_state(struct si_context *sctx, const struct pipe_draw_info *info, unsigned *num_patches) { - struct radeon_winsys_cs *cs = sctx->b.gfx.cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; struct si_shader *ls_current; struct si_shader_selector *ls; /* The TES pointer will only be used for sctx->last_tcs. @@ -104,8 +78,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx, struct si_shader_selector *tcs = sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso; unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id; - bool has_primid_instancing_bug = sctx->b.chip_class == SI && - sctx->b.screen->info.max_se == 1; + bool has_primid_instancing_bug = sctx->chip_class == SI && + sctx->screen->info.max_se == 1; unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; unsigned num_tcs_input_cp = info->vertices_per_patch; unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs; @@ -117,7 +91,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned offchip_layout, hardware_lds_size, ls_hs_config; /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */ - if (sctx->b.chip_class >= GFX9) { + if (sctx->chip_class >= GFX9) { if (sctx->tcs_shader.cso) ls_current = sctx->tcs_shader.current; else @@ -136,7 +110,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, (!has_primid_instancing_bug || (sctx->last_tess_uses_primid == tess_uses_primid))) { *num_patches = sctx->last_num_patches; - return; + return false; } sctx->last_ls = ls_current; @@ -160,7 +134,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */ } - input_vertex_size = num_tcs_inputs * 16; + input_vertex_size = ls->lshs_vertex_stride; output_vertex_size = num_tcs_outputs * 16; input_patch_size = num_tcs_input_cp * input_vertex_size; @@ -172,7 +146,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx, * resource usage. Also ensures that the number of tcs in and out * vertices per threadgroup are at most 256. */ - *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4; + unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp); + *num_patches = 256 / max_verts_per_patch; /* Make sure that the data fits in LDS. This assumes the shaders only * use LDS for the inputs and outputs. @@ -190,16 +165,31 @@ static void si_emit_derived_tess_state(struct si_context *sctx, (sctx->screen->tess_offchip_block_dw_size * 4) / output_patch_size); - /* Not necessary for correctness, but improves performance. The - * specific value is taken from the proprietary driver. + /* Not necessary for correctness, but improves performance. + * The hardware can do more, but the radeonsi shader constant is + * limited to 6 bits. + */ + *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */ + + /* When distributed tessellation is unsupported, switch between SEs + * at a higher frequency to compensate for it. */ - *num_patches = MIN2(*num_patches, 40); + if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1) + *num_patches = MIN2(*num_patches, 16); /* recommended */ - if (sctx->b.chip_class == SI) { + /* Make sure that vector lanes are reasonably occupied. It probably + * doesn't matter much because this is LS-HS, and TES is likely to + * occupy significantly more CUs. + */ + unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch; + if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48) + *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch; + + if (sctx->chip_class == SI) { /* SI bug workaround, related to power management. Limit LS-HS * threadgroups to only one wave. */ - unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp); + unsigned one_wave = 64 / max_verts_per_patch; *num_patches = MIN2(*num_patches, one_wave); } @@ -231,9 +221,14 @@ static void si_emit_derived_tess_state(struct si_context *sctx, assert(num_tcs_input_cp <= 32); assert(num_tcs_output_cp <= 32); + uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address; + assert((ring_va & u_bit_consecutive(0, 19)) == 0); + tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) | S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4); - tcs_out_layout = output_patch_size / 4; + tcs_out_layout = (output_patch_size / 4) | + (num_tcs_input_cp << 13) | + ring_va; tcs_out_offsets = (output_patch0_offset / 16) | ((perpatch_output_offset / 16) << 16); offchip_layout = *num_patches | @@ -243,7 +238,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, /* Compute the LDS size. */ lds_size = output_patch0_offset + output_patch_size * *num_patches; - if (sctx->b.chip_class >= CIK) { + if (sctx->chip_class >= CIK) { assert(lds_size <= 65536); lds_size = align(lds_size, 512) / 512; } else { @@ -256,7 +251,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, C_VS_STATE_LS_OUT_VERTEX_SIZE; sctx->current_vs_state |= tcs_in_layout; - if (sctx->b.chip_class >= GFX9) { + if (sctx->chip_class >= GFX9) { unsigned hs_rsrc2 = ls_current->config.rsrc2 | S_00B42C_LDS_SIZE(lds_size); @@ -268,7 +263,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3); radeon_emit(cs, offchip_layout); radeon_emit(cs, tcs_out_offsets); - radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26)); + radeon_emit(cs, tcs_out_layout); } else { unsigned ls_rsrc2 = ls_current->config.rsrc2; @@ -277,7 +272,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, /* Due to a hw bug, RSRC2_LS must be written twice with another * LS register written in between. */ - if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII) + if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII) radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2); radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); radeon_emit(cs, ls_current->config.rsrc1); @@ -288,25 +283,31 @@ static void si_emit_derived_tess_state(struct si_context *sctx, R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4); radeon_emit(cs, offchip_layout); radeon_emit(cs, tcs_out_offsets); - radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26)); + radeon_emit(cs, tcs_out_layout); radeon_emit(cs, tcs_in_layout); } /* Set userdata SGPRs for TES. */ radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); radeon_emit(cs, offchip_layout); - radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16); + radeon_emit(cs, ring_va); ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) | S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) | S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp); - if (sctx->b.chip_class >= CIK) - radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, - ls_hs_config); - else - radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, - ls_hs_config); + if (sctx->last_ls_hs_config != ls_hs_config) { + if (sctx->chip_class >= CIK) { + radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, + ls_hs_config); + } else { + radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, + ls_hs_config); + } + sctx->last_ls_hs_config = ls_hs_config; + return true; /* true if the context rolls */ + } + return false; } static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info) @@ -314,10 +315,12 @@ static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info) switch (info->mode) { case PIPE_PRIM_PATCHES: return info->count / info->vertices_per_patch; - case R600_PRIM_RECTANGLE_LIST: + case PIPE_PRIM_POLYGON: + return info->count >= 3; + case SI_PRIM_RECTANGLE_LIST: return info->count / 3; default: - return u_prims_for_vertices(info->mode, info->count); + return u_decomposed_prims_for_vertices(info->mode, info->count); } } @@ -341,25 +344,17 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen, ia_switch_on_eoi = true; /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */ - if ((sscreen->b.family == CHIP_TAHITI || - sscreen->b.family == CHIP_PITCAIRN || - sscreen->b.family == CHIP_BONAIRE) && + if ((sscreen->info.family == CHIP_TAHITI || + sscreen->info.family == CHIP_PITCAIRN || + sscreen->info.family == CHIP_BONAIRE) && key->u.uses_gs) partial_vs_wave = true; - /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */ + /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= VI) */ if (sscreen->has_distributed_tess) { if (key->u.uses_gs) { - if (sscreen->b.chip_class <= VI) + if (sscreen->info.chip_class == VI) partial_es_wave = true; - - /* GPU hang workaround. */ - if (sscreen->b.family == CHIP_TONGA || - sscreen->b.family == CHIP_FIJI || - sscreen->b.family == CHIP_POLARIS10 || - sscreen->b.family == CHIP_POLARIS11 || - sscreen->b.family == CHIP_POLARIS12) - partial_vs_wave = true; } else { partial_vs_wave = true; } @@ -368,12 +363,12 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen, /* This is a hardware requirement. */ if (key->u.line_stipple_enabled || - (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) { + (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) { ia_switch_on_eop = true; wd_switch_on_eop = true; } - if (sscreen->b.chip_class >= CIK) { + if (sscreen->info.chip_class >= CIK) { /* WD_SWITCH_ON_EOP has no effect on GPUs with less than * 4 shader engines. Set 1 to pass the assertion below. * The other cases are hardware requirements. @@ -381,13 +376,13 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen, * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0 * for points, line strips, and tri strips. */ - if (sscreen->b.info.max_se < 4 || + if (sscreen->info.max_se <= 2 || key->u.prim == PIPE_PRIM_POLYGON || key->u.prim == PIPE_PRIM_LINE_LOOP || key->u.prim == PIPE_PRIM_TRIANGLE_FAN || key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY || (key->u.primitive_restart && - (sscreen->b.family < CHIP_POLARIS10 || + (sscreen->info.family < CHIP_POLARIS10 || (key->u.prim != PIPE_PRIM_POINTS && key->u.prim != PIPE_PRIM_LINE_STRIP && key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) || @@ -397,7 +392,7 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen, /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0. * We don't know that for indirect drawing, so treat it as * always problematic. */ - if (sscreen->b.family == CHIP_HAWAII && + if (sscreen->info.family == CHIP_HAWAII && key->u.uses_instancing) wd_switch_on_eop = true; @@ -406,50 +401,68 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen, * Assume indirect draws always use small instances. * This is needed for good VS wave utilization. */ - if (sscreen->b.chip_class <= VI && - sscreen->b.info.max_se == 4 && + if (sscreen->info.chip_class <= VI && + sscreen->info.max_se == 4 && key->u.multi_instances_smaller_than_primgroup) wd_switch_on_eop = true; /* Required on CIK and later. */ - if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop) + if (sscreen->info.max_se == 4 && !wd_switch_on_eop) ia_switch_on_eoi = true; + /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set + * to work around a GS hang. + */ + if (key->u.uses_gs && + (sscreen->info.family == CHIP_TONGA || + sscreen->info.family == CHIP_FIJI || + sscreen->info.family == CHIP_POLARIS10 || + sscreen->info.family == CHIP_POLARIS11 || + sscreen->info.family == CHIP_POLARIS12 || + sscreen->info.family == CHIP_VEGAM)) + partial_vs_wave = true; + /* Required by Hawaii and, for some special cases, by VI. */ if (ia_switch_on_eoi && - (sscreen->b.family == CHIP_HAWAII || - (sscreen->b.chip_class == VI && + (sscreen->info.family == CHIP_HAWAII || + (sscreen->info.chip_class == VI && (key->u.uses_gs || max_primgroup_in_wave != 2)))) partial_vs_wave = true; /* Instancing bug on Bonaire. */ - if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi && + if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi && key->u.uses_instancing) partial_vs_wave = true; + /* This only applies to Polaris10 and later 4 SE chips. + * wd_switch_on_eop is already true on all other chips. + */ + if (!wd_switch_on_eop && key->u.primitive_restart) + partial_vs_wave = true; + /* If the WD switch is false, the IA switch must be false too. */ assert(wd_switch_on_eop || !ia_switch_on_eop); } /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */ - if (sscreen->b.chip_class <= VI && ia_switch_on_eoi) + if (sscreen->info.chip_class <= VI && ia_switch_on_eoi) partial_es_wave = true; return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) | S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) | - S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) | + S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) | /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ - S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ? + S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ? max_primgroup_in_wave : 0) | - S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) | - S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9); + S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) | + S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9); } -void si_init_ia_multi_vgt_param_table(struct si_context *sctx) +static void si_init_ia_multi_vgt_param_table(struct si_context *sctx) { - for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++) + for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++) for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++) for (int multi_instances = 0; multi_instances < 2; multi_instances++) for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++) @@ -507,7 +520,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, if (sctx->gs_shader.cso) { /* GS requirement. */ - if (sctx->b.chip_class <= VI && + if (sctx->chip_class <= VI && SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3) ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1); @@ -515,36 +528,32 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, * The hw doc says all multi-SE chips are affected, but Vulkan * only applies it to Hawaii. Do what Vulkan does. */ - if (sctx->b.family == CHIP_HAWAII && + if (sctx->family == CHIP_HAWAII && G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) && (info->indirect || (info->instance_count > 1 && (info->count_from_stream_output || si_num_prims_for_vertices(info) <= 1)))) - sctx->b.flags |= SI_CONTEXT_VGT_FLUSH; + sctx->flags |= SI_CONTEXT_VGT_FLUSH; } return ia_multi_vgt_param; } /* rast_prim is the primitive type after GS. */ -static void si_emit_rasterizer_prim_state(struct si_context *sctx) +static bool si_emit_rasterizer_prim_state(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->b.gfx.cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; enum pipe_prim_type rast_prim = sctx->current_rast_prim; - struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer; + struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; /* Skip this if not rendering lines. */ - if (rast_prim != PIPE_PRIM_LINES && - rast_prim != PIPE_PRIM_LINE_LOOP && - rast_prim != PIPE_PRIM_LINE_STRIP && - rast_prim != PIPE_PRIM_LINES_ADJACENCY && - rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY) - return; + if (!util_prim_is_lines(rast_prim)) + return false; if (rast_prim == sctx->last_rast_prim && rs->pa_sc_line_stipple == sctx->last_sc_line_stipple) - return; + return false; /* For lines, reset the stipple pattern at each primitive. Otherwise, * reset the stipple pattern at each packet (line strips, line loops). @@ -555,6 +564,7 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx) sctx->last_rast_prim = rast_prim; sctx->last_sc_line_stipple = rs->pa_sc_line_stipple; + return true; /* true if the context rolls */ } static void si_emit_vs_state(struct si_context *sctx, @@ -563,34 +573,60 @@ static void si_emit_vs_state(struct si_context *sctx, sctx->current_vs_state &= C_VS_STATE_INDEXED; sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size); + if (sctx->num_vs_blit_sgprs) { + /* Re-emit the state after we leave u_blitter. */ + sctx->last_vs_state = ~0; + return; + } + if (sctx->current_vs_state != sctx->last_vs_state) { - struct radeon_winsys_cs *cs = sctx->b.gfx.cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; + /* For the API vertex shader (VS_STATE_INDEXED). */ radeon_set_sh_reg(cs, sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_STATE_BITS * 4, sctx->current_vs_state); + /* For vertex color clamping, which is done in the last stage + * before the rasterizer. */ + if (sctx->gs_shader.cso || sctx->tes_shader.cso) { + /* GS copy shader or TES if GS is missing. */ + radeon_set_sh_reg(cs, + R_00B130_SPI_SHADER_USER_DATA_VS_0 + + SI_SGPR_VS_STATE_BITS * 4, + sctx->current_vs_state); + } + sctx->last_vs_state = sctx->current_vs_state; } } +static inline bool si_prim_restart_index_changed(struct si_context *sctx, + const struct pipe_draw_info *info) +{ + return info->primitive_restart && + (info->restart_index != sctx->last_restart_index || + sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN); +} + static void si_emit_draw_registers(struct si_context *sctx, const struct pipe_draw_info *info, unsigned num_patches) { - struct radeon_winsys_cs *cs = sctx->b.gfx.cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned prim = si_conv_pipe_prim(info->mode); - unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim); unsigned ia_multi_vgt_param; ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches); /* Draw state. */ if (ia_multi_vgt_param != sctx->last_multi_vgt_param) { - if (sctx->b.chip_class >= GFX9) - radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param); - else if (sctx->b.chip_class >= CIK) + if (sctx->chip_class >= GFX9) + radeon_set_uconfig_reg_idx(cs, sctx->screen, + R_030960_IA_MULTI_VGT_PARAM, 4, + ia_multi_vgt_param); + else if (sctx->chip_class >= CIK) radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param); else radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); @@ -598,22 +634,18 @@ static void si_emit_draw_registers(struct si_context *sctx, sctx->last_multi_vgt_param = ia_multi_vgt_param; } if (prim != sctx->last_prim) { - if (sctx->b.chip_class >= CIK) - radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim); + if (sctx->chip_class >= CIK) + radeon_set_uconfig_reg_idx(cs, sctx->screen, + R_030908_VGT_PRIMITIVE_TYPE, 1, prim); else radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim); sctx->last_prim = prim; } - if (gs_out_prim != sctx->last_gs_out_prim) { - radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); - sctx->last_gs_out_prim = gs_out_prim; - } - /* Primitive restart. */ if (info->primitive_restart != sctx->last_primitive_restart_en) { - if (sctx->b.chip_class >= GFX9) + if (sctx->chip_class >= GFX9) radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart); else @@ -623,9 +655,7 @@ static void si_emit_draw_registers(struct si_context *sctx, sctx->last_primitive_restart_en = info->primitive_restart; } - if (info->primitive_restart && - (info->restart_index != sctx->last_restart_index || - sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) { + if (si_prim_restart_index_changed(sctx, info)) { radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index); sctx->last_restart_index = info->restart_index; @@ -639,15 +669,15 @@ static void si_emit_draw_packets(struct si_context *sctx, unsigned index_offset) { struct pipe_draw_indirect_info *indirect = info->indirect; - struct radeon_winsys_cs *cs = sctx->b.gfx.cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX]; - bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off; + bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off; uint32_t index_max_size = 0; uint64_t index_va = 0; if (info->count_from_stream_output) { - struct r600_so_target *t = - (struct r600_so_target*)info->count_from_stream_output; + struct si_streamout_target *t = + (struct si_streamout_target*)info->count_from_stream_output; uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset; @@ -655,7 +685,7 @@ static void si_emit_draw_packets(struct si_context *sctx, t->stride_in_dw); radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); - radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) | + radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) | COPY_DATA_DST_SEL(COPY_DATA_REG) | COPY_DATA_WR_CONFIRM); radeon_emit(cs, va); /* src address lo */ @@ -663,7 +693,7 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); radeon_emit(cs, 0); /* unused */ - radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, t->buf_filled_size, RADEON_USAGE_READ, RADEON_PRIO_SO_FILLED_SIZE); } @@ -680,12 +710,12 @@ static void si_emit_draw_packets(struct si_context *sctx, break; case 2: index_type = V_028A7C_VGT_INDEX_16 | - (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ? + (SI_BIG_ENDIAN && sctx->chip_class <= CIK ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0); break; case 4: index_type = V_028A7C_VGT_INDEX_32 | - (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ? + (SI_BIG_ENDIAN && sctx->chip_class <= CIK ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0); break; default: @@ -693,9 +723,10 @@ static void si_emit_draw_packets(struct si_context *sctx, return; } - if (sctx->b.chip_class >= GFX9) { - radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE, - 2, index_type); + if (sctx->chip_class >= GFX9) { + radeon_set_uconfig_reg_idx(cs, sctx->screen, + R_03090C_VGT_INDEX_TYPE, 2, + index_type); } else { radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); radeon_emit(cs, index_type); @@ -708,14 +739,14 @@ static void si_emit_draw_packets(struct si_context *sctx, index_size; index_va = r600_resource(indexbuf)->gpu_address + index_offset; - radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, - (struct r600_resource *)indexbuf, + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + r600_resource(indexbuf), RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER); } else { /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE, * so the state must be re-emitted before the next indexed draw. */ - if (sctx->b.chip_class >= CIK) + if (sctx->chip_class >= CIK) sctx->last_index_size = -1; } @@ -731,8 +762,8 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_emit(cs, indirect_va); radeon_emit(cs, indirect_va >> 32); - radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, - (struct r600_resource *)indirect->buffer, + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + r600_resource(indirect->buffer), RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT); unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA @@ -762,10 +793,10 @@ static void si_emit_draw_packets(struct si_context *sctx, if (indirect->indirect_draw_count) { struct r600_resource *params_buf = - (struct r600_resource *)indirect->indirect_draw_count; + r600_resource(indirect->indirect_draw_count); radeon_add_to_buffer_list( - &sctx->b, &sctx->b.gfx, params_buf, + sctx, sctx->gfx_cs, params_buf, RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT); count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset; @@ -787,19 +818,33 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_emit(cs, di_src_sel); } } else { + unsigned instance_count = info->instance_count; int base_vertex; - radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); - radeon_emit(cs, info->instance_count); + if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN || + sctx->last_instance_count != instance_count) { + radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); + radeon_emit(cs, instance_count); + sctx->last_instance_count = instance_count; + } /* Base vertex and start instance. */ base_vertex = index_size ? info->index_bias : info->start; - if (base_vertex != sctx->last_base_vertex || - sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN || - info->start_instance != sctx->last_start_instance || - info->drawid != sctx->last_drawid || - sh_base_reg != sctx->last_sh_base_reg) { + if (sctx->num_vs_blit_sgprs) { + /* Re-emit draw constants after we leave u_blitter. */ + si_invalidate_draw_sh_constants(sctx); + + /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */ + radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, + sctx->num_vs_blit_sgprs); + radeon_emit_array(cs, sctx->vs_blit_sh_data, + sctx->num_vs_blit_sgprs); + } else if (base_vertex != sctx->last_base_vertex || + sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN || + info->start_instance != sctx->last_start_instance || + info->drawid != sctx->last_drawid || + sh_base_reg != sctx->last_sh_base_reg) { radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3); radeon_emit(cs, base_vertex); radeon_emit(cs, info->start_instance); @@ -829,12 +874,12 @@ static void si_emit_draw_packets(struct si_context *sctx, } } -static void si_emit_surface_sync(struct r600_common_context *rctx, +static void si_emit_surface_sync(struct si_context *sctx, unsigned cp_coher_cntl) { - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; - if (rctx->chip_class >= GFX9) { + if (sctx->chip_class >= GFX9) { /* Flush caches and wait for the caches to assert idle. */ radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0)); radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ @@ -855,16 +900,16 @@ static void si_emit_surface_sync(struct r600_common_context *rctx, void si_emit_cache_flush(struct si_context *sctx) { - struct r600_common_context *rctx = &sctx->b; - struct radeon_winsys_cs *cs = rctx->gfx.cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; + uint32_t flags = sctx->flags; uint32_t cp_coher_cntl = 0; - uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB | - SI_CONTEXT_FLUSH_AND_INV_DB); + uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB | + SI_CONTEXT_FLUSH_AND_INV_DB); - if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) - sctx->b.num_cb_cache_flushes++; - if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) - sctx->b.num_db_cache_flushes++; + if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) + sctx->num_cb_cache_flushes++; + if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) + sctx->num_db_cache_flushes++; /* SI has a bug that it always flushes ICACHE and KCACHE if either * bit is set. An alternative way is to write SQC_CACHES, but that @@ -874,13 +919,13 @@ void si_emit_cache_flush(struct si_context *sctx) * to add a workaround for it. */ - if (rctx->flags & SI_CONTEXT_INV_ICACHE) + if (flags & SI_CONTEXT_INV_ICACHE) cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1); - if (rctx->flags & SI_CONTEXT_INV_SMEM_L1) + if (flags & SI_CONTEXT_INV_SMEM_L1) cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1); - if (rctx->chip_class <= VI) { - if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) { + if (sctx->chip_class <= VI) { + if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) { cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) | S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) | @@ -892,23 +937,25 @@ void si_emit_cache_flush(struct si_context *sctx) S_0085F0_CB7_DEST_BASE_ENA(1); /* Necessary for DCC */ - if (rctx->chip_class == VI) - si_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS, - 0, EOP_DATA_SEL_DISCARD, NULL, - 0, 0, R600_NOT_QUERY); + if (sctx->chip_class == VI) + si_cp_release_mem(sctx, + V_028A90_FLUSH_AND_INV_CB_DATA_TS, + 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, + EOP_DATA_SEL_DISCARD, NULL, + 0, 0, SI_NOT_QUERY); } - if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) + if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1); } - if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) { + if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) { /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); } - if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_DB | - SI_CONTEXT_FLUSH_AND_INV_DB_META)) { + if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB | + SI_CONTEXT_FLUSH_AND_INV_DB_META)) { /* Flush HTILE. SURFACE_SYNC will wait for idle. */ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); @@ -919,35 +966,35 @@ void si_emit_cache_flush(struct si_context *sctx) * for everything including CB/DB cache flushes. */ if (!flush_cb_db) { - if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) { + if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); /* Only count explicit shader flushes, not implicit ones * done by SURFACE_SYNC. */ - rctx->num_vs_flushes++; - rctx->num_ps_flushes++; - } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) { + sctx->num_vs_flushes++; + sctx->num_ps_flushes++; + } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); - rctx->num_vs_flushes++; + sctx->num_vs_flushes++; } } - if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH && + if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && sctx->compute_is_busy) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4))); - rctx->num_cs_flushes++; + radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); + sctx->num_cs_flushes++; sctx->compute_is_busy = false; } /* VGT state synchronization. */ - if (rctx->flags & SI_CONTEXT_VGT_FLUSH) { + if (flags & SI_CONTEXT_VGT_FLUSH) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); } - if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) { + if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); } @@ -955,7 +1002,7 @@ void si_emit_cache_flush(struct si_context *sctx) /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't * wait for idle on GFX9. We have to use a TS event. */ - if (sctx->b.chip_class >= GFX9 && flush_cb_db) { + if (sctx->chip_class >= GFX9 && flush_cb_db) { uint64_t va; unsigned tc_flags, cb_db_event; @@ -986,40 +1033,43 @@ void si_emit_cache_flush(struct si_context *sctx) */ tc_flags = 0; - if (rctx->flags & SI_CONTEXT_INV_L2_METADATA) { + if (flags & SI_CONTEXT_INV_L2_METADATA) { tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_MD_ACTION_ENA; } /* Ideally flush TC together with CB/DB. */ - if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) { + if (flags & SI_CONTEXT_INV_GLOBAL_L2) { /* Writeback and invalidate everything in L2 & L1. */ tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_WB_ACTION_ENA; /* Clear the flags. */ - rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 | - SI_CONTEXT_WRITEBACK_GLOBAL_L2 | - SI_CONTEXT_INV_VMEM_L1); - sctx->b.num_L2_invalidates++; + flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 | + SI_CONTEXT_WRITEBACK_GLOBAL_L2 | + SI_CONTEXT_INV_VMEM_L1); + sctx->num_L2_invalidates++; } /* Do the flush (enqueue the event and wait for it). */ va = sctx->wait_mem_scratch->gpu_address; sctx->wait_mem_number++; - si_gfx_write_event_eop(rctx, cb_db_event, tc_flags, - EOP_DATA_SEL_VALUE_32BIT, - sctx->wait_mem_scratch, va, - sctx->wait_mem_number, R600_NOT_QUERY); - si_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff); + si_cp_release_mem(sctx, cb_db_event, tc_flags, + EOP_DST_SEL_MEM, + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, + EOP_DATA_SEL_VALUE_32BIT, + sctx->wait_mem_scratch, va, + sctx->wait_mem_number, SI_NOT_QUERY); + si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff, + WAIT_REG_MEM_EQUAL); } /* Make sure ME is idle (it executes most packets) before continuing. * This prevents read-after-write hazards between PFP and ME. */ if (cp_coher_cntl || - (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH | + (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_INV_VMEM_L1 | SI_CONTEXT_INV_GLOBAL_L2 | SI_CONTEXT_WRITEBACK_GLOBAL_L2))) { @@ -1036,38 +1086,38 @@ void si_emit_cache_flush(struct si_context *sctx) * * SI-CIK don't support L2 write-back. */ - if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 || - (rctx->chip_class <= CIK && - (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) { + if (flags & SI_CONTEXT_INV_GLOBAL_L2 || + (sctx->chip_class <= CIK && + (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) { /* Invalidate L1 & L2. (L1 is always invalidated on SI) * WB must be set on VI+ when TC_ACTION is set. */ - si_emit_surface_sync(rctx, cp_coher_cntl | + si_emit_surface_sync(sctx, cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) | - S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI)); + S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI)); cp_coher_cntl = 0; - sctx->b.num_L2_invalidates++; + sctx->num_L2_invalidates++; } else { /* L1 invalidation and L2 writeback must be done separately, * because both operations can't be done together. */ - if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) { + if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) { /* WB = write-back * NC = apply to non-coherent MTYPEs * (i.e. MTYPE <= 1, which is what we use everywhere) * * WB doesn't work without NC. */ - si_emit_surface_sync(rctx, cp_coher_cntl | + si_emit_surface_sync(sctx, cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1)); cp_coher_cntl = 0; - sctx->b.num_L2_writebacks++; + sctx->num_L2_writebacks++; } - if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) { + if (flags & SI_CONTEXT_INV_VMEM_L1) { /* Invalidate per-CU VMEM L1. */ - si_emit_surface_sync(rctx, cp_coher_cntl | + si_emit_surface_sync(sctx, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1)); cp_coher_cntl = 0; } @@ -1075,19 +1125,19 @@ void si_emit_cache_flush(struct si_context *sctx) /* If TC flushes haven't cleared this... */ if (cp_coher_cntl) - si_emit_surface_sync(rctx, cp_coher_cntl); + si_emit_surface_sync(sctx, cp_coher_cntl); - if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) { + if (flags & SI_CONTEXT_START_PIPELINE_STATS) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); - } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) { + } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); } - rctx->flags = 0; + sctx->flags = 0; } static void si_get_draw_start_count(struct si_context *sctx, @@ -1104,7 +1154,7 @@ static void si_get_draw_start_count(struct si_context *sctx, unsigned *data; if (indirect->indirect_draw_count) { - data = pipe_buffer_map_range(&sctx->b.b, + data = pipe_buffer_map_range(&sctx->b, indirect->indirect_draw_count, indirect->indirect_draw_count_offset, sizeof(unsigned), @@ -1112,7 +1162,7 @@ static void si_get_draw_start_count(struct si_context *sctx, indirect_count = *data; - pipe_buffer_unmap(&sctx->b.b, transfer); + pipe_buffer_unmap(&sctx->b, transfer); } else { indirect_count = indirect->draw_count; } @@ -1123,7 +1173,7 @@ static void si_get_draw_start_count(struct si_context *sctx, } map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned); - data = pipe_buffer_map_range(&sctx->b.b, indirect->buffer, + data = pipe_buffer_map_range(&sctx->b, indirect->buffer, indirect->offset, map_size, PIPE_TRANSFER_READ, &transfer); @@ -1142,7 +1192,7 @@ static void si_get_draw_start_count(struct si_context *sctx, data += indirect->stride / sizeof(unsigned); } - pipe_buffer_unmap(&sctx->b.b, transfer); + pipe_buffer_unmap(&sctx->b, transfer); if (begin < end) { *start = begin; @@ -1159,13 +1209,33 @@ static void si_get_draw_start_count(struct si_context *sctx, static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info, unsigned skip_atom_mask) { + unsigned num_patches = 0; + /* Vega10/Raven scissor bug workaround. When any context register is + * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR + * registers must be written too. + */ + bool handle_scissor_bug = (sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) && + !si_is_atom_dirty(sctx, &sctx->atoms.s.scissors); + bool context_roll = false; /* set correctly for GFX9 only */ + + context_roll |= si_emit_rasterizer_prim_state(sctx); + if (sctx->tes_shader.cso) + context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches); + + if (handle_scissor_bug && + (info->count_from_stream_output || + sctx->dirty_atoms & si_atoms_that_always_roll_context() || + sctx->dirty_states & si_states_that_always_roll_context() || + si_prim_restart_index_changed(sctx, info))) + context_roll = true; + + sctx->context_roll_counter = 0; + /* Emit state atoms. */ unsigned mask = sctx->dirty_atoms & ~skip_atom_mask; - while (mask) { - struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)]; + while (mask) + sctx->atoms.array[u_bit_scan(&mask)].emit(sctx); - atom->emit(&sctx->b, atom); - } sctx->dirty_atoms &= skip_atom_mask; /* Emit states. */ @@ -1182,17 +1252,18 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i } sctx->dirty_states = 0; - /* Emit draw states. */ - unsigned num_patches = 0; + if (handle_scissor_bug && + (context_roll || sctx->context_roll_counter)) { + sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1; + sctx->atoms.s.scissors.emit(sctx); + } - si_emit_rasterizer_prim_state(sctx); - if (sctx->tes_shader.cso) - si_emit_derived_tess_state(sctx, info, &num_patches); + /* Emit draw states. */ si_emit_vs_state(sctx, info); si_emit_draw_registers(sctx, info, num_patches); } -void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) +static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) { struct si_context *sctx = (struct si_context *)ctx; struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; @@ -1216,27 +1287,22 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) return; } - if (unlikely(!sctx->vs_shader.cso)) { - assert(0); - return; - } - if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) { - assert(0); - return; - } - if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) { + if (unlikely(!sctx->vs_shader.cso || + !rs || + (!sctx->ps_shader.cso && !rs->rasterizer_discard) || + (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)))) { assert(0); return; } /* Recompute and re-emit the texture resource states if needed. */ - dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter); - if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) { - sctx->b.last_dirty_tex_counter = dirty_tex_counter; + dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter); + if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) { + sctx->last_dirty_tex_counter = dirty_tex_counter; sctx->framebuffer.dirty_cbufs |= ((1 << sctx->framebuffer.state.nr_cbufs) - 1); sctx->framebuffer.dirty_zsbuf = true; - si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); + si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); si_update_all_texture_descriptors(sctx); } @@ -1258,19 +1324,16 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) rast_prim = info->mode; if (rast_prim != sctx->current_rast_prim) { - bool old_is_poly = sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES; - bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES; - if (old_is_poly != new_is_poly) { - sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1; - si_mark_atom_dirty(sctx, &sctx->scissors.atom); - } + if (util_prim_is_points_or_lines(sctx->current_rast_prim) != + util_prim_is_points_or_lines(rast_prim)) + si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband); sctx->current_rast_prim = rast_prim; sctx->do_update_shaders = true; } if (sctx->tes_shader.cso && - (sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) { + sctx->screen->has_ls_vgpr_init_bug) { /* Determine whether the LS VGPR fix should be applied. * * It is only required when num input CPs > num output CPs, @@ -1314,7 +1377,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) if (index_size) { /* Translate or upload, if needed. */ /* 8-bit indices are supported on VI. */ - if (sctx->b.chip_class <= CIK && index_size == 1) { + if (sctx->chip_class <= CIK && index_size == 1) { unsigned start, count, start_offset, size, offset; void *ptr; @@ -1330,7 +1393,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) if (!indexbuf) return; - util_shorten_ubyte_elts_to_userptr(&sctx->b.b, info, 0, 0, + util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0, index_offset + start, count, ptr); @@ -1346,7 +1409,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) indexbuf = NULL; u_upload_data(ctx->stream_uploader, start_offset, info->count * index_size, - sctx->screen->b.info.tcc_cache_line_size, + sctx->screen->info.tcc_cache_line_size, (char*)info->index.user + start_offset, &index_offset, &indexbuf); if (!indexbuf) @@ -1354,11 +1417,11 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) /* info->start will be added by the drawing code */ index_offset -= start_offset; - } else if (sctx->b.chip_class <= CIK && + } else if (sctx->chip_class <= CIK && r600_resource(indexbuf)->TC_L2_dirty) { /* VI reads index buffers through TC L2, so it doesn't * need this. */ - sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; r600_resource(indexbuf)->TC_L2_dirty = false; } } @@ -1367,73 +1430,57 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) struct pipe_draw_indirect_info *indirect = info->indirect; /* Add the buffer size for memory checking in need_cs_space. */ - r600_context_add_resource_size(ctx, indirect->buffer); + si_context_add_resource_size(sctx, indirect->buffer); /* Indirect buffers use TC L2 on GFX9, but not older hw. */ - if (sctx->b.chip_class <= VI) { + if (sctx->chip_class <= VI) { if (r600_resource(indirect->buffer)->TC_L2_dirty) { - sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; r600_resource(indirect->buffer)->TC_L2_dirty = false; } if (indirect->indirect_draw_count && r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) { - sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false; } } } - si_need_cs_space(sctx); + si_need_gfx_cs_space(sctx); - /* Since we've called r600_context_add_resource_size for vertex buffers, + /* Since we've called si_context_add_resource_size for vertex buffers, * this must be called after si_need_cs_space, because we must let * need_cs_space flush before we add buffers to the buffer list. */ if (!si_upload_vertex_buffer_descriptors(sctx)) return; - /* GFX9 scissor bug workaround. This must be done before VPORT scissor - * registers are changed. There is also a more efficient but more - * involved alternative workaround. - */ - if (sctx->b.chip_class == GFX9 && - si_is_atom_dirty(sctx, &sctx->scissors.atom)) { - sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH; - si_emit_cache_flush(sctx); - } - /* Use optimal packet order based on whether we need to sync the pipeline. */ - if (unlikely(sctx->b.flags & (SI_CONTEXT_FLUSH_AND_INV_CB | + if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH))) { /* If we have to wait for idle, set all states first, so that all * SET packets are processed in parallel with previous draw calls. - * Then upload descriptors, set shader pointers, and draw, and - * prefetch at the end. This ensures that the time the CUs - * are idle is very short. (there are only SET_SH packets between - * the wait and the draw) + * Then draw and prefetch at the end. This ensures that the time + * the CUs are idle is very short. */ - struct r600_atom *shader_pointers = &sctx->shader_pointers.atom; - unsigned masked_atoms = 1u << shader_pointers->id; + unsigned masked_atoms = 0; - if (unlikely(sctx->b.flags & R600_CONTEXT_FLUSH_FOR_RENDER_COND)) - masked_atoms |= 1u << sctx->b.render_cond_atom.id; + if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND)) + masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond); - /* Emit all states except shader pointers and render condition. */ + if (!si_upload_graphics_shader_descriptors(sctx)) + return; + + /* Emit all states except possibly render condition. */ si_emit_all_states(sctx, info, masked_atoms); si_emit_cache_flush(sctx); - /* <-- CUs are idle here. */ - if (!si_upload_graphics_shader_descriptors(sctx)) - return; - /* Set shader pointers after descriptors are uploaded. */ - if (si_is_atom_dirty(sctx, shader_pointers)) - shader_pointers->emit(&sctx->b, NULL); - if (si_is_atom_dirty(sctx, &sctx->b.render_cond_atom)) - sctx->b.render_cond_atom.emit(&sctx->b, NULL); + if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) + sctx->atoms.s.render_cond.emit(sctx); sctx->dirty_atoms = 0; si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset); @@ -1442,152 +1489,115 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) /* Start prefetches after the draw has been started. Both will run * in parallel, but starting the draw first is more important. */ - if (sctx->b.chip_class >= CIK && sctx->prefetch_L2_mask) - cik_emit_prefetch_L2(sctx); + if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask) + cik_emit_prefetch_L2(sctx, false); } else { /* If we don't wait for idle, start prefetches first, then set * states, and draw at the end. */ - if (sctx->b.flags) + if (sctx->flags) si_emit_cache_flush(sctx); - if (sctx->b.chip_class >= CIK && sctx->prefetch_L2_mask) - cik_emit_prefetch_L2(sctx); + /* Only prefetch the API VS and VBO descriptors. */ + if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask) + cik_emit_prefetch_L2(sctx, true); if (!si_upload_graphics_shader_descriptors(sctx)) return; si_emit_all_states(sctx, info, 0); si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset); + + /* Prefetch the remaining shaders after the draw has been + * started. */ + if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask) + cik_emit_prefetch_L2(sctx, false); } if (unlikely(sctx->current_saved_cs)) { si_trace_emit(sctx); - si_log_draw_state(sctx, sctx->b.log); + si_log_draw_state(sctx, sctx->log); } /* Workaround for a VGT hang when streamout is enabled. * It must be done after drawing. */ - if ((sctx->b.family == CHIP_HAWAII || - sctx->b.family == CHIP_TONGA || - sctx->b.family == CHIP_FIJI) && - r600_get_strmout_en(&sctx->b)) { - sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC; + if ((sctx->family == CHIP_HAWAII || + sctx->family == CHIP_TONGA || + sctx->family == CHIP_FIJI) && + si_get_strmout_en(sctx)) { + sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC; } if (unlikely(sctx->decompression_enabled)) { - sctx->b.num_decompress_calls++; + sctx->num_decompress_calls++; } else { - sctx->b.num_draw_calls++; + sctx->num_draw_calls++; if (sctx->framebuffer.state.nr_cbufs > 1) - sctx->b.num_mrt_draw_calls++; + sctx->num_mrt_draw_calls++; if (info->primitive_restart) - sctx->b.num_prim_restart_calls++; + sctx->num_prim_restart_calls++; if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size)) - sctx->b.num_spill_draw_calls++; + sctx->num_spill_draw_calls++; } if (index_size && indexbuf != info->index.resource) pipe_resource_reference(&indexbuf, NULL); } -void si_draw_rectangle(struct blitter_context *blitter, - void *vertex_elements_cso, - blitter_get_vs_func get_vs, - int x1, int y1, int x2, int y2, - float depth, unsigned num_instances, - enum blitter_attrib_type type, - const union blitter_attrib *attrib) +static void +si_draw_rectangle(struct blitter_context *blitter, + void *vertex_elements_cso, + blitter_get_vs_func get_vs, + int x1, int y1, int x2, int y2, + float depth, unsigned num_instances, + enum blitter_attrib_type type, + const union blitter_attrib *attrib) { struct pipe_context *pipe = util_blitter_get_pipe(blitter); struct si_context *sctx = (struct si_context*)pipe; - struct pipe_viewport_state viewport; - struct pipe_resource *buf = NULL; - unsigned offset = 0; - float *vb; - - /* setup viewport */ - viewport.scale[0] = 1.0f; - viewport.scale[1] = 1.0f; - viewport.scale[2] = 1.0f; - viewport.translate[0] = 0.0f; - viewport.translate[1] = 0.0f; - viewport.translate[2] = 0.0f; - pipe->set_viewport_states(pipe, 0, 1, &viewport); - - /* Upload vertices. The hw rectangle has only 3 vertices, - * The 4th one is derived from the first 3. - * The vertex specification should match u_blitter's vertex element state. */ - u_upload_alloc(pipe->stream_uploader, 0, sizeof(float) * 24, - sctx->screen->b.info.tcc_cache_line_size, - &offset, &buf, (void**)&vb); - if (!buf) - return; - - vb[0] = x1; - vb[1] = y1; - vb[2] = depth; - vb[3] = 1; - - vb[8] = x1; - vb[9] = y2; - vb[10] = depth; - vb[11] = 1; - vb[16] = x2; - vb[17] = y1; - vb[18] = depth; - vb[19] = 1; + /* Pack position coordinates as signed int16. */ + sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) | + ((uint32_t)(y1 & 0xffff) << 16); + sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) | + ((uint32_t)(y2 & 0xffff) << 16); + sctx->vs_blit_sh_data[2] = fui(depth); switch (type) { case UTIL_BLITTER_ATTRIB_COLOR: - memcpy(vb+4, attrib->color, sizeof(float)*4); - memcpy(vb+12, attrib->color, sizeof(float)*4); - memcpy(vb+20, attrib->color, sizeof(float)*4); + memcpy(&sctx->vs_blit_sh_data[3], attrib->color, + sizeof(float)*4); break; - case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW: case UTIL_BLITTER_ATTRIB_TEXCOORD_XY: - vb[6] = vb[14] = vb[22] = attrib->texcoord.z; - vb[7] = vb[15] = vb[23] = attrib->texcoord.w; - /* fall through */ - vb[4] = attrib->texcoord.x1; - vb[5] = attrib->texcoord.y1; - vb[12] = attrib->texcoord.x1; - vb[13] = attrib->texcoord.y2; - vb[20] = attrib->texcoord.x2; - vb[21] = attrib->texcoord.y1; + case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW: + memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord, + sizeof(attrib->texcoord)); break; - default:; /* Nothing to do. */ + case UTIL_BLITTER_ATTRIB_NONE:; } - /* draw */ - struct pipe_vertex_buffer vbuffer = {}; - vbuffer.buffer.resource = buf; - vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */ - vbuffer.buffer_offset = offset; - - pipe->set_vertex_buffers(pipe, blitter->vb_slot, 1, &vbuffer); - pipe->bind_vs_state(pipe, get_vs(blitter)); - - if (sctx->vertex_elements != vertex_elements_cso) - pipe->bind_vertex_elements_state(pipe, vertex_elements_cso); + pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances)); struct pipe_draw_info info = {}; - info.mode = R600_PRIM_RECTANGLE_LIST; + info.mode = SI_PRIM_RECTANGLE_LIST; info.count = 3; info.instance_count = num_instances; + /* Don't set per-stage shader pointers for VS. */ + sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX); + sctx->vertex_buffer_pointer_dirty = false; + si_draw_vbo(pipe, &info); - pipe_resource_reference(&buf, NULL); } void si_trace_emit(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->b.gfx.cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address; uint32_t trace_id = ++sctx->current_saved_cs->trace_id; radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); - radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) | + radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM + : V_370_MEM_GRBM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME)); radeon_emit(cs, va); @@ -1596,6 +1606,15 @@ void si_trace_emit(struct si_context *sctx) radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id)); - if (sctx->b.log) - u_log_flush(sctx->b.log); + if (sctx->log) + u_log_flush(sctx->log); +} + +void si_init_draw_functions(struct si_context *sctx) +{ + sctx->b.draw_vbo = si_draw_vbo; + + sctx->blitter->draw_rectangle = si_draw_rectangle; + + si_init_ia_multi_vgt_param_table(sctx); }