X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state_draw.c;h=b6b789da0c223ed380fbaf2543fa38e69ba0e739;hb=e2e700f6053d0b16ba46e4d5c5b20e965fb2224e;hp=c7223d9412204fc28c2d32a404fcee336641eafc;hpb=b0c77a5f1d442b05888017dce8b1d522996ca3e5;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index c7223d94122..b6b789da0c2 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -761,7 +761,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw /* draw packet */ if (index_size) { - if (index_size != sctx->last_index_size) { + /* Register shadowing doesn't shadow INDEX_TYPE. */ + if (index_size != sctx->last_index_size || sctx->shadowed_regs) { unsigned index_type; /* index type */ @@ -880,7 +881,9 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw } else { int base_vertex; - if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN || + /* Register shadowing requires that we always emit PKT3_NUM_INSTANCES. */ + if (sctx->shadowed_regs || + sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN || sctx->last_instance_count != instance_count) { radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); radeon_emit(cs, instance_count); @@ -1864,7 +1867,8 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i /* Update NGG culling settings. */ if (sctx->ngg && !dispatch_prim_discard_cs && rast_prim == PIPE_PRIM_TRIANGLES && !sctx->gs_shader.cso && /* GS doesn't support NGG culling. */ - (sctx->screen->always_use_ngg_culling || + (sctx->screen->always_use_ngg_culling_all || + (sctx->tes_shader.cso && sctx->screen->always_use_ngg_culling_tess) || /* At least 1024 non-indexed vertices (8 subgroups) are needed * per draw call (no TES/GS) to enable NGG culling. */