X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fradeonsi%2Fsi_state_shaders.c;h=498deff502041412d7e142cd6e4c519eb7281c7a;hb=405262439857d86f03fe530fbc745457a234644d;hp=50c55fbfd583c96f1cd5213c2d0870cdff981651;hpb=95bc30275b3de7b856ffac9a1e438f7d246550dc;p=mesa.git diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 50c55fbfd58..498deff5020 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1,5 +1,6 @@ /* * Copyright 2012 Advanced Micro Devices, Inc. + * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -21,14 +22,11 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "si_pipe.h" -#include "sid.h" +#include "si_build_pm4.h" #include "gfx9d.h" -#include "radeon/r600_cs.h" #include "compiler/nir/nir_serialize.h" #include "tgsi/tgsi_parse.h" -#include "tgsi/tgsi_ureg.h" #include "util/hash_table.h" #include "util/crc32.h" #include "util/u_async_debug.h" @@ -46,7 +44,7 @@ * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its * size as integer. */ -static void *si_get_ir_binary(struct si_shader_selector *sel) +void *si_get_ir_binary(struct si_shader_selector *sel) { struct blob blob; unsigned ir_size; @@ -203,10 +201,9 @@ static bool si_load_shader_binary(struct si_shader *shader, void *binary) * * Returns false on failure, in which case the ir_binary should be freed. */ -static bool si_shader_cache_insert_shader(struct si_screen *sscreen, - void *ir_binary, - struct si_shader *shader, - bool insert_into_disk_cache) +bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary, + struct si_shader *shader, + bool insert_into_disk_cache) { void *hw_binary; struct hash_entry *entry; @@ -236,9 +233,8 @@ static bool si_shader_cache_insert_shader(struct si_screen *sscreen, return true; } -static bool si_shader_cache_load_shader(struct si_screen *sscreen, - void *ir_binary, - struct si_shader *shader) +bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary, + struct si_shader *shader) { struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary); @@ -456,7 +452,13 @@ static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader) else shader->pm4 = CALLOC_STRUCT(si_pm4_state); - return shader->pm4; + if (shader->pm4) { + shader->pm4->shader = shader; + return shader->pm4; + } else { + fprintf(stderr, "radeonsi: Failed to create pm4 state.\n"); + return NULL; + } } static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs) @@ -556,6 +558,18 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) } } +static void si_emit_shader_es(struct si_context *sctx) +{ + struct si_shader *shader = sctx->queued.named.es->shader; + + if (!shader) + return; + + radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, + SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, + shader->selector->esgs_itemsize / 4); +} + static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) { struct si_pm4_state *pm4; @@ -570,6 +584,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) if (!pm4) return; + pm4->atom.emit = si_emit_shader_es; va = shader->bo->gpu_address; si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); @@ -585,8 +600,6 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0; - si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE, - shader->selector->esgs_itemsize / 4); si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40)); si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES, @@ -606,6 +619,30 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4); } +static unsigned si_conv_prim_to_gs_out(unsigned mode) +{ + static const int prim_conv[] = { + [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST, + [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, + [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, + [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, + [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, + [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, + [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, + [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, + [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, + [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, + [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, + [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, + [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, + [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, + [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST, + }; + assert(mode < ARRAY_SIZE(prim_conv)); + + return prim_conv[mode]; +} + struct gfx9_gs_info { unsigned es_verts_per_subgroup; unsigned gs_prims_per_subgroup; @@ -637,8 +674,6 @@ static void gfx9_get_gs_info(struct si_shader_selector *es, unsigned max_gs_prims, gs_prims; unsigned min_es_verts, es_verts, worst_case_es_verts; - assert(gs_num_invocations <= 32); /* GL maximum */ - if (uses_adjacency || gs_num_invocations > 1) max_gs_prims = 127 / gs_num_invocations; else @@ -714,6 +749,62 @@ static void gfx9_get_gs_info(struct si_shader_selector *es, assert(out->max_prims_per_subgroup <= max_out_prims); } +static void si_emit_shader_gs(struct si_context *sctx) +{ + struct si_shader *shader = sctx->queued.named.gs->shader; + if (!shader) + return; + + /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2 + * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */ + radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, + SI_TRACKED_VGT_GSVS_RING_OFFSET_1, + shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, + shader->ctx_reg.gs.vgt_gsvs_ring_offset_2, + shader->ctx_reg.gs.vgt_gsvs_ring_offset_3, + shader->ctx_reg.gs.vgt_gs_out_prim_type); + + + /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */ + radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE, + SI_TRACKED_VGT_GSVS_RING_ITEMSIZE, + shader->ctx_reg.gs.vgt_gsvs_ring_itemsize); + + /* R_028B38_VGT_GS_MAX_VERT_OUT */ + radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, + SI_TRACKED_VGT_GS_MAX_VERT_OUT, + shader->ctx_reg.gs.vgt_gs_max_vert_out); + + /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1 + * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */ + radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, + SI_TRACKED_VGT_GS_VERT_ITEMSIZE, + shader->ctx_reg.gs.vgt_gs_vert_itemsize, + shader->ctx_reg.gs.vgt_gs_vert_itemsize_1, + shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, + shader->ctx_reg.gs.vgt_gs_vert_itemsize_3); + + /* R_028B90_VGT_GS_INSTANCE_CNT */ + radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, + SI_TRACKED_VGT_GS_INSTANCE_CNT, + shader->ctx_reg.gs.vgt_gs_instance_cnt); + + if (sctx->chip_class >= GFX9) { + /* R_028A44_VGT_GS_ONCHIP_CNTL */ + radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, + SI_TRACKED_VGT_GS_ONCHIP_CNTL, + shader->ctx_reg.gs.vgt_gs_onchip_cntl); + /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */ + radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, + SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, + shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup); + /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */ + radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, + SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, + shader->ctx_reg.gs.vgt_esgs_ring_itemsize); + } +} + static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) { struct si_shader_selector *sel = shader->selector; @@ -728,31 +819,38 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) if (!pm4) return; + pm4->atom.emit = si_emit_shader_gs; + offset = num_components[0] * sel->gs_max_out_vertices; - si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset); + shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset; + if (max_stream >= 1) offset += num_components[1] * sel->gs_max_out_vertices; - si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset); + shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset; + if (max_stream >= 2) offset += num_components[2] * sel->gs_max_out_vertices; - si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset); + shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset; + + shader->ctx_reg.gs.vgt_gs_out_prim_type = + si_conv_prim_to_gs_out(sel->gs_output_prim); + if (max_stream >= 3) offset += num_components[3] * sel->gs_max_out_vertices; - si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset); + shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset; /* The GSVS_RING_ITEMSIZE register takes 15 bits */ assert(offset < (1 << 15)); - si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices); + shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices; - si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]); - si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0); - si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0); - si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0); + shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0]; + shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0; + shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0; + shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0; - si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, - S_028B90_CNT(MIN2(gs_num_invocations, 127)) | - S_028B90_ENABLE(gs_num_invocations > 0)); + shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) | + S_028B90_ENABLE(gs_num_invocations > 0); va = shader->bo->gpu_address; si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY); @@ -808,14 +906,14 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) S_00B22C_LDS_SIZE(gs_info.lds_size) | S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0)); - si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL, - S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) | - S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) | - S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup)); - si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, - S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup)); - si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE, - shader->key.part.gs.es->esgs_itemsize / 4); + shader->ctx_reg.gs.vgt_gs_onchip_cntl = + S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) | + S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) | + S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup); + shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup = + S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup); + shader->ctx_reg.gs.vgt_esgs_ring_itemsize = + shader->key.part.gs.es->esgs_itemsize / 4; if (es_type == PIPE_SHADER_TESS_EVAL) si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4); @@ -1174,7 +1272,8 @@ static void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key) { - if (!sctx->vertex_elements) + if (!sctx->vertex_elements || + vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) return; prolog_key->instance_divisor_is_one = @@ -1224,12 +1323,13 @@ static void si_shader_selector_key_hw_vs(struct si_context *sctx, } /* Find out which VS outputs aren't used by the PS. */ - uint64_t outputs_written = vs->outputs_written; + uint64_t outputs_written = vs->outputs_written_before_ps; uint64_t inputs_read = 0; - /* ignore POSITION, PSIZE */ - outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) | - (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0)))); + /* Ignore outputs that are not passed from VS to PS. */ + outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) | + (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) | + (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true))); if (!ps_disabled) { inputs_read = ps->inputs_read; @@ -1265,7 +1365,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, } break; case PIPE_SHADER_TESS_CTRL: - if (sctx->b.chip_class >= GFX9) { + if (sctx->chip_class >= GFX9) { si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.tcs.ls_prolog); key->part.tcs.ls = sctx->vs_shader.cso; @@ -1306,7 +1406,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, } break; case PIPE_SHADER_GEOMETRY: - if (sctx->b.chip_class >= GFX9) { + if (sctx->chip_class >= GFX9) { if (sctx->tes_shader.cso) { key->part.gs.es = sctx->tes_shader.cso; } else { @@ -1380,7 +1480,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, * to the range supported by the type if a channel has less * than 16 bits and the export format is 16_ABGR. */ - if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) { + if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) { key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8; key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10; } @@ -1392,67 +1492,63 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, key->part.ps.epilog.color_is_int10 &= sel->info.colors_written; } - if (rs) { - bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES && - sctx->current_rast_prim <= PIPE_PRIM_POLYGON) || - sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY; - bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS; + bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim); + bool is_line = util_prim_is_lines(sctx->current_rast_prim); - key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read; - key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read; + key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read; + key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read; - if (sctx->queued.named.blend) { - key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one && - rs->multisample_enable; - } + if (sctx->queued.named.blend) { + key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one && + rs->multisample_enable; + } - key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly; - key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) || - (is_line && rs->line_smooth)) && - sctx->framebuffer.nr_samples <= 1; - key->part.ps.epilog.clamp_color = rs->clamp_fragment_color; + key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly; + key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) || + (is_line && rs->line_smooth)) && + sctx->framebuffer.nr_samples <= 1; + key->part.ps.epilog.clamp_color = rs->clamp_fragment_color; - if (sctx->ps_iter_samples > 1 && - sel->info.reads_samplemask) { - key->part.ps.prolog.samplemask_log_ps_iter = - util_logbase2(util_next_power_of_two(sctx->ps_iter_samples)); - } + if (sctx->ps_iter_samples > 1 && + sel->info.reads_samplemask) { + key->part.ps.prolog.samplemask_log_ps_iter = + util_logbase2(sctx->ps_iter_samples); + } - if (rs->force_persample_interp && - rs->multisample_enable && - sctx->framebuffer.nr_samples > 1 && - sctx->ps_iter_samples > 1) { - key->part.ps.prolog.force_persp_sample_interp = - sel->info.uses_persp_center || - sel->info.uses_persp_centroid; - - key->part.ps.prolog.force_linear_sample_interp = - sel->info.uses_linear_center || - sel->info.uses_linear_centroid; - } else if (rs->multisample_enable && - sctx->framebuffer.nr_samples > 1) { - key->part.ps.prolog.bc_optimize_for_persp = - sel->info.uses_persp_center && - sel->info.uses_persp_centroid; - key->part.ps.prolog.bc_optimize_for_linear = - sel->info.uses_linear_center && - sel->info.uses_linear_centroid; - } else { - /* Make sure SPI doesn't compute more than 1 pair - * of (i,j), which is the optimization here. */ - key->part.ps.prolog.force_persp_center_interp = - sel->info.uses_persp_center + - sel->info.uses_persp_centroid + - sel->info.uses_persp_sample > 1; - - key->part.ps.prolog.force_linear_center_interp = - sel->info.uses_linear_center + - sel->info.uses_linear_centroid + - sel->info.uses_linear_sample > 1; - - if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]) - key->mono.u.ps.interpolate_at_sample_force_center = 1; - } + if (rs->force_persample_interp && + rs->multisample_enable && + sctx->framebuffer.nr_samples > 1 && + sctx->ps_iter_samples > 1) { + key->part.ps.prolog.force_persp_sample_interp = + sel->info.uses_persp_center || + sel->info.uses_persp_centroid; + + key->part.ps.prolog.force_linear_sample_interp = + sel->info.uses_linear_center || + sel->info.uses_linear_centroid; + } else if (rs->multisample_enable && + sctx->framebuffer.nr_samples > 1) { + key->part.ps.prolog.bc_optimize_for_persp = + sel->info.uses_persp_center && + sel->info.uses_persp_centroid; + key->part.ps.prolog.bc_optimize_for_linear = + sel->info.uses_linear_center && + sel->info.uses_linear_centroid; + } else { + /* Make sure SPI doesn't compute more than 1 pair + * of (i,j), which is the optimization here. */ + key->part.ps.prolog.force_persp_center_interp = + sel->info.uses_persp_center + + sel->info.uses_persp_centroid + + sel->info.uses_persp_sample > 1; + + key->part.ps.prolog.force_linear_center_interp = + sel->info.uses_linear_center + + sel->info.uses_linear_centroid + + sel->info.uses_linear_sample > 1; + + if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]) + key->mono.u.ps.interpolate_at_sample_force_center = 1; } key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx); @@ -1464,7 +1560,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, /* 1D textures are allocated and used as 2D on GFX9. */ key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1; - key->mono.u.ps.fbfetch_is_1D = sctx->b.chip_class != GFX9 && + key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 && (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY); key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY || @@ -1489,28 +1585,28 @@ static void si_build_shader_variant(struct si_shader *shader, { struct si_shader_selector *sel = shader->selector; struct si_screen *sscreen = sel->screen; - LLVMTargetMachineRef tm; + struct ac_llvm_compiler *compiler; struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug; int r; if (thread_index >= 0) { if (low_priority) { - assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority)); - tm = sscreen->tm_low_priority[thread_index]; + assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp)); + compiler = &sscreen->compiler_lowp[thread_index]; } else { - assert(thread_index < ARRAY_SIZE(sscreen->tm)); - tm = sscreen->tm[thread_index]; + assert(thread_index < ARRAY_SIZE(sscreen->compiler)); + compiler = &sscreen->compiler[thread_index]; } if (!debug->async) debug = NULL; } else { assert(!low_priority); - tm = shader->compiler_ctx_state.tm; + compiler = shader->compiler_ctx_state.compiler; } - r = si_shader_create(sscreen, tm, shader, debug); + r = si_shader_create(sscreen, compiler, shader, debug); if (unlikely(r)) { - R600_ERR("Failed to build shader variant (type=%u) %d\n", + PRINT_ERR("Failed to build shader variant (type=%u) %d\n", sel->type, r); shader->compilation_failed = true; return; @@ -1560,10 +1656,10 @@ static bool si_check_missing_main_part(struct si_screen *sscreen, main_part->selector = sel; main_part->key.as_es = key->as_es; main_part->key.as_ls = key->as_ls; + main_part->is_monolithic = false; - if (si_compile_tgsi_shader(sscreen, compiler_state->tm, - main_part, false, - &compiler_state->debug) != 0) { + if (si_compile_tgsi_shader(sscreen, compiler_state->compiler, + main_part, &compiler_state->debug) != 0) { FREE(main_part); return false; } @@ -1836,13 +1932,13 @@ static void si_init_shader_selector_async(void *job, int thread_index) { struct si_shader_selector *sel = (struct si_shader_selector *)job; struct si_screen *sscreen = sel->screen; - LLVMTargetMachineRef tm; + struct ac_llvm_compiler *compiler; struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug; assert(!debug->debug_message || debug->async); assert(thread_index >= 0); - assert(thread_index < ARRAY_SIZE(sscreen->tm)); - tm = sscreen->tm[thread_index]; + assert(thread_index < ARRAY_SIZE(sscreen->compiler)); + compiler = &sscreen->compiler[thread_index]; /* Compile the main shader part for use with a prolog and/or epilog. * If this fails, the driver will try to compile a monolithic shader @@ -1862,6 +1958,7 @@ static void si_init_shader_selector_async(void *job, int thread_index) util_queue_fence_init(&shader->ready); shader->selector = sel; + shader->is_monolithic = false; si_parse_next_shader_property(&sel->info, sel->so.num_outputs != 0, &shader->key); @@ -1880,7 +1977,7 @@ static void si_init_shader_selector_async(void *job, int thread_index) mtx_unlock(&sscreen->shader_cache_mutex); /* Compile the shader if it hasn't been loaded from the cache. */ - if (si_compile_tgsi_shader(sscreen, tm, shader, false, + if (si_compile_tgsi_shader(sscreen, compiler, shader, debug) != 0) { FREE(shader); FREE(ir_binary); @@ -1928,8 +2025,8 @@ static void si_init_shader_selector_async(void *job, int thread_index) break; /* fall through */ default: - id = si_shader_io_get_unique_index(name, index); - sel->outputs_written &= ~(1ull << id); + id = si_shader_io_get_unique_index(name, index, true); + sel->outputs_written_before_ps &= ~(1ull << id); break; case TGSI_SEMANTIC_POSITION: /* ignore these */ case TGSI_SEMANTIC_PSIZE: @@ -1943,7 +2040,7 @@ static void si_init_shader_selector_async(void *job, int thread_index) /* The GS copy shader is always pre-compiled. */ if (sel->type == PIPE_SHADER_GEOMETRY) { - sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug); + sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug); if (!sel->gs_copy_shader) { fprintf(stderr, "radeonsi: can't create GS copy shader\n"); return; @@ -1953,6 +2050,34 @@ static void si_init_shader_selector_async(void *job, int thread_index) } } +void si_schedule_initial_compile(struct si_context *sctx, unsigned processor, + struct util_queue_fence *ready_fence, + struct si_compiler_ctx_state *compiler_ctx_state, + void *job, util_queue_execute_func execute) +{ + util_queue_fence_init(ready_fence); + + struct util_async_debug_callback async_debug; + bool wait = + (sctx->debug.debug_message && !sctx->debug.async) || + sctx->is_debug || + si_can_dump_shader(sctx->screen, processor); + + if (wait) { + u_async_debug_init(&async_debug); + compiler_ctx_state->debug = async_debug.base; + } + + util_queue_add_job(&sctx->screen->shader_compiler_queue, job, + ready_fence, execute, NULL); + + if (wait) { + util_queue_fence_wait(ready_fence); + u_async_debug_drain(&async_debug, &sctx->debug); + u_async_debug_cleanup(&async_debug); + } +} + /* Return descriptor slot usage masks from the given shader info. */ void si_get_active_slot_masks(const struct tgsi_shader_info *info, uint32_t *const_and_shader_buffers, @@ -2102,20 +2227,30 @@ static void *si_create_shader_selector(struct pipe_context *ctx, /* fall through */ default: sel->outputs_written |= - 1ull << si_shader_io_get_unique_index(name, index); + 1ull << si_shader_io_get_unique_index(name, index, false); + sel->outputs_written_before_ps |= + 1ull << si_shader_io_get_unique_index(name, index, true); break; - case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */ case TGSI_SEMANTIC_EDGEFLAG: break; } } sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16; + sel->lshs_vertex_stride = sel->esgs_itemsize; + + /* Add 1 dword to reduce LDS bank conflicts, so that each vertex + * will start on a different bank. (except for the maximum 32*16). + */ + if (sel->lshs_vertex_stride < 32*16) + sel->lshs_vertex_stride += 4; /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank * conflicts, i.e. each vertex will start at a different bank. */ - if (sctx->b.chip_class >= GFX9) + if (sctx->chip_class >= GFX9) sel->esgs_itemsize += 4; + + assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0); break; case PIPE_SHADER_FRAGMENT: @@ -2131,7 +2266,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx, /* fall through */ default: sel->inputs_read |= - 1ull << si_shader_io_get_unique_index(name, index); + 1ull << si_shader_io_get_unique_index(name, index, true); break; case TGSI_SEMANTIC_PCOORD: /* ignore this */ break; @@ -2218,29 +2353,10 @@ static void *si_create_shader_selector(struct pipe_context *ctx, } (void) mtx_init(&sel->mutex, mtx_plain); - util_queue_fence_init(&sel->ready); - - struct util_async_debug_callback async_debug; - bool wait = - (sctx->debug.debug_message && !sctx->debug.async) || - sctx->is_debug || - si_can_dump_shader(sscreen, sel->info.processor); - - if (wait) { - u_async_debug_init(&async_debug); - sel->compiler_ctx_state.debug = async_debug.base; - } - - util_queue_add_job(&sscreen->shader_compiler_queue, sel, - &sel->ready, si_init_shader_selector_async, - NULL); - - if (wait) { - util_queue_fence_wait(&sel->ready); - u_async_debug_drain(&async_debug, &sctx->debug); - u_async_debug_cleanup(&async_debug); - } + si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready, + &sel->compiler_ctx_state, sel, + si_init_shader_selector_async); return sel; } @@ -2273,7 +2389,7 @@ static void si_update_clip_regs(struct si_context *sctx, !next_hw_vs_variant || old_hw_vs_variant->key.opt.clip_disable != next_hw_vs_variant->key.opt.clip_disable)) - si_mark_atom_dirty(sctx, &sctx->clip_regs); + si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs); } static void si_update_common_shader_state(struct si_context *sctx) @@ -2429,14 +2545,14 @@ static void si_bind_ps_shader(struct pipe_context *ctx, void *state) if (!old_sel || old_sel->info.colors_written != sel->info.colors_written) - si_mark_atom_dirty(sctx, &sctx->cb_render_state); + si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state); if (sctx->screen->has_out_of_order_rast && (!old_sel || old_sel->info.writes_memory != sel->info.writes_memory || old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] != sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])) - si_mark_atom_dirty(sctx, &sctx->msaa_config); + si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config); } si_set_active_descriptors_for_shader(sctx, sel); si_update_ps_colorbuf0_slot(sctx); @@ -2455,10 +2571,10 @@ static void si_delete_shader(struct si_context *sctx, struct si_shader *shader) switch (shader->selector->type) { case PIPE_SHADER_VERTEX: if (shader->key.as_ls) { - assert(sctx->b.chip_class <= VI); + assert(sctx->chip_class <= VI); si_pm4_delete_state(sctx, ls, shader->pm4); } else if (shader->key.as_es) { - assert(sctx->b.chip_class <= VI); + assert(sctx->chip_class <= VI); si_pm4_delete_state(sctx, es, shader->pm4); } else { si_pm4_delete_state(sctx, vs, shader->pm4); @@ -2469,7 +2585,7 @@ static void si_delete_shader(struct si_context *sctx, struct si_shader *shader) break; case PIPE_SHADER_TESS_EVAL: if (shader->key.as_es) { - assert(sctx->b.chip_class <= VI); + assert(sctx->chip_class <= VI); si_pm4_delete_state(sctx, es, shader->pm4); } else { si_pm4_delete_state(sctx, vs, shader->pm4); @@ -2599,29 +2715,27 @@ static unsigned si_get_ps_input_cntl(struct si_context *sctx, return ps_input_cntl; } -static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom) +static void si_emit_spi_map(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->b.gfx_cs; struct si_shader *ps = sctx->ps_shader.current; struct si_shader *vs = si_get_vs_state(sctx); struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL; unsigned i, num_interp, num_written = 0, bcol_interp[2]; + unsigned spi_ps_input_cntl[32]; if (!ps || !ps->selector->info.num_inputs) return; num_interp = si_get_ps_num_interp(ps); assert(num_interp > 0); - radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp); for (i = 0; i < psinfo->num_inputs; i++) { unsigned name = psinfo->input_semantic_name[i]; unsigned index = psinfo->input_semantic_index[i]; unsigned interpolate = psinfo->input_interpolate[i]; - radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index, - interpolate)); - num_written++; + spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name, + index, interpolate); if (name == TGSI_SEMANTIC_COLOR) { assert(index < ARRAY_SIZE(bcol_interp)); @@ -2636,12 +2750,19 @@ static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom) if (!(psinfo->colors_read & (0xf << (i * 4)))) continue; - radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol, - i, bcol_interp[i])); - num_written++; + spi_ps_input_cntl[num_written++] = + si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]); + } } assert(num_interp == num_written); + + /* R_028644_SPI_PS_INPUT_CNTL_0 */ + /* Dota 2: Only ~16% of SPI map updates set different values. */ + /* Talos: Only ~9% of SPI map updates set different values. */ + radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0, + spi_ps_input_cntl, + sctx->tracked_regs.spi_ps_input_cntl, num_interp); } /** @@ -2680,7 +2801,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16. * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). */ - unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se; + unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se; unsigned alignment = 256 * num_se; /* The maximum size is 63.999 MB per SE. */ unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; @@ -2707,7 +2828,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) * * GFX9 doesn't have the ESGS ring. */ - bool update_esgs = sctx->b.chip_class <= VI && + bool update_esgs = sctx->chip_class <= VI && esgs_ring_size && (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size); @@ -2721,8 +2842,8 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) if (update_esgs) { pipe_resource_reference(&sctx->esgs_ring, NULL); sctx->esgs_ring = - si_aligned_buffer_create(sctx->b.b.screen, - R600_RESOURCE_FLAG_UNMAPPABLE, + pipe_aligned_buffer_create(sctx->b.screen, + SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT, esgs_ring_size, alignment); if (!sctx->esgs_ring) @@ -2732,8 +2853,8 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) if (update_gsvs) { pipe_resource_reference(&sctx->gsvs_ring, NULL); sctx->gsvs_ring = - si_aligned_buffer_create(sctx->b.b.screen, - R600_RESOURCE_FLAG_UNMAPPABLE, + pipe_aligned_buffer_create(sctx->b.screen, + SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT, gsvs_ring_size, alignment); if (!sctx->gsvs_ring) @@ -2745,9 +2866,9 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) if (!pm4) return false; - if (sctx->b.chip_class >= CIK) { + if (sctx->chip_class >= CIK) { if (sctx->esgs_ring) { - assert(sctx->b.chip_class <= VI); + assert(sctx->chip_class <= VI); si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256); } @@ -2774,21 +2895,21 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) } /* Flush the context to re-emit both init_config states. */ - sctx->b.initial_gfx_cs_size = 0; /* force flush */ - si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL); + sctx->initial_gfx_cs_size = 0; /* force flush */ + si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); /* Set ring bindings. */ if (sctx->esgs_ring) { - assert(sctx->b.chip_class <= VI); - si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS, + assert(sctx->chip_class <= VI); + si_set_ring_buffer(sctx, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true, true, 4, 64, 0); - si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS, + si_set_ring_buffer(sctx, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false, false, 0, 0, 0); } if (sctx->gsvs_ring) { - si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS, + si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false, false, 0, 0, 0); } @@ -2973,16 +3094,16 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx) /* Create a bigger scratch buffer */ r600_resource_reference(&sctx->scratch_buffer, NULL); - sctx->scratch_buffer = (struct r600_resource*) + sctx->scratch_buffer = si_aligned_buffer_create(&sctx->screen->b, - R600_RESOURCE_FLAG_UNMAPPABLE, + SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT, scratch_needed_size, 256); if (!sctx->scratch_buffer) return false; - si_mark_atom_dirty(sctx, &sctx->scratch_state); - si_context_add_resource_size(&sctx->b.b, + si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state); + si_context_add_resource_size(sctx, &sctx->scratch_buffer->b.b); } @@ -2998,7 +3119,7 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx) S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10); if (spi_tmpring_size != sctx->spi_tmpring_size) { sctx->spi_tmpring_size = spi_tmpring_size; - si_mark_atom_dirty(sctx, &sctx->scratch_state); + si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state); } return true; } @@ -3010,8 +3131,8 @@ static void si_init_tess_factor_ring(struct si_context *sctx) /* The address must be aligned to 2^19, because the shader only * receives the high 13 bits. */ - sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen, - R600_RESOURCE_FLAG_32BIT, + sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen, + SI_RESOURCE_FLAG_32BIT, PIPE_USAGE_DEFAULT, sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, @@ -3028,12 +3149,12 @@ static void si_init_tess_factor_ring(struct si_context *sctx) sctx->screen->tess_offchip_ring_size; /* Append these registers to the init config state. */ - if (sctx->b.chip_class >= CIK) { + if (sctx->chip_class >= CIK) { si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4)); si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8); - if (sctx->b.chip_class >= GFX9) + if (sctx->chip_class >= GFX9) si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(factor_va >> 40)); si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM, @@ -3051,40 +3172,8 @@ static void si_init_tess_factor_ring(struct si_context *sctx) * This is done only once in a lifetime of a context. */ si_pm4_upload_indirect_buffer(sctx, sctx->init_config); - sctx->b.initial_gfx_cs_size = 0; /* force flush */ - si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL); -} - -/** - * This is used when TCS is NULL in the VS->TCS->TES chain. In this case, - * VS passes its outputs to TES directly, so the fixed-function shader only - * has to write TESSOUTER and TESSINNER. - */ -static void si_generate_fixed_func_tcs(struct si_context *sctx) -{ - struct ureg_src outer, inner; - struct ureg_dst tessouter, tessinner; - struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL); - - if (!ureg) - return; /* if we get here, we're screwed */ - - assert(!sctx->fixed_func_tcs_shader.cso); - - outer = ureg_DECL_system_value(ureg, - TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0); - inner = ureg_DECL_system_value(ureg, - TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0); - - tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0); - tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0); - - ureg_MOV(ureg, tessouter, outer); - ureg_MOV(ureg, tessinner, inner); - ureg_END(ureg); - - sctx->fixed_func_tcs_shader.cso = - ureg_create_shader_and_destroy(ureg, &sctx->b.b); + sctx->initial_gfx_cs_size = 0; /* force flush */ + si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); } static void si_update_vgt_shader_config(struct si_context *sctx) @@ -3115,7 +3204,7 @@ static void si_update_vgt_shader_config(struct si_context *sctx) S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); } - if (sctx->b.chip_class >= GFX9) + if (sctx->chip_class >= GFX9) stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages); @@ -3135,7 +3224,7 @@ bool si_update_shaders(struct si_context *sctx) old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0; int r; - compiler_state.tm = sctx->tm; + compiler_state.compiler = &sctx->compiler; compiler_state.debug = sctx->debug; compiler_state.is_debug_context = sctx->is_debug; @@ -3148,7 +3237,7 @@ bool si_update_shaders(struct si_context *sctx) } /* VS as LS */ - if (sctx->b.chip_class <= VI) { + if (sctx->chip_class <= VI) { r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state); if (r) @@ -3164,7 +3253,8 @@ bool si_update_shaders(struct si_context *sctx) si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4); } else { if (!sctx->fixed_func_tcs_shader.cso) { - si_generate_fixed_func_tcs(sctx); + sctx->fixed_func_tcs_shader.cso = + si_create_fixed_func_tcs(sctx); if (!sctx->fixed_func_tcs_shader.cso) return false; } @@ -3179,7 +3269,7 @@ bool si_update_shaders(struct si_context *sctx) if (sctx->gs_shader.cso) { /* TES as ES */ - if (sctx->b.chip_class <= VI) { + if (sctx->chip_class <= VI) { r = si_shader_select(ctx, &sctx->tes_shader, &compiler_state); if (r) @@ -3195,7 +3285,7 @@ bool si_update_shaders(struct si_context *sctx) si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4); } } else if (sctx->gs_shader.cso) { - if (sctx->b.chip_class <= VI) { + if (sctx->chip_class <= VI) { /* VS as ES */ r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state); @@ -3228,14 +3318,14 @@ bool si_update_shaders(struct si_context *sctx) return false; } else { si_pm4_bind_state(sctx, gs, NULL); - if (sctx->b.chip_class <= VI) + if (sctx->chip_class <= VI) si_pm4_bind_state(sctx, es, NULL); } si_update_vgt_shader_config(sctx); if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable) - si_mark_atom_dirty(sctx, &sctx->clip_regs); + si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs); if (sctx->ps_shader.cso) { unsigned db_shader_control; @@ -3254,7 +3344,7 @@ bool si_update_shaders(struct si_context *sctx) sctx->flatshade != rs->flatshade) { sctx->sprite_coord_enable = rs->sprite_coord_enable; sctx->flatshade = rs->flatshade; - si_mark_atom_dirty(sctx, &sctx->spi_map); + si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map); } if (sctx->screen->rbplus_allowed && @@ -3262,24 +3352,24 @@ bool si_update_shaders(struct si_context *sctx) (!old_ps || old_spi_shader_col_format != sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format)) - si_mark_atom_dirty(sctx, &sctx->cb_render_state); + si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state); if (sctx->ps_db_shader_control != db_shader_control) { sctx->ps_db_shader_control = db_shader_control; - si_mark_atom_dirty(sctx, &sctx->db_render_state); + si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); if (sctx->screen->dpbb_allowed) - si_mark_atom_dirty(sctx, &sctx->dpbb_state); + si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state); } if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) { sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing; - si_mark_atom_dirty(sctx, &sctx->msaa_config); + si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config); - if (sctx->b.chip_class == SI) - si_mark_atom_dirty(sctx, &sctx->db_render_state); + if (sctx->chip_class == SI) + si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); if (sctx->framebuffer.nr_samples <= 1) - si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom); + si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs); } } @@ -3293,7 +3383,7 @@ bool si_update_shaders(struct si_context *sctx) return false; } - if (sctx->b.chip_class >= CIK) { + if (sctx->chip_class >= CIK) { if (si_pm4_state_enabled_and_changed(sctx, ls)) sctx->prefetch_L2_mask |= SI_PREFETCH_LS; else if (!sctx->queued.named.ls) @@ -3329,107 +3419,40 @@ bool si_update_shaders(struct si_context *sctx) return true; } -static void si_emit_scratch_state(struct si_context *sctx, - struct r600_atom *atom) +static void si_emit_scratch_state(struct si_context *sctx) { - struct radeon_winsys_cs *cs = sctx->b.gfx_cs; + struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size); if (sctx->scratch_buffer) { - radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->scratch_buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_SCRATCH_BUFFER); } } -void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type, - unsigned num_layers) -{ - struct pipe_context *pipe = &sctx->b.b; - unsigned vs_blit_property; - void **vs; - - switch (type) { - case UTIL_BLITTER_ATTRIB_NONE: - vs = num_layers > 1 ? &sctx->vs_blit_pos_layered : - &sctx->vs_blit_pos; - vs_blit_property = SI_VS_BLIT_SGPRS_POS; - break; - case UTIL_BLITTER_ATTRIB_COLOR: - vs = num_layers > 1 ? &sctx->vs_blit_color_layered : - &sctx->vs_blit_color; - vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR; - break; - case UTIL_BLITTER_ATTRIB_TEXCOORD_XY: - case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW: - assert(num_layers == 1); - vs = &sctx->vs_blit_texcoord; - vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD; - break; - default: - assert(0); - return NULL; - } - if (*vs) - return *vs; - - struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX); - if (!ureg) - return NULL; - - /* Tell the shader to load VS inputs from SGPRs: */ - ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property); - ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true); - - /* This is just a pass-through shader with 1-3 MOV instructions. */ - ureg_MOV(ureg, - ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0), - ureg_DECL_vs_input(ureg, 0)); - - if (type != UTIL_BLITTER_ATTRIB_NONE) { - ureg_MOV(ureg, - ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0), - ureg_DECL_vs_input(ureg, 1)); - } - - if (num_layers > 1) { - struct ureg_src instance_id = - ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0); - struct ureg_dst layer = - ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0); - - ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X), - ureg_scalar(instance_id, TGSI_SWIZZLE_X)); - } - ureg_END(ureg); - - *vs = ureg_create_shader_and_destroy(ureg, pipe); - return *vs; -} - void si_init_shader_functions(struct si_context *sctx) { - si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map); - si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state, - si_emit_scratch_state); - - sctx->b.b.create_vs_state = si_create_shader_selector; - sctx->b.b.create_tcs_state = si_create_shader_selector; - sctx->b.b.create_tes_state = si_create_shader_selector; - sctx->b.b.create_gs_state = si_create_shader_selector; - sctx->b.b.create_fs_state = si_create_shader_selector; - - sctx->b.b.bind_vs_state = si_bind_vs_shader; - sctx->b.b.bind_tcs_state = si_bind_tcs_shader; - sctx->b.b.bind_tes_state = si_bind_tes_shader; - sctx->b.b.bind_gs_state = si_bind_gs_shader; - sctx->b.b.bind_fs_state = si_bind_ps_shader; - - sctx->b.b.delete_vs_state = si_delete_shader_selector; - sctx->b.b.delete_tcs_state = si_delete_shader_selector; - sctx->b.b.delete_tes_state = si_delete_shader_selector; - sctx->b.b.delete_gs_state = si_delete_shader_selector; - sctx->b.b.delete_fs_state = si_delete_shader_selector; + sctx->atoms.s.spi_map.emit = si_emit_spi_map; + sctx->atoms.s.scratch_state.emit = si_emit_scratch_state; + + sctx->b.create_vs_state = si_create_shader_selector; + sctx->b.create_tcs_state = si_create_shader_selector; + sctx->b.create_tes_state = si_create_shader_selector; + sctx->b.create_gs_state = si_create_shader_selector; + sctx->b.create_fs_state = si_create_shader_selector; + + sctx->b.bind_vs_state = si_bind_vs_shader; + sctx->b.bind_tcs_state = si_bind_tcs_shader; + sctx->b.bind_tes_state = si_bind_tes_shader; + sctx->b.bind_gs_state = si_bind_gs_shader; + sctx->b.bind_fs_state = si_bind_ps_shader; + + sctx->b.delete_vs_state = si_delete_shader_selector; + sctx->b.delete_tcs_state = si_delete_shader_selector; + sctx->b.delete_tes_state = si_delete_shader_selector; + sctx->b.delete_gs_state = si_delete_shader_selector; + sctx->b.delete_fs_state = si_delete_shader_selector; }