X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fsvga%2Fsvga_state_rss.c;h=b7195d246bc87c0b41b27aeb73b6948f964d69de;hb=f0f04cd12db156ec53b7ea46fae27199af121f90;hp=ff656a7e053f2e575c262c89aaf0f077ba209f16;hpb=45dac0d82a5a69166e86dce77c2550f7512c541e;p=mesa.git diff --git a/src/gallium/drivers/svga/svga_state_rss.c b/src/gallium/drivers/svga/svga_state_rss.c index ff656a7e053..b7195d246bc 100644 --- a/src/gallium/drivers/svga/svga_state_rss.c +++ b/src/gallium/drivers/svga/svga_state_rss.c @@ -100,6 +100,17 @@ static int emit_rss( struct svga_context *svga, } } + if (dirty & SVGA_NEW_BLEND_COLOR) { + uint32 color; + uint32 r = float_to_ubyte(svga->curr.blend_color.color[0]); + uint32 g = float_to_ubyte(svga->curr.blend_color.color[1]); + uint32 b = float_to_ubyte(svga->curr.blend_color.color[2]); + uint32 a = float_to_ubyte(svga->curr.blend_color.color[3]); + + color = (a << 24) | (r << 16) | (g << 8) | b; + + EMIT_RS( svga, color, BLENDCOLOR, fail ); + } if (dirty & (SVGA_NEW_DEPTH_STENCIL | SVGA_NEW_RAST)) { const struct svga_depth_stencil_state *curr = svga->curr.depth; @@ -123,8 +134,7 @@ static int emit_rss( struct svga_context *svga, EMIT_RS( svga, curr->stencil[0].fail, STENCILFAIL, fail ); EMIT_RS( svga, curr->stencil[0].zfail, STENCILZFAIL, fail ); EMIT_RS( svga, curr->stencil[0].pass, STENCILPASS, fail ); - - EMIT_RS( svga, curr->stencil_ref, STENCILREF, fail ); + EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail ); EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail ); } @@ -160,7 +170,6 @@ static int emit_rss( struct svga_context *svga, EMIT_RS( svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL, fail ); EMIT_RS( svga, curr->stencil[ccw].pass, CCWSTENCILPASS, fail ); - EMIT_RS( svga, curr->stencil_ref, STENCILREF, fail ); EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail ); EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail ); } @@ -178,23 +187,36 @@ static int emit_rss( struct svga_context *svga, } } + if (dirty & SVGA_NEW_STENCIL_REF) { + EMIT_RS( svga, svga->curr.stencil_ref.ref_value[0], STENCILREF, fail ); + } - if (dirty & SVGA_NEW_RAST) + if (dirty & (SVGA_NEW_RAST | SVGA_NEW_NEED_PIPELINE)) { const struct svga_rasterizer_state *curr = svga->curr.rast; + unsigned cullmode = curr->cullmode; /* Shademode: still need to rearrange index list to move * flat-shading PV first vertex. */ EMIT_RS( svga, curr->shademode, SHADEMODE, fail ); - EMIT_RS( svga, curr->cullmode, CULLMODE, fail ); + + /* Don't do culling while the software pipeline is active. It + * does it for us, and additionally introduces potentially + * back-facing triangles. + */ + if (svga->state.sw.need_pipeline) + cullmode = SVGA3D_FACE_NONE; + + EMIT_RS( svga, cullmode, CULLMODE, fail ); EMIT_RS( svga, curr->scissortestenable, SCISSORTESTENABLE, fail ); EMIT_RS( svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS, fail ); EMIT_RS( svga, curr->lastpixel, LASTPIXEL, fail ); EMIT_RS( svga, curr->linepattern, LINEPATTERN, fail ); EMIT_RS_FLOAT( svga, curr->pointsize, POINTSIZE, fail ); - EMIT_RS_FLOAT( svga, curr->pointsize_min, POINTSIZEMIN, fail ); - EMIT_RS_FLOAT( svga, curr->pointsize_max, POINTSIZEMAX, fail ); + /* XXX still need to set this? */ + EMIT_RS_FLOAT( svga, 0.0, POINTSIZEMIN, fail ); + EMIT_RS_FLOAT( svga, SVGA_MAX_POINTSIZE, POINTSIZEMAX, fail ); } if (dirty & (SVGA_NEW_RAST | SVGA_NEW_FRAME_BUFFER | SVGA_NEW_NEED_PIPELINE)) @@ -230,13 +252,10 @@ static int emit_rss( struct svga_context *svga, memcpy( rs, queue.rs, queue.rs_count * sizeof queue.rs[0]); - + SVGA_FIFOCommitAll( svga->swc ); } - /* Also blend color: - */ - return 0; fail: @@ -256,7 +275,9 @@ struct svga_tracked_state svga_hw_rss = "hw rss state", (SVGA_NEW_BLEND | + SVGA_NEW_BLEND_COLOR | SVGA_NEW_DEPTH_STENCIL | + SVGA_NEW_STENCIL_REF | SVGA_NEW_RAST | SVGA_NEW_FRAME_BUFFER | SVGA_NEW_NEED_PIPELINE),