X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_context.h;h=c271a957717458333dbb07c3246b9616640960d8;hb=48d743c5019076056739561f979e7101c04acf21;hp=7faf5223630e6becf29d9e908d89535270da8b37;hpb=7124feba1b879deb88dbf2baf600ed42309d9839;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_context.h b/src/gallium/drivers/vc4/vc4_context.h index 7faf5223630..c271a957717 100644 --- a/src/gallium/drivers/vc4/vc4_context.h +++ b/src/gallium/drivers/vc4/vc4_context.h @@ -67,7 +67,9 @@ #define VC4_DIRTY_CLIP (1 << 20) #define VC4_DIRTY_UNCOMPILED_VS (1 << 21) #define VC4_DIRTY_UNCOMPILED_FS (1 << 22) -#define VC4_DIRTY_COMPILED_FS (1 << 24) +#define VC4_DIRTY_COMPILED_CS (1 << 23) +#define VC4_DIRTY_COMPILED_VS (1 << 24) +#define VC4_DIRTY_COMPILED_FS (1 << 25) struct vc4_sampler_view { struct pipe_sampler_view base; @@ -101,7 +103,6 @@ struct vc4_uncompiled_shader { /** How many variants of this program were compiled, for shader-db. */ uint32_t compiled_variant_count; struct pipe_shader_state base; - const struct tgsi_token *twoside_tokens; }; struct vc4_ubo_range { @@ -132,6 +133,12 @@ struct vc4_compiled_shader { struct vc4_ubo_range *ubo_ranges; uint32_t num_ubo_ranges; uint32_t ubo_size; + /** + * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the + * uniforms have to be rewritten (and therefore the shader state + * reemitted). + */ + uint32_t uniform_dirty_bits; /** bitmask of which inputs are color inputs, for flat shade handling. */ uint32_t color_inputs; @@ -150,18 +157,12 @@ struct vc4_compiled_shader { * It doesn't include those that aren't part of the VPM, like * point/line coordinates. */ - struct vc4_varying_semantic *input_semantics; + struct vc4_varying_slot *input_slots; }; struct vc4_program_stateobj { struct vc4_uncompiled_shader *bind_vs, *bind_fs; struct vc4_compiled_shader *cs, *vs, *fs; - uint8_t num_exports; - /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index - * for TGSI_SEMANTIC_GENERIC. Special vs exports (position and point- - * size) are not included in this - */ - uint8_t export_linkage[63]; }; struct vc4_constbuf_stateobj { @@ -200,6 +201,8 @@ struct vc4_context { struct pipe_surface *color_write; struct pipe_surface *zs_read; struct pipe_surface *zs_write; + struct pipe_surface *msaa_color_write; + struct pipe_surface *msaa_zs_write; /** @} */ /** @{ * Bounding box of the scissor across all queued drawing. @@ -218,6 +221,15 @@ struct vc4_context { uint32_t draw_width; uint32_t draw_height; /** @} */ + /** @{ Tile information, depending on MSAA and float color buffer. */ + uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */ + uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */ + + uint32_t tile_width; /** @< Width of a tile. */ + uint32_t tile_height; /** @< Height of a tile. */ + /** Whether the current rendering is in a 4X MSAA tile buffer. */ + bool msaa; + /** @} */ struct util_slab_mempool transfer_pool; struct blitter_context *blitter; @@ -244,10 +256,15 @@ struct vc4_context { bool needs_flush; /** - * Set when needs_flush, and the queued rendering is not just composed - * of full-buffer clears. + * Number of draw calls (not counting full buffer clears) queued in + * the current job. */ - bool draw_call_queued; + uint32_t draw_calls_queued; + + /** Maximum index buffer valid for the current shader_rec. */ + uint32_t max_index; + /** Last index bias baked into the current shader_rec. */ + uint32_t last_index_bias; struct primconvert_context *primconvert; @@ -257,6 +274,8 @@ struct vc4_context { struct ra_regs *regs; unsigned int reg_class_any; + unsigned int reg_class_a_or_b_or_acc; + unsigned int reg_class_r4_or_a; unsigned int reg_class_a; uint8_t prim_mode; @@ -278,7 +297,10 @@ struct vc4_context { struct vc4_vertex_stateobj *vtx; - struct pipe_blend_color blend_color; + struct { + struct pipe_blend_color f; + uint8_t ub[4]; + } blend_color; struct pipe_stencil_ref stencil_ref; unsigned sample_mask; struct pipe_framebuffer_state framebuffer; @@ -350,7 +372,7 @@ vc4_sampler_state(struct pipe_sampler_state *psampler) } struct pipe_context *vc4_context_create(struct pipe_screen *pscreen, - void *priv); + void *priv, unsigned flags); void vc4_draw_init(struct pipe_context *pctx); void vc4_state_init(struct pipe_context *pctx); void vc4_program_init(struct pipe_context *pctx); @@ -360,6 +382,7 @@ void vc4_simulator_init(struct vc4_screen *screen); int vc4_simulator_flush(struct vc4_context *vc4, struct drm_vc4_submit_cl *args); +void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader); void vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader, struct vc4_constbuf_stateobj *cb, @@ -369,7 +392,8 @@ void vc4_flush(struct pipe_context *pctx); void vc4_job_init(struct vc4_context *vc4); void vc4_job_submit(struct vc4_context *vc4); void vc4_job_reset(struct vc4_context *vc4); -bool vc4_cl_references_bo(struct pipe_context *pctx, struct vc4_bo *bo); +bool vc4_cl_references_bo(struct pipe_context *pctx, struct vc4_bo *bo, + bool include_reads); void vc4_emit_state(struct pipe_context *pctx); void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c); struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);