X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_context.h;h=f02992f07ee5c19aa15ec94b64e1cdf870c5656f;hb=1a99fc0fd022018ed056cd42f299d5ad1a02c264;hp=a7c25a8bb0dc97cdec8db0bf4ad7b0964d327e29;hpb=5db82e0c897da46867dec5886bae1607d3124abc;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_context.h b/src/gallium/drivers/vc4/vc4_context.h index a7c25a8bb0d..f02992f07ee 100644 --- a/src/gallium/drivers/vc4/vc4_context.h +++ b/src/gallium/drivers/vc4/vc4_context.h @@ -29,15 +29,23 @@ #include "pipe/p_context.h" #include "pipe/p_state.h" -#include "util/u_slab.h" +#include "util/slab.h" +#include "xf86drm.h" #define __user -#include "vc4_drm.h" +#include "drm-uapi/vc4_drm.h" #include "vc4_bufmgr.h" #include "vc4_resource.h" #include "vc4_cl.h" #include "vc4_qir.h" +#ifndef DRM_VC4_PARAM_SUPPORTS_ETC1 +#define DRM_VC4_PARAM_SUPPORTS_ETC1 4 +#endif +#ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS +#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 +#endif + #ifdef USE_VC4_SIMULATOR #define using_vc4_simulator true #else @@ -49,7 +57,6 @@ #define VC4_DIRTY_ZSA (1 << 2) #define VC4_DIRTY_FRAGTEX (1 << 3) #define VC4_DIRTY_VERTTEX (1 << 4) -#define VC4_DIRTY_TEXSTATE (1 << 5) #define VC4_DIRTY_BLEND_COLOR (1 << 7) #define VC4_DIRTY_STENCIL_REF (1 << 8) @@ -60,7 +67,7 @@ #define VC4_DIRTY_CONSTBUF (1 << 13) #define VC4_DIRTY_VTXSTATE (1 << 14) #define VC4_DIRTY_VTXBUF (1 << 15) -#define VC4_DIRTY_INDEXBUF (1 << 16) + #define VC4_DIRTY_SCISSOR (1 << 17) #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18) #define VC4_DIRTY_PRIM_MODE (1 << 19) @@ -70,11 +77,21 @@ #define VC4_DIRTY_COMPILED_CS (1 << 23) #define VC4_DIRTY_COMPILED_VS (1 << 24) #define VC4_DIRTY_COMPILED_FS (1 << 25) +#define VC4_DIRTY_FS_INPUTS (1 << 26) +#define VC4_DIRTY_UBO_1_SIZE (1 << 27) struct vc4_sampler_view { struct pipe_sampler_view base; uint32_t texture_p0; uint32_t texture_p1; + bool force_first_level; + /** + * Resource containing the actual texture that will be sampled. + * + * We may need to rebase the .base.texture resource to work around the + * lack of GL_TEXTURE_BASE_LEVEL, or to upload the texture as tiled. + */ + struct pipe_resource *texture; }; struct vc4_sampler_state { @@ -104,23 +121,15 @@ struct vc4_uncompiled_shader { struct pipe_shader_state base; }; -struct vc4_ubo_range { +struct vc4_fs_inputs { /** - * offset in bytes from the start of the ubo where this range is - * uploaded. + * Array of the meanings of the VPM inputs this shader needs. * - * Only set once used is set. - */ - uint32_t dst_offset; - - /** - * offset in bytes from the start of the gallium uniforms where the - * data comes from. + * It doesn't include those that aren't part of the VPM, like + * point/line coordinates. */ - uint32_t src_offset; - - /** size in bytes of this ubo range */ - uint32_t size; + struct vc4_varying_slot *input_slots; + uint32_t num_inputs; }; struct vc4_compiled_shader { @@ -129,9 +138,6 @@ struct vc4_compiled_shader { struct vc4_shader_uniform_info uniforms; - struct vc4_ubo_range *ubo_ranges; - uint32_t num_ubo_ranges; - uint32_t ubo_size; /** * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the * uniforms have to be rewritten (and therefore the shader state @@ -142,6 +148,16 @@ struct vc4_compiled_shader { /** bitmask of which inputs are color inputs, for flat shade handling. */ uint32_t color_inputs; + bool disable_early_z; + + /* Set if the compile failed, likely due to register allocation + * failure. In this case, we have no shader to run and should not try + * to do any draws. + */ + bool failed; + + bool fs_threaded; + uint8_t num_inputs; /* Byte offsets for the start of the vertex attributes 0-7, and the @@ -150,13 +166,7 @@ struct vc4_compiled_shader { uint8_t vattr_offsets[9]; uint8_t vattrs_live; - /** - * Array of the meanings of the VPM inputs this shader needs. - * - * It doesn't include those that aren't part of the VPM, like - * point/line coordinates. - */ - struct vc4_varying_slot *input_slots; + const struct vc4_fs_inputs *fs_inputs; }; struct vc4_program_stateobj { @@ -182,18 +192,45 @@ struct vc4_vertex_stateobj { unsigned num_elements; }; -struct vc4_context { - struct pipe_context base; +/* Hash table key for vc4->jobs */ +struct vc4_job_key { + struct pipe_surface *cbuf; + struct pipe_surface *zsbuf; +}; - int fd; - struct vc4_screen *screen; +struct vc4_hwperfmon { + uint32_t id; + uint64_t last_seqno; + uint8_t events[DRM_VC4_MAX_PERF_COUNTERS]; + uint64_t counters[DRM_VC4_MAX_PERF_COUNTERS]; +}; +/** + * A complete bin/render job. + * + * This is all of the state necessary to submit a bin/render to the kernel. + * We want to be able to have multiple in progress at a time, so that we don't + * need to flush an existing CL just to switch to rendering to a new render + * target (which would mean reading back from the old render target when + * starting to render to it again). + */ +struct vc4_job { struct vc4_cl bcl; struct vc4_cl shader_rec; struct vc4_cl uniforms; struct vc4_cl bo_handles; struct vc4_cl bo_pointers; uint32_t shader_rec_count; + /** + * Amount of memory used by the BOs in bo_pointers. + * + * Used for checking when we should flush the job early so we don't + * OOM. + */ + uint32_t bo_space; + + /* Last BO hindex referenced from VC4_PACKET_GEM_HANDLES. */ + uint32_t last_gem_handle_hindex; /** @{ Surfaces to submit rendering for. */ struct pipe_surface *color_read; @@ -230,11 +267,6 @@ struct vc4_context { bool msaa; /** @} */ - struct util_slab_mempool transfer_pool; - struct blitter_context *blitter; - - /** bitfield of VC4_DIRTY_* */ - uint32_t dirty; /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the * first rendering. */ @@ -260,30 +292,73 @@ struct vc4_context { */ uint32_t draw_calls_queued; - /** Maximum index buffer valid for the current shader_rec. */ - uint32_t max_index; - /** Last index bias baked into the current shader_rec. */ - uint32_t last_index_bias; + /** Any flags to be passed in drm_vc4_submit_cl.flags. */ + uint32_t flags; + + /* Performance monitor attached to this job. */ + struct vc4_hwperfmon *perfmon; + + struct vc4_job_key key; +}; + +struct vc4_context { + struct pipe_context base; + + int fd; + struct vc4_screen *screen; + + /** The 3D rendering job for the currently bound FBO. */ + struct vc4_job *job; + + /* Map from struct vc4_job_key to the job for that FBO. + */ + struct hash_table *jobs; + + /** + * Map from vc4_resource to a job writing to that resource. + * + * Primarily for flushing jobs rendering to textures that are now + * being read from. + */ + struct hash_table *write_jobs; + + struct slab_child_pool transfer_pool; + struct blitter_context *blitter; + + /** bitfield of VC4_DIRTY_* */ + uint32_t dirty; struct primconvert_context *primconvert; struct hash_table *fs_cache, *vs_cache; + struct set *fs_inputs_set; uint32_t next_uncompiled_program_id; uint64_t next_compiled_program_id; struct ra_regs *regs; - unsigned int reg_class_any; - unsigned int reg_class_a_or_b_or_acc; - unsigned int reg_class_r4_or_a; - unsigned int reg_class_a; + unsigned int reg_class_any[2]; + unsigned int reg_class_a_or_b[2]; + unsigned int reg_class_a_or_b_or_acc[2]; + unsigned int reg_class_r0_r3; + unsigned int reg_class_r4_or_a[2]; + unsigned int reg_class_a[2]; uint8_t prim_mode; + /** Maximum index buffer valid for the current shader_rec. */ + uint32_t max_index; + /** Last index bias baked into the current shader_rec. */ + uint32_t last_index_bias; + /** Seqno of the last CL flush's job. */ uint64_t last_emit_seqno; struct u_upload_mgr *uploader; + struct pipe_shader_state *yuv_linear_blit_vs; + struct pipe_shader_state *yuv_linear_blit_fs_8bit; + struct pipe_shader_state *yuv_linear_blit_fs_16bit; + /** @{ Current pipeline state objects */ struct pipe_scissor_state scissor; struct pipe_blend_state *blend; @@ -308,35 +383,40 @@ struct vc4_context { struct pipe_viewport_state viewport; struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES]; struct vc4_vertexbuf_stateobj vertexbuf; - struct pipe_index_buffer indexbuf; + struct pipe_debug_callback debug; + + struct vc4_hwperfmon *perfmon; /** @} */ + + /** Handle of syncobj containing the last submitted job fence. */ + uint32_t job_syncobj; + + int in_fence_fd; + /** Handle of the syncobj that holds in_fence_fd for submission. */ + uint32_t in_syncobj; }; struct vc4_rasterizer_state { struct pipe_rasterizer_state base; /* VC4_CONFIGURATION_BITS */ - uint8_t config_bits[3]; + uint8_t config_bits[V3D21_CONFIGURATION_BITS_length]; - float point_size; + struct PACKED { + uint8_t depth_offset[V3D21_DEPTH_OFFSET_length]; + uint8_t point_size[V3D21_POINT_SIZE_length]; + uint8_t line_width[V3D21_LINE_WIDTH_length]; + } packed; - /** - * Half-float (1/8/7 bits) value of polygon offset units for - * VC4_PACKET_DEPTH_OFFSET - */ - uint16_t offset_units; - /** - * Half-float (1/8/7 bits) value of polygon offset scale for - * VC4_PACKET_DEPTH_OFFSET - */ - uint16_t offset_factor; + /** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */ + uint32_t tile_raster_order_flags; }; struct vc4_depth_stencil_alpha_state { struct pipe_depth_stencil_alpha_state base; /* VC4_CONFIGURATION_BITS */ - uint8_t config_bits[3]; + uint8_t config_bits[V3D21_CONFIGURATION_BITS_length]; /** Uniforms for stencil state. * @@ -350,6 +430,8 @@ struct vc4_depth_stencil_alpha_state { #define perf_debug(...) do { \ if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \ fprintf(stderr, __VA_ARGS__); \ + if (unlikely(vc4->debug.debug_message)) \ + pipe_debug_message(&vc4->debug, PERF_INFO, __VA_ARGS__); \ } while (0) static inline struct vc4_context * @@ -370,6 +452,12 @@ vc4_sampler_state(struct pipe_sampler_state *psampler) return (struct vc4_sampler_state *)psampler; } +int vc4_get_driver_query_group_info(struct pipe_screen *pscreen, + unsigned index, + struct pipe_driver_query_group_info *info); +int vc4_get_driver_query_info(struct pipe_screen *pscreen, unsigned index, + struct pipe_driver_query_info *info); + struct pipe_context *vc4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags); void vc4_draw_init(struct pipe_context *pctx); @@ -378,8 +466,18 @@ void vc4_program_init(struct pipe_context *pctx); void vc4_program_fini(struct pipe_context *pctx); void vc4_query_init(struct pipe_context *pctx); void vc4_simulator_init(struct vc4_screen *screen); -int vc4_simulator_flush(struct vc4_context *vc4, - struct drm_vc4_submit_cl *args); +void vc4_simulator_destroy(struct vc4_screen *screen); +int vc4_simulator_ioctl(int fd, unsigned long request, void *arg); +void vc4_simulator_open_from_handle(int fd, int handle, uint32_t size); + +static inline int +vc4_ioctl(int fd, unsigned long request, void *arg) +{ + if (using_vc4_simulator) + return vc4_simulator_ioctl(fd, request, arg); + else + return drmIoctl(fd, request, arg); +} void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader); void vc4_write_uniforms(struct vc4_context *vc4, @@ -388,15 +486,22 @@ void vc4_write_uniforms(struct vc4_context *vc4, struct vc4_texture_stateobj *texstate); void vc4_flush(struct pipe_context *pctx); -void vc4_job_init(struct vc4_context *vc4); -void vc4_job_submit(struct vc4_context *vc4); -void vc4_job_reset(struct vc4_context *vc4); -bool vc4_cl_references_bo(struct pipe_context *pctx, struct vc4_bo *bo, - bool include_reads); +int vc4_job_init(struct vc4_context *vc4); +int vc4_fence_context_init(struct vc4_context *vc4); +struct vc4_job *vc4_get_job(struct vc4_context *vc4, + struct pipe_surface *cbuf, + struct pipe_surface *zsbuf); +struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4); + +void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job); +void vc4_flush_jobs_writing_resource(struct vc4_context *vc4, + struct pipe_resource *prsc); +void vc4_flush_jobs_reading_resource(struct vc4_context *vc4, + struct pipe_resource *prsc); void vc4_emit_state(struct pipe_context *pctx); void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c); struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c); -void vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode); +bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode); bool vc4_rt_format_supported(enum pipe_format f); bool vc4_rt_format_is_565(enum pipe_format f); @@ -405,4 +510,5 @@ uint8_t vc4_get_tex_format(enum pipe_format f); const uint8_t *vc4_get_format_swizzle(enum pipe_format f); void vc4_init_query_functions(struct vc4_context *vc4); void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info); +void vc4_blitter_save(struct vc4_context *vc4); #endif /* VC4_CONTEXT_H */