X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_emit.c;h=5d6479777551fc5b8c97e63cd2e3b53806379ad0;hb=1ffe77e7bb2486ea74cda077ed2a9622b758395c;hp=ba064ff889bdb5785570765fd5a014a1e989bd9b;hpb=6a7ca4ef2cd3f39d3b5e77051cb3f3175e9e60df;p=mesa.git

diff --git a/src/gallium/drivers/vc4/vc4_emit.c b/src/gallium/drivers/vc4/vc4_emit.c
index ba064ff889b..5d647977755 100644
--- a/src/gallium/drivers/vc4/vc4_emit.c
+++ b/src/gallium/drivers/vc4/vc4_emit.c
@@ -29,17 +29,35 @@ vc4_emit_state(struct pipe_context *pctx)
         struct vc4_context *vc4 = vc4_context(pctx);
 
         struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
-        if (vc4->dirty & (VC4_DIRTY_SCISSOR | VC4_DIRTY_VIEWPORT)) {
+        if (vc4->dirty & (VC4_DIRTY_SCISSOR | VC4_DIRTY_VIEWPORT |
+                          VC4_DIRTY_RASTERIZER)) {
                 float *vpscale = vc4->viewport.scale;
                 float *vptranslate = vc4->viewport.translate;
                 float vp_minx = -fabsf(vpscale[0]) + vptranslate[0];
                 float vp_maxx = fabsf(vpscale[0]) + vptranslate[0];
                 float vp_miny = -fabsf(vpscale[1]) + vptranslate[1];
                 float vp_maxy = fabsf(vpscale[1]) + vptranslate[1];
-                uint32_t minx = MAX2(vc4->scissor.minx, vp_minx);
-                uint32_t miny = MAX2(vc4->scissor.miny, vp_miny);
-                uint32_t maxx = MIN2(vc4->scissor.maxx, vp_maxx);
-                uint32_t maxy = MIN2(vc4->scissor.maxy, vp_maxy);
+
+                /* Clip to the scissor if it's enabled, but still clip to the
+                 * drawable regardless since that controls where the binner
+                 * tries to put things.
+                 *
+                 * Additionally, always clip the rendering to the viewport,
+                 * since the hardware does guardband clipping, meaning
+                 * primitives would rasterize outside of the view volume.
+                 */
+                uint32_t minx, miny, maxx, maxy;
+                if (!vc4->rasterizer->base.scissor) {
+                        minx = MAX2(vp_minx, 0);
+                        miny = MAX2(vp_miny, 0);
+                        maxx = MIN2(vp_maxx, vc4->draw_width);
+                        maxy = MIN2(vp_maxy, vc4->draw_height);
+                } else {
+                        minx = MAX2(vp_minx, vc4->scissor.minx);
+                        miny = MAX2(vp_miny, vc4->scissor.miny);
+                        maxx = MIN2(vp_maxx, vc4->scissor.maxx);
+                        maxy = MIN2(vp_maxy, vc4->scissor.maxy);
+                }
 
                 cl_u8(&bcl, VC4_PACKET_CLIP_WINDOW);
                 cl_u16(&bcl, minx);
@@ -54,6 +72,20 @@ vc4_emit_state(struct pipe_context *pctx)
         }
 
         if (vc4->dirty & (VC4_DIRTY_RASTERIZER | VC4_DIRTY_ZSA)) {
+                uint8_t ez_enable_mask_out = ~0;
+
+                /* HW-2905: If the RCL ends up doing a full-res load when
+                 * multisampling, then early Z tracking may end up with values
+                 * from the previous tile due to a HW bug.  Disable it to
+                 * avoid that.
+                 *
+                 * We should be able to skip this when the Z is cleared, but I
+                 * was seeing bad rendering on glxgears -samples 4 even in
+                 * that case.
+                 */
+                if (vc4->msaa)
+                        ez_enable_mask_out &= ~VC4_CONFIG_BITS_EARLY_Z;
+
                 cl_u8(&bcl, VC4_PACKET_CONFIGURATION_BITS);
                 cl_u8(&bcl,
                       vc4->rasterizer->config_bits[0] |
@@ -62,8 +94,8 @@ vc4_emit_state(struct pipe_context *pctx)
                       vc4->rasterizer->config_bits[1] |
                       vc4->zsa->config_bits[1]);
                 cl_u8(&bcl,
-                      vc4->rasterizer->config_bits[2] |
-                      vc4->zsa->config_bits[2]);
+                      (vc4->rasterizer->config_bits[2] |
+                       vc4->zsa->config_bits[2]) & ez_enable_mask_out);
         }
 
         if (vc4->dirty & VC4_DIRTY_RASTERIZER) {