X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_qpu_defines.h;h=e6ca345c3b2286ffd229e88d48c66ae0a698adbc;hb=09c1c13c4442148e45a4aeac3425382bbe90e8cd;hp=b2f028f01945ab0868291b5af59ae8248bd2c678;hpb=9ca32d6c19489653222ff1084856fa5584932b66;p=mesa.git

diff --git a/src/gallium/drivers/vc4/vc4_qpu_defines.h b/src/gallium/drivers/vc4/vc4_qpu_defines.h
index b2f028f0194..e6ca345c3b2 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_defines.h
+++ b/src/gallium/drivers/vc4/vc4_qpu_defines.h
@@ -147,8 +147,11 @@ enum qpu_mux {
         QPU_MUX_A,
         QPU_MUX_B,
 
-        /* non-hardware mux values */
-        QPU_MUX_IMM,
+        /**
+         * Non-hardware mux value, stores a small immediate field to be
+         * programmed into raddr_b in the qpu_reg.index.
+         */
+        QPU_MUX_SMALL_IMM,
 };
 
 enum qpu_cond {
@@ -162,6 +165,23 @@ enum qpu_cond {
         QPU_COND_CC,
 };
 
+enum qpu_branch_cond {
+        QPU_COND_BRANCH_ALL_ZS,
+        QPU_COND_BRANCH_ALL_ZC,
+        QPU_COND_BRANCH_ANY_ZS,
+        QPU_COND_BRANCH_ANY_ZC,
+        QPU_COND_BRANCH_ALL_NS,
+        QPU_COND_BRANCH_ALL_NC,
+        QPU_COND_BRANCH_ANY_NS,
+        QPU_COND_BRANCH_ANY_NC,
+        QPU_COND_BRANCH_ALL_CS,
+        QPU_COND_BRANCH_ALL_CC,
+        QPU_COND_BRANCH_ANY_CS,
+        QPU_COND_BRANCH_ANY_CC,
+
+        QPU_COND_BRANCH_ALWAYS = 15
+};
+
 enum qpu_pack_mul {
         QPU_PACK_MUL_NOP,
         QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */
@@ -197,8 +217,8 @@ enum qpu_pack_a {
 
 enum qpu_unpack {
         QPU_UNPACK_NOP,
-        QPU_UNPACK_16A_TO_F32,
-        QPU_UNPACK_16B_TO_F32,
+        QPU_UNPACK_16A,
+        QPU_UNPACK_16B,
         QPU_UNPACK_8D_REP,
         QPU_UNPACK_8A,
         QPU_UNPACK_8B,
@@ -217,12 +237,21 @@ enum qpu_unpack {
 
 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word)  & field ## _MASK) >> field ## _SHIFT))
 
+#define QPU_UPDATE_FIELD(inst, value, field)                              \
+        (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
+
 #define QPU_SIG_SHIFT                   60
 #define QPU_SIG_MASK                    QPU_MASK(63, 60)
 
 #define QPU_UNPACK_SHIFT                57
 #define QPU_UNPACK_MASK                 QPU_MASK(59, 57)
 
+#define QPU_LOAD_IMM_MODE_SHIFT         57
+#define QPU_LOAD_IMM_MODE_MASK          QPU_MASK(59, 57)
+# define QPU_LOAD_IMM_MODE_U32          0
+# define QPU_LOAD_IMM_MODE_I2           1
+# define QPU_LOAD_IMM_MODE_U2           3
+
 /**
  * If set, the pack field means PACK_MUL or R4 packing, instead of normal
  * regfile a packing.
@@ -237,6 +266,16 @@ enum qpu_unpack {
 #define QPU_COND_MUL_SHIFT              46
 #define QPU_COND_MUL_MASK               QPU_MASK(48, 46)
 
+
+#define QPU_BRANCH_COND_SHIFT           52
+#define QPU_BRANCH_COND_MASK            QPU_MASK(55, 52)
+
+#define QPU_BRANCH_REL                  ((uint64_t)1 << 51)
+#define QPU_BRANCH_REG                  ((uint64_t)1 << 50)
+
+#define QPU_BRANCH_RADDR_A_SHIFT        45
+#define QPU_BRANCH_RADDR_A_MASK         QPU_MASK(49, 45)
+
 #define QPU_SF                          ((uint64_t)1 << 45)
 
 #define QPU_WADDR_ADD_SHIFT             38
@@ -253,6 +292,10 @@ enum qpu_unpack {
 #define QPU_RADDR_B_MASK                QPU_MASK(17, 12)
 #define QPU_SMALL_IMM_SHIFT             12
 #define QPU_SMALL_IMM_MASK              QPU_MASK(17, 12)
+/* Small immediate value for rotate-by-r5, and 49-63 are "rotate by n
+ * channels"
+ */
+#define QPU_SMALL_IMM_MUL_ROT		48
 
 #define QPU_ADD_A_SHIFT                 9
 #define QPU_ADD_A_MASK                  QPU_MASK(11, 9)
@@ -268,4 +311,10 @@ enum qpu_unpack {
 #define QPU_OP_ADD_SHIFT                24
 #define QPU_OP_ADD_MASK                 QPU_MASK(28, 24)
 
+#define QPU_LOAD_IMM_SHIFT              0
+#define QPU_LOAD_IMM_MASK               QPU_MASK(31, 0)
+
+#define QPU_BRANCH_TARGET_SHIFT         0
+#define QPU_BRANCH_TARGET_MASK          QPU_MASK(31, 0)
+
 #endif /* VC4_QPU_DEFINES_H */