X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_qpu_emit.c;h=2257dcce83be3f70c180c612abbe815d75f6fb2f;hb=ee69cfd11d34e6570c579c42f9cd8b5c8ea36bcf;hp=c4359e718f5e4e44c4f40154c5f702a064831da9;hpb=87db578268012ffc7ca09b737441490144340c6e;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c b/src/gallium/drivers/vc4/vc4_qpu_emit.c index c4359e718f5..2257dcce83b 100644 --- a/src/gallium/drivers/vc4/vc4_qpu_emit.c +++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c @@ -40,6 +40,7 @@ vc4_dump_program(struct vc4_compile *c) vc4_qpu_disasm(&c->qpu_insts[i], 1); fprintf(stderr, "\n"); } + fprintf(stderr, "\n"); } static void @@ -47,14 +48,14 @@ queue(struct vc4_compile *c, uint64_t inst) { struct queued_qpu_inst *q = rzalloc(c, struct queued_qpu_inst); q->inst = inst; - insert_at_tail(&c->qpu_inst_list, &q->link); + list_addtail(&q->link, &c->qpu_inst_list); } static uint64_t * last_inst(struct vc4_compile *c) { struct queued_qpu_inst *q = - (struct queued_qpu_inst *)last_elem(&c->qpu_inst_list); + (struct queued_qpu_inst *)c->qpu_inst_list.prev; return &q->inst; } @@ -64,6 +65,12 @@ set_last_cond_add(struct vc4_compile *c, uint32_t cond) *last_inst(c) = qpu_set_cond_add(*last_inst(c), cond); } +static void +set_last_cond_mul(struct vc4_compile *c, uint32_t cond) +{ + *last_inst(c) = qpu_set_cond_mul(*last_inst(c), cond); +} + /** * Some special registers can be read from either file, which lets us resolve * raddr conflicts without extra MOVs. @@ -74,11 +81,15 @@ swap_file(struct qpu_reg *src) switch (src->addr) { case QPU_R_UNIF: case QPU_R_VARY: - if (src->mux == QPU_MUX_A) - src->mux = QPU_MUX_B; - else - src->mux = QPU_MUX_A; - return true; + if (src->mux == QPU_MUX_SMALL_IMM) { + return false; + } else { + if (src->mux == QPU_MUX_A) + src->mux = QPU_MUX_B; + else + src->mux = QPU_MUX_A; + return true; + } default: return false; @@ -92,57 +103,91 @@ swap_file(struct qpu_reg *src) * address. * * In that case, we need to move one to a temporary that can be used in the - * instruction, instead. + * instruction, instead. We reserve ra31/rb31 for this purpose. */ -static bool +static void fixup_raddr_conflict(struct vc4_compile *c, struct qpu_reg dst, struct qpu_reg *src0, struct qpu_reg *src1, - bool r3_live) + struct qinst *inst, uint64_t *unpack) { - if ((src0->mux != QPU_MUX_A && src0->mux != QPU_MUX_B) || - src0->mux != src1->mux || - src0->addr == src1->addr) { - return false; + uint32_t mux0 = src0->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src0->mux; + uint32_t mux1 = src1->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src1->mux; + + if (mux0 <= QPU_MUX_R5 || + mux0 != mux1 || + (src0->addr == src1->addr && + src0->mux == src1->mux)) { + return; } if (swap_file(src0) || swap_file(src1)) - return false; + return; - if (src0->mux == QPU_MUX_A) { - /* If we're conflicting over the A regfile, then we can just - * use the reserved rb31. + if (mux0 == QPU_MUX_A) { + /* Make sure we use the same type of MOV as the instruction, + * in case of unpacks. */ - queue(c, qpu_a_MOV(qpu_rb(31), *src1)); - *src1 = qpu_rb(31); - return false; - } else { - /* Otherwise, we need a non-B regfile. So, we spill r3 out to - * rb31, then store our desired value in r3, and tell the - * caller to put rb31 back into r3 when we're done. + if (qir_is_float_input(inst)) + queue(c, qpu_a_FMAX(qpu_rb(31), *src0, *src0)); + else + queue(c, qpu_a_MOV(qpu_rb(31), *src0)); + + /* If we had an unpack on this A-file source, we need to put + * it into this MOV, not into the later move from regfile B. */ - if (r3_live) - queue(c, qpu_a_MOV(qpu_rb(31), qpu_r3())); - queue(c, qpu_a_MOV(qpu_r3(), *src1)); + if (inst->src[0].pack) { + *last_inst(c) |= *unpack; + *unpack = 0; + } + *src0 = qpu_rb(31); + } else { + queue(c, qpu_a_MOV(qpu_ra(31), *src0)); + *src0 = qpu_ra(31); + } +} - *src1 = qpu_r3(); +static void +set_last_dst_pack(struct vc4_compile *c, struct qinst *inst) +{ + bool had_pm = *last_inst(c) & QPU_PM; + bool had_ws = *last_inst(c) & QPU_WS; + uint32_t unpack = QPU_GET_FIELD(*last_inst(c), QPU_UNPACK); - return r3_live && dst.mux != QPU_MUX_R3; + if (!inst->dst.pack) + return; + + *last_inst(c) |= QPU_SET_FIELD(inst->dst.pack, QPU_PACK); + + if (qir_is_mul(inst)) { + assert(!unpack || had_pm); + *last_inst(c) |= QPU_PM; + } else { + assert(!unpack || !had_pm); + assert(!had_ws); /* dst must be a-file to pack. */ } } +static void +handle_r4_qpu_write(struct vc4_compile *c, struct qinst *qinst, + struct qpu_reg dst) +{ + if (dst.mux != QPU_MUX_R4) + queue(c, qpu_a_MOV(dst, qpu_r4())); + else if (qinst->sf) + queue(c, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4())); +} + void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) { struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c); - bool discard = false; uint32_t inputs_remaining = c->num_inputs; uint32_t vpm_read_fifo_count = 0; uint32_t vpm_read_offset = 0; - bool written_r3 = false; - bool needs_restore; + int last_vpm_read_index = -1; - make_empty_list(&c->qpu_inst_list); + list_inithead(&c->qpu_inst_list); switch (c->stage) { case QSTAGE_VERT: @@ -168,10 +213,7 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) break; } - struct simple_node *node; - foreach(node, &c->instructions) { - struct qinst *qinst = (struct qinst *)node; - + qir_for_each_inst_inorder(qinst, c) { #if 0 fprintf(stderr, "translating qinst to qpu: "); qir_dump_inst(qinst); @@ -180,10 +222,9 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) static const struct { uint32_t op; - bool is_mul; } translate[] = { -#define A(name) [QOP_##name] = {QPU_A_##name, false} -#define M(name) [QOP_##name] = {QPU_M_##name, true} +#define A(name) [QOP_##name] = {QPU_A_##name} +#define M(name) [QOP_##name] = {QPU_M_##name} A(FADD), A(FSUB), A(FMIN), @@ -205,18 +246,40 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) A(NOT), M(FMUL), + M(V8MULD), + M(V8MIN), + M(V8MAX), + M(V8ADDS), + M(V8SUBS), M(MUL24), + + /* If we replicate src[0] out to src[1], this works + * out the same as a MOV. + */ + [QOP_MOV] = { QPU_A_OR }, + [QOP_FMOV] = { QPU_A_FMAX }, + [QOP_MMOV] = { QPU_M_V8MIN }, }; + uint64_t unpack = 0; struct qpu_reg src[4]; for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) { int index = qinst->src[i].index; switch (qinst->src[i].file) { case QFILE_NULL: + case QFILE_LOAD_IMM: src[i] = qpu_rn(0); break; case QFILE_TEMP: src[i] = temp_registers[index]; + if (qinst->src[i].pack) { + assert(!unpack || + unpack == qinst->src[i].pack); + unpack = QPU_SET_FIELD(qinst->src[i].pack, + QPU_UNPACK); + if (src[i].mux == QPU_MUX_R4) + unpack |= QPU_PM; + } break; case QFILE_UNIF: src[i] = qpu_unif(); @@ -224,6 +287,37 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) case QFILE_VARY: src[i] = qpu_vary(); break; + case QFILE_SMALL_IMM: + src[i].mux = QPU_MUX_SMALL_IMM; + src[i].addr = qpu_encode_small_immediate(qinst->src[i].index); + /* This should only have returned a valid + * small immediate field, not ~0 for failure. + */ + assert(src[i].addr <= 47); + break; + case QFILE_VPM: + assert((int)qinst->src[i].index >= + last_vpm_read_index); + (void)last_vpm_read_index; + last_vpm_read_index = qinst->src[i].index; + src[i] = qpu_ra(QPU_R_VPM); + break; + + case QFILE_FRAG_X: + src[i] = qpu_ra(QPU_R_XY_PIXEL_COORD); + break; + case QFILE_FRAG_Y: + src[i] = qpu_rb(QPU_R_XY_PIXEL_COORD); + break; + case QFILE_FRAG_REV_FLAG: + src[i] = qpu_rb(QPU_R_MS_REV_FLAGS); + break; + + case QFILE_TLB_COLOR_WRITE: + case QFILE_TLB_COLOR_WRITE_MS: + case QFILE_TLB_Z_WRITE: + case QFILE_TLB_STENCIL_SETUP: + unreachable("bad qir src file"); } } @@ -235,61 +329,40 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) case QFILE_TEMP: dst = temp_registers[qinst->dst.index]; break; - case QFILE_VARY: - case QFILE_UNIF: - assert(!"not reached"); + case QFILE_VPM: + dst = qpu_ra(QPU_W_VPM); break; - } - switch (qinst->op) { - case QOP_MOV: - /* Skip emitting the MOV if it's a no-op. */ - if (dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B || - dst.mux != src[0].mux || dst.addr != src[0].addr) { - queue(c, qpu_a_MOV(dst, src[0])); - } + case QFILE_TLB_COLOR_WRITE: + dst = qpu_tlbc(); break; - case QOP_SF: - queue(c, qpu_a_MOV(qpu_ra(QPU_W_NOP), src[0])); - *last_inst(c) |= QPU_SF; + case QFILE_TLB_COLOR_WRITE_MS: + dst = qpu_tlbc_ms(); break; - case QOP_SEL_X_0_ZS: - case QOP_SEL_X_0_ZC: - case QOP_SEL_X_0_NS: - case QOP_SEL_X_0_NC: - queue(c, qpu_a_MOV(dst, src[0])); - set_last_cond_add(c, qinst->op - QOP_SEL_X_0_ZS + - QPU_COND_ZS); - - queue(c, qpu_a_XOR(dst, qpu_r0(), qpu_r0())); - set_last_cond_add(c, ((qinst->op - QOP_SEL_X_0_ZS) ^ - 1) + QPU_COND_ZS); + case QFILE_TLB_Z_WRITE: + dst = qpu_ra(QPU_W_TLB_Z); break; - case QOP_SEL_X_Y_ZS: - case QOP_SEL_X_Y_ZC: - case QOP_SEL_X_Y_NS: - case QOP_SEL_X_Y_NC: - queue(c, qpu_a_MOV(dst, src[0])); - set_last_cond_add(c, qinst->op - QOP_SEL_X_Y_ZS + - QPU_COND_ZS); - - queue(c, qpu_a_MOV(dst, src[1])); - set_last_cond_add(c, ((qinst->op - QOP_SEL_X_Y_ZS) ^ - 1) + QPU_COND_ZS); - + case QFILE_TLB_STENCIL_SETUP: + dst = qpu_ra(QPU_W_TLB_STENCIL_SETUP); break; - case QOP_VPM_WRITE: - queue(c, qpu_a_MOV(qpu_ra(QPU_W_VPM), src[0])); + case QFILE_VARY: + case QFILE_UNIF: + case QFILE_SMALL_IMM: + case QFILE_LOAD_IMM: + case QFILE_FRAG_X: + case QFILE_FRAG_Y: + case QFILE_FRAG_REV_FLAG: + assert(!"not reached"); break; + } - case QOP_VPM_READ: - queue(c, qpu_a_MOV(dst, qpu_ra(QPU_R_VPM))); - break; + bool handled_qinst_cond = false; + switch (qinst->op) { case QOP_RCP: case QOP_RSQ: case QOP_EXP2: @@ -297,76 +370,39 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) switch (qinst->op) { case QOP_RCP: queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP), - src[0])); + src[0]) | unpack); break; case QOP_RSQ: queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT), - src[0])); + src[0]) | unpack); break; case QOP_EXP2: queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP), - src[0])); + src[0]) | unpack); break; case QOP_LOG2: queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG), - src[0])); + src[0]) | unpack); break; default: abort(); } - queue(c, qpu_a_MOV(dst, qpu_r4())); - - break; - - case QOP_PACK_COLORS: { - /* We have to be careful not to start writing over one - * of our source values when incrementally writing the - * destination. So, if the dst is one of the srcs, we - * pack that one first (and we pack 4 channels at once - * for the first pack). - */ - struct qpu_reg first_pack = src[0]; - for (int i = 0; i < 4; i++) { - if (src[i].mux == dst.mux && - src[i].addr == dst.addr) { - first_pack = dst; - break; - } - } - queue(c, qpu_m_MOV(dst, first_pack)); - *last_inst(c) |= QPU_PM; - *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8888, - QPU_PACK); - - for (int i = 0; i < 4; i++) { - if (src[i].mux == first_pack.mux && - src[i].addr == first_pack.addr) { - continue; - } - - queue(c, qpu_m_MOV(dst, src[i])); - *last_inst(c) |= QPU_PM; - *last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i, - QPU_PACK); - } - - break; - } + handle_r4_qpu_write(c, qinst, dst); - case QOP_FRAG_X: - queue(c, qpu_a_ITOF(dst, - qpu_ra(QPU_R_XY_PIXEL_COORD))); break; - case QOP_FRAG_Y: - queue(c, qpu_a_ITOF(dst, - qpu_rb(QPU_R_XY_PIXEL_COORD))); + case QOP_LOAD_IMM: + assert(qinst->src[0].file == QFILE_LOAD_IMM); + queue(c, qpu_load_imm_ui(dst, qinst->src[0].index)); break; - case QOP_FRAG_REV_FLAG: - queue(c, qpu_a_ITOF(dst, - qpu_rb(QPU_R_MS_REV_FLAGS))); + case QOP_MS_MASK: + src[1] = qpu_ra(QPU_R_MS_REV_FLAGS); + fixup_raddr_conflict(c, dst, &src[0], &src[1], + qinst, &unpack); + queue(c, qpu_a_AND(qpu_ra(QPU_W_MS_FLAGS), + src[0], src[1]) | unpack); break; case QOP_FRAG_Z: @@ -376,127 +412,59 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) */ break; - case QOP_TLB_DISCARD_SETUP: - discard = true; - queue(c, qpu_a_MOV(src[0], src[0])); - *last_inst(c) |= QPU_SF; - break; - - case QOP_TLB_STENCIL_SETUP: - queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_STENCIL_SETUP), src[0])); - break; - - case QOP_TLB_Z_WRITE: - queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z), src[0])); - if (discard) { - set_last_cond_add(c, QPU_COND_ZS); - } - break; - case QOP_TLB_COLOR_READ: queue(c, qpu_NOP()); *last_inst(c) = qpu_set_sig(*last_inst(c), QPU_SIG_COLOR_LOAD); - - break; - - case QOP_TLB_COLOR_WRITE: - queue(c, qpu_a_MOV(qpu_tlbc(), src[0])); - if (discard) { - set_last_cond_add(c, QPU_COND_ZS); - } + handle_r4_qpu_write(c, qinst, dst); break; case QOP_VARY_ADD_C: - queue(c, qpu_a_FADD(dst, src[0], qpu_r5())); + queue(c, qpu_a_FADD(dst, src[0], qpu_r5()) | unpack); break; - case QOP_PACK_SCALED: { - uint64_t a = (qpu_a_MOV(dst, src[0]) | - QPU_SET_FIELD(QPU_PACK_A_16A, - QPU_PACK)); - uint64_t b = (qpu_a_MOV(dst, src[1]) | - QPU_SET_FIELD(QPU_PACK_A_16B, - QPU_PACK)); - - if (dst.mux == src[1].mux && dst.addr == src[1].addr) { - queue(c, b); - queue(c, a); - } else { - queue(c, a); - queue(c, b); - } - break; - } - case QOP_TEX_S: case QOP_TEX_T: case QOP_TEX_R: case QOP_TEX_B: queue(c, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S + (qinst->op - QOP_TEX_S)), - src[0])); + src[0]) | unpack); break; case QOP_TEX_DIRECT: - needs_restore = fixup_raddr_conflict(c, dst, - &src[0], &src[1], - written_r3); - queue(c, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S), src[0], src[1])); - if (needs_restore) - queue(c, qpu_a_MOV(qpu_r3(), qpu_rb(31))); + fixup_raddr_conflict(c, dst, &src[0], &src[1], + qinst, &unpack); + queue(c, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S), + src[0], src[1]) | unpack); break; case QOP_TEX_RESULT: queue(c, qpu_NOP()); *last_inst(c) = qpu_set_sig(*last_inst(c), QPU_SIG_LOAD_TMU0); - + handle_r4_qpu_write(c, qinst, dst); break; - case QOP_R4_UNPACK_A: - case QOP_R4_UNPACK_B: - case QOP_R4_UNPACK_C: - case QOP_R4_UNPACK_D: - assert(src[0].mux == QPU_MUX_R4); - queue(c, qpu_a_MOV(dst, src[0])); - *last_inst(c) |= QPU_PM; - *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A + - (qinst->op - - QOP_R4_UNPACK_A), - QPU_UNPACK); - - break; - - case QOP_UNPACK_8A: - case QOP_UNPACK_8B: - case QOP_UNPACK_8C: - case QOP_UNPACK_8D: { - assert(src[0].mux == QPU_MUX_A); - - /* And, since we're setting the pack bits, if the - * destination is in A it would get re-packed. + case QOP_BRANCH: + /* The branch target will be updated at QPU scheduling + * time. */ - struct qpu_reg orig_dst = dst; - if (orig_dst.mux == QPU_MUX_A) - dst = qpu_rn(3); - - queue(c, qpu_a_FMAX(dst, src[0], src[0])); - *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A + - (qinst->op - - QOP_UNPACK_8A), - QPU_UNPACK); - - if (orig_dst.mux == QPU_MUX_A) { - queue(c, qpu_a_MOV(orig_dst, dst)); - } - } + queue(c, (qpu_branch(qinst->cond, 0) | + QPU_BRANCH_REL)); + handled_qinst_cond = true; break; default: assert(qinst->op < ARRAY_SIZE(translate)); assert(translate[qinst->op].op != 0); /* NOPs */ + /* Skip emitting the MOV if it's a no-op. */ + if (qir_is_raw_mov(qinst) && + dst.mux == src[0].mux && dst.addr == src[0].addr) { + break; + } + /* If we have only one source, put it in the second * argument slot as well so that we don't take up * another raddr just to get unused data. @@ -504,30 +472,35 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) if (qir_get_op_nsrc(qinst->op) == 1) src[1] = src[0]; - needs_restore = fixup_raddr_conflict(c, dst, - &src[0], &src[1], - written_r3); + fixup_raddr_conflict(c, dst, &src[0], &src[1], + qinst, &unpack); - if (translate[qinst->op].is_mul) { + if (qir_is_mul(qinst)) { queue(c, qpu_m_alu2(translate[qinst->op].op, dst, - src[0], src[1])); + src[0], src[1]) | unpack); + set_last_cond_mul(c, qinst->cond); } else { queue(c, qpu_a_alu2(translate[qinst->op].op, dst, - src[0], src[1])); + src[0], src[1]) | unpack); + set_last_cond_add(c, qinst->cond); } - if (needs_restore) - queue(c, qpu_a_MOV(qpu_r3(), qpu_rb(31))); + handled_qinst_cond = true; + set_last_dst_pack(c, qinst); break; } - if (dst.mux == QPU_MUX_R3) - written_r3 = true; + assert(qinst->cond == QPU_COND_ALWAYS || + handled_qinst_cond); + + if (qinst->sf) + *last_inst(c) |= QPU_SF; } - qpu_schedule_instructions(c); + uint32_t cycles = qpu_schedule_instructions(c); + uint32_t inst_count_at_schedule_time = c->qpu_inst_count; /* thread end can't have VPM write or read */ if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], @@ -553,6 +526,14 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) if (qpu_inst_is_tlb(c->qpu_insts[c->qpu_inst_count - 1])) qpu_serialize_one_inst(c, qpu_NOP()); + /* Make sure there's no existing signal set (like for a small + * immediate) + */ + if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_SIG) != QPU_SIG_NONE) { + qpu_serialize_one_inst(c, qpu_NOP()); + } + c->qpu_insts[c->qpu_inst_count - 1] = qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1], QPU_SIG_PROG_END); @@ -570,6 +551,15 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) break; } + cycles += c->qpu_inst_count - inst_count_at_schedule_time; + + if (vc4_debug & VC4_DEBUG_SHADERDB) { + fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d estimated cycles\n", + qir_get_stage_name(c->stage), + c->program_id, c->variant_id, + cycles); + } + if (vc4_debug & VC4_DEBUG_QPU) vc4_dump_program(c);