X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_qpu_emit.c;h=2257dcce83be3f70c180c612abbe815d75f6fb2f;hb=ee69cfd11d34e6570c579c42f9cd8b5c8ea36bcf;hp=f02fe822b07b7b8af8592b5bac34845bfa8f4c0a;hpb=c29392751180e21a2857cade8d0b4902cbe9d001;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c b/src/gallium/drivers/vc4/vc4_qpu_emit.c index f02fe822b07..2257dcce83b 100644 --- a/src/gallium/drivers/vc4/vc4_qpu_emit.c +++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c @@ -21,23 +21,79 @@ * IN THE SOFTWARE. */ -#include #include #include "vc4_context.h" #include "vc4_qir.h" #include "vc4_qpu.h" +#include "util/ralloc.h" static void -vc4_dump_program(struct qcompile *c) +vc4_dump_program(struct vc4_compile *c) { - fprintf(stderr, "%s:\n", qir_get_stage_name(c->stage)); + fprintf(stderr, "%s prog %d/%d QPU:\n", + qir_get_stage_name(c->stage), + c->program_id, c->variant_id); - for (int i = 0; i < c->num_qpu_insts; i++) { + for (int i = 0; i < c->qpu_inst_count; i++) { fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]); vc4_qpu_disasm(&c->qpu_insts[i], 1); fprintf(stderr, "\n"); } + fprintf(stderr, "\n"); +} + +static void +queue(struct vc4_compile *c, uint64_t inst) +{ + struct queued_qpu_inst *q = rzalloc(c, struct queued_qpu_inst); + q->inst = inst; + list_addtail(&q->link, &c->qpu_inst_list); +} + +static uint64_t * +last_inst(struct vc4_compile *c) +{ + struct queued_qpu_inst *q = + (struct queued_qpu_inst *)c->qpu_inst_list.prev; + return &q->inst; +} + +static void +set_last_cond_add(struct vc4_compile *c, uint32_t cond) +{ + *last_inst(c) = qpu_set_cond_add(*last_inst(c), cond); +} + +static void +set_last_cond_mul(struct vc4_compile *c, uint32_t cond) +{ + *last_inst(c) = qpu_set_cond_mul(*last_inst(c), cond); +} + +/** + * Some special registers can be read from either file, which lets us resolve + * raddr conflicts without extra MOVs. + */ +static bool +swap_file(struct qpu_reg *src) +{ + switch (src->addr) { + case QPU_R_UNIF: + case QPU_R_VARY: + if (src->mux == QPU_MUX_SMALL_IMM) { + return false; + } else { + if (src->mux == QPU_MUX_A) + src->mux = QPU_MUX_B; + else + src->mux = QPU_MUX_A; + return true; + } + + default: + return false; + } } /** @@ -47,68 +103,117 @@ vc4_dump_program(struct qcompile *c) * address. * * In that case, we need to move one to a temporary that can be used in the - * instruction, instead. + * instruction, instead. We reserve ra31/rb31 for this purpose. */ static void -fixup_raddr_conflict(uint64_t *insts, uint32_t *ni, - struct qpu_reg src0, struct qpu_reg *src1) +fixup_raddr_conflict(struct vc4_compile *c, + struct qpu_reg dst, + struct qpu_reg *src0, struct qpu_reg *src1, + struct qinst *inst, uint64_t *unpack) { - if ((src0.mux == QPU_MUX_A || src0.mux == QPU_MUX_B) && - (src1->mux == QPU_MUX_A || src1->mux == QPU_MUX_B) && - src0.addr != src1->addr) { - insts[(*ni)++] = qpu_inst(qpu_a_MOV(qpu_r3(), *src1), - qpu_m_NOP()); - *src1 = qpu_r3(); + uint32_t mux0 = src0->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src0->mux; + uint32_t mux1 = src1->mux == QPU_MUX_SMALL_IMM ? QPU_MUX_B : src1->mux; + + if (mux0 <= QPU_MUX_R5 || + mux0 != mux1 || + (src0->addr == src1->addr && + src0->mux == src1->mux)) { + return; + } + + if (swap_file(src0) || swap_file(src1)) + return; + + if (mux0 == QPU_MUX_A) { + /* Make sure we use the same type of MOV as the instruction, + * in case of unpacks. + */ + if (qir_is_float_input(inst)) + queue(c, qpu_a_FMAX(qpu_rb(31), *src0, *src0)); + else + queue(c, qpu_a_MOV(qpu_rb(31), *src0)); + + /* If we had an unpack on this A-file source, we need to put + * it into this MOV, not into the later move from regfile B. + */ + if (inst->src[0].pack) { + *last_inst(c) |= *unpack; + *unpack = 0; + } + *src0 = qpu_rb(31); + } else { + queue(c, qpu_a_MOV(qpu_ra(31), *src0)); + *src0 = qpu_ra(31); } } -void -vc4_generate_code(struct qcompile *c) +static void +set_last_dst_pack(struct vc4_compile *c, struct qinst *inst) { - uint64_t *insts = malloc(sizeof(uint64_t) * 1024); /* XXX: sizing */ - uint32_t ni = 0; - struct qpu_reg allocate_to_qpu_reg[3 + 32 + 32]; - bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)]; - int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated)); - int *reg_uses_remaining = - calloc(c->num_temps, sizeof(*reg_uses_remaining)); - - for (int i = 0; i < ARRAY_SIZE(reg_in_use); i++) - reg_in_use[i] = false; - for (int i = 0; i < c->num_temps; i++) - reg_allocated[i] = -1; - for (int i = 0; i < 3; i++) - allocate_to_qpu_reg[i] = qpu_rn(i); - for (int i = 0; i < 32; i++) - allocate_to_qpu_reg[i + 3] = qpu_ra(i); - for (int i = 0; i < 32; i++) - allocate_to_qpu_reg[i + 3 + 32] = qpu_rb(i); - - struct simple_node *node; - foreach(node, &c->instructions) { - struct qinst *qinst = (struct qinst *)node; - - if (qinst->dst.file == QFILE_TEMP) - reg_uses_remaining[qinst->dst.index]++; - for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) { - if (qinst->src[i].file == QFILE_TEMP) - reg_uses_remaining[qinst->src[i].index]++; - } + bool had_pm = *last_inst(c) & QPU_PM; + bool had_ws = *last_inst(c) & QPU_WS; + uint32_t unpack = QPU_GET_FIELD(*last_inst(c), QPU_UNPACK); + + if (!inst->dst.pack) + return; + + *last_inst(c) |= QPU_SET_FIELD(inst->dst.pack, QPU_PACK); + + if (qir_is_mul(inst)) { + assert(!unpack || had_pm); + *last_inst(c) |= QPU_PM; + } else { + assert(!unpack || !had_pm); + assert(!had_ws); /* dst must be a-file to pack. */ } +} + +static void +handle_r4_qpu_write(struct vc4_compile *c, struct qinst *qinst, + struct qpu_reg dst) +{ + if (dst.mux != QPU_MUX_R4) + queue(c, qpu_a_MOV(dst, qpu_r4())); + else if (qinst->sf) + queue(c, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4())); +} + +void +vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) +{ + struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c); + uint32_t inputs_remaining = c->num_inputs; + uint32_t vpm_read_fifo_count = 0; + uint32_t vpm_read_offset = 0; + int last_vpm_read_index = -1; + + list_inithead(&c->qpu_inst_list); switch (c->stage) { case QSTAGE_VERT: case QSTAGE_COORD: - insts[ni++] = qpu_load_imm_ui(qpu_vrsetup(), 0x00401a00); - insts[ni++] = qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00); + /* There's a 4-entry FIFO for VPMVCD reads, each of which can + * load up to 16 dwords (4 vec4s) per vertex. + */ + while (inputs_remaining) { + uint32_t num_entries = MIN2(inputs_remaining, 16); + queue(c, qpu_load_imm_ui(qpu_vrsetup(), + vpm_read_offset | + 0x00001a00 | + ((num_entries & 0xf) << 20))); + inputs_remaining -= num_entries; + vpm_read_offset += num_entries; + vpm_read_fifo_count++; + } + assert(vpm_read_fifo_count <= 4); + + queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00)); break; case QSTAGE_FRAG: break; } - foreach(node, &c->instructions) { - struct qinst *qinst = (struct qinst *)node; - + qir_for_each_inst_inorder(qinst, c) { #if 0 fprintf(stderr, "translating qinst to qpu: "); qir_dump_inst(qinst); @@ -117,10 +222,9 @@ vc4_generate_code(struct qcompile *c) static const struct { uint32_t op; - bool is_mul; } translate[] = { -#define A(name) [QOP_##name] = {QPU_A_##name, false} -#define M(name) [QOP_##name] = {QPU_M_##name, true} +#define A(name) [QOP_##name] = {QPU_A_##name} +#define M(name) [QOP_##name] = {QPU_M_##name} A(FADD), A(FSUB), A(FMIN), @@ -128,30 +232,54 @@ vc4_generate_code(struct qcompile *c) A(FMINABS), A(FMAXABS), A(FTOI), + A(ITOF), + A(ADD), + A(SUB), + A(SHL), + A(SHR), + A(ASR), + A(MIN), + A(MAX), + A(AND), + A(OR), + A(XOR), + A(NOT), M(FMUL), + M(V8MULD), + M(V8MIN), + M(V8MAX), + M(V8ADDS), + M(V8SUBS), + M(MUL24), + + /* If we replicate src[0] out to src[1], this works + * out the same as a MOV. + */ + [QOP_MOV] = { QPU_A_OR }, + [QOP_FMOV] = { QPU_A_FMAX }, + [QOP_MMOV] = { QPU_M_V8MIN }, }; - static const uint32_t compareflags[] = { - [QOP_SEQ - QOP_SEQ] = QPU_COND_ZS, - [QOP_SNE - QOP_SEQ] = QPU_COND_ZC, - [QOP_SLT - QOP_SEQ] = QPU_COND_NS, - [QOP_SGE - QOP_SEQ] = QPU_COND_NC, - }; - + uint64_t unpack = 0; struct qpu_reg src[4]; for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) { int index = qinst->src[i].index; switch (qinst->src[i].file) { case QFILE_NULL: + case QFILE_LOAD_IMM: src[i] = qpu_rn(0); break; case QFILE_TEMP: - assert(reg_allocated[index] != -1); - src[i] = allocate_to_qpu_reg[reg_allocated[index]]; - reg_uses_remaining[index]--; - if (reg_uses_remaining[index] == 0) - reg_in_use[reg_allocated[index]] = false; + src[i] = temp_registers[index]; + if (qinst->src[i].pack) { + assert(!unpack || + unpack == qinst->src[i].pack); + unpack = QPU_SET_FIELD(qinst->src[i].pack, + QPU_UNPACK); + if (src[i].mux == QPU_MUX_R4) + unpack |= QPU_PM; + } break; case QFILE_UNIF: src[i] = qpu_unif(); @@ -159,6 +287,37 @@ vc4_generate_code(struct qcompile *c) case QFILE_VARY: src[i] = qpu_vary(); break; + case QFILE_SMALL_IMM: + src[i].mux = QPU_MUX_SMALL_IMM; + src[i].addr = qpu_encode_small_immediate(qinst->src[i].index); + /* This should only have returned a valid + * small immediate field, not ~0 for failure. + */ + assert(src[i].addr <= 47); + break; + case QFILE_VPM: + assert((int)qinst->src[i].index >= + last_vpm_read_index); + (void)last_vpm_read_index; + last_vpm_read_index = qinst->src[i].index; + src[i] = qpu_ra(QPU_R_VPM); + break; + + case QFILE_FRAG_X: + src[i] = qpu_ra(QPU_R_XY_PIXEL_COORD); + break; + case QFILE_FRAG_Y: + src[i] = qpu_rb(QPU_R_XY_PIXEL_COORD); + break; + case QFILE_FRAG_REV_FLAG: + src[i] = qpu_rb(QPU_R_MS_REV_FLAGS); + break; + + case QFILE_TLB_COLOR_WRITE: + case QFILE_TLB_COLOR_WRITE_MS: + case QFILE_TLB_Z_WRITE: + case QFILE_TLB_STENCIL_SETUP: + unreachable("bad qir src file"); } } @@ -167,159 +326,145 @@ vc4_generate_code(struct qcompile *c) case QFILE_NULL: dst = qpu_ra(QPU_W_NOP); break; - case QFILE_TEMP: - if (reg_allocated[qinst->dst.index] == -1) { - int alloc; - for (alloc = 0; - alloc < ARRAY_SIZE(reg_in_use); - alloc++) { - /* The pack flags require an A-file register. */ - if (qinst->op == QOP_PACK_SCALED && - allocate_to_qpu_reg[alloc].mux != QPU_MUX_A) { - continue; - } - - if (!reg_in_use[alloc]) - break; - } - assert(alloc != ARRAY_SIZE(reg_in_use) && "need better reg alloc"); - reg_in_use[alloc] = true; - reg_allocated[qinst->dst.index] = alloc; - } - - dst = allocate_to_qpu_reg[reg_allocated[qinst->dst.index]]; - - reg_uses_remaining[qinst->dst.index]--; - if (reg_uses_remaining[qinst->dst.index] == 0) { - reg_in_use[reg_allocated[qinst->dst.index]] = - false; - } + dst = temp_registers[qinst->dst.index]; break; - - case QFILE_VARY: - case QFILE_UNIF: - assert(!"not reached"); + case QFILE_VPM: + dst = qpu_ra(QPU_W_VPM); break; - } - switch (qinst->op) { - case QOP_MOV: - /* Skip emitting the MOV if it's a no-op. */ - if (dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B || - dst.mux != src[0].mux || dst.addr != src[0].addr) { - insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[0]), - qpu_m_NOP()); - } + case QFILE_TLB_COLOR_WRITE: + dst = qpu_tlbc(); break; - case QOP_SEQ: - case QOP_SNE: - case QOP_SGE: - case QOP_SLT: - fixup_raddr_conflict(insts, &ni, src[0], &src[1]); - insts[ni++] = qpu_inst(qpu_a_SUB(qpu_ra(QPU_W_NOP), - src[0], src[1]), - qpu_m_NOP()); - insts[ni - 1] |= QPU_SF; - - insts[ni++] = qpu_load_imm_f(dst, 0.0); - insts[ni++] = qpu_load_imm_f(dst, 1.0); - insts[ni - 1] = ((insts[ni - 1] & ~QPU_COND_ADD_MASK) - | QPU_SET_FIELD(compareflags[qinst->op - QOP_SEQ], - QPU_COND_ADD)); + case QFILE_TLB_COLOR_WRITE_MS: + dst = qpu_tlbc_ms(); + break; + case QFILE_TLB_Z_WRITE: + dst = qpu_ra(QPU_W_TLB_Z); break; - case QOP_VPM_WRITE: - insts[ni++] = qpu_inst(qpu_a_MOV(qpu_ra(QPU_W_VPM), - src[0]), - qpu_m_NOP()); + case QFILE_TLB_STENCIL_SETUP: + dst = qpu_ra(QPU_W_TLB_STENCIL_SETUP); break; - case QOP_VPM_READ: - insts[ni++] = qpu_inst(qpu_a_MOV(dst, - qpu_ra(QPU_R_VPM)), - qpu_m_NOP()); + case QFILE_VARY: + case QFILE_UNIF: + case QFILE_SMALL_IMM: + case QFILE_LOAD_IMM: + case QFILE_FRAG_X: + case QFILE_FRAG_Y: + case QFILE_FRAG_REV_FLAG: + assert(!"not reached"); break; + } + + bool handled_qinst_cond = false; + switch (qinst->op) { case QOP_RCP: case QOP_RSQ: case QOP_EXP2: case QOP_LOG2: switch (qinst->op) { case QOP_RCP: - insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP), - src[0]), - qpu_m_NOP()); + queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP), + src[0]) | unpack); break; case QOP_RSQ: - insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT), - src[0]), - qpu_m_NOP()); + queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT), + src[0]) | unpack); break; case QOP_EXP2: - insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP), - src[0]), - qpu_m_NOP()); + queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP), + src[0]) | unpack); break; case QOP_LOG2: - insts[ni++] = qpu_inst(qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG), - src[0]), - qpu_m_NOP()); + queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG), + src[0]) | unpack); break; default: abort(); } - insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP()); - insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP()); + handle_r4_qpu_write(c, qinst, dst); - insts[ni++] = qpu_inst(qpu_a_MOV(dst, qpu_r4()), - qpu_m_NOP()); + break; + case QOP_LOAD_IMM: + assert(qinst->src[0].file == QFILE_LOAD_IMM); + queue(c, qpu_load_imm_ui(dst, qinst->src[0].index)); break; - case QOP_PACK_COLORS: - for (int i = 0; i < 4; i++) { - insts[ni++] = qpu_inst(qpu_a_NOP(), - qpu_m_MOV(qpu_r3(), src[i])); - insts[ni - 1] |= QPU_PM; - insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_MUL_8A + i, - QPU_PACK); - } + case QOP_MS_MASK: + src[1] = qpu_ra(QPU_R_MS_REV_FLAGS); + fixup_raddr_conflict(c, dst, &src[0], &src[1], + qinst, &unpack); + queue(c, qpu_a_AND(qpu_ra(QPU_W_MS_FLAGS), + src[0], src[1]) | unpack); + break; - insts[ni++] = qpu_inst(qpu_a_MOV(dst, qpu_r3()), - qpu_m_NOP()); + case QOP_FRAG_Z: + case QOP_FRAG_W: + /* QOP_FRAG_Z/W don't emit instructions, just allocate + * the register to the Z/W payload. + */ break; - case QOP_TLB_COLOR_WRITE: - insts[ni++] = qpu_inst(qpu_a_MOV(qpu_tlbc(), - src[0]), - qpu_m_NOP()); + case QOP_TLB_COLOR_READ: + queue(c, qpu_NOP()); + *last_inst(c) = qpu_set_sig(*last_inst(c), + QPU_SIG_COLOR_LOAD); + handle_r4_qpu_write(c, qinst, dst); break; case QOP_VARY_ADD_C: - insts[ni++] = qpu_inst(qpu_a_FADD(dst, - src[0], qpu_r5()), - qpu_m_NOP()); + queue(c, qpu_a_FADD(dst, src[0], qpu_r5()) | unpack); break; - case QOP_PACK_SCALED: - insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[0]), - qpu_m_NOP()); - insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_A_16A, QPU_PACK); + case QOP_TEX_S: + case QOP_TEX_T: + case QOP_TEX_R: + case QOP_TEX_B: + queue(c, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S + + (qinst->op - QOP_TEX_S)), + src[0]) | unpack); + break; - insts[ni++] = qpu_inst(qpu_a_MOV(dst, src[1]), - qpu_m_NOP()); - insts[ni - 1] |= QPU_SET_FIELD(QPU_PACK_A_16B, QPU_PACK); + case QOP_TEX_DIRECT: + fixup_raddr_conflict(c, dst, &src[0], &src[1], + qinst, &unpack); + queue(c, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S), + src[0], src[1]) | unpack); + break; + case QOP_TEX_RESULT: + queue(c, qpu_NOP()); + *last_inst(c) = qpu_set_sig(*last_inst(c), + QPU_SIG_LOAD_TMU0); + handle_r4_qpu_write(c, qinst, dst); + break; + + case QOP_BRANCH: + /* The branch target will be updated at QPU scheduling + * time. + */ + queue(c, (qpu_branch(qinst->cond, 0) | + QPU_BRANCH_REL)); + handled_qinst_cond = true; break; default: assert(qinst->op < ARRAY_SIZE(translate)); assert(translate[qinst->op].op != 0); /* NOPs */ + /* Skip emitting the MOV if it's a no-op. */ + if (qir_is_raw_mov(qinst) && + dst.mux == src[0].mux && dst.addr == src[0].addr) { + break; + } + /* If we have only one source, put it in the second * argument slot as well so that we don't take up * another raddr just to get unused data. @@ -327,51 +472,98 @@ vc4_generate_code(struct qcompile *c) if (qir_get_op_nsrc(qinst->op) == 1) src[1] = src[0]; - fixup_raddr_conflict(insts, &ni, src[0], &src[1]); + fixup_raddr_conflict(c, dst, &src[0], &src[1], + qinst, &unpack); - if (translate[qinst->op].is_mul) { - insts[ni++] = qpu_inst(qpu_a_NOP(), - qpu_m_alu2(translate[qinst->op].op, - dst, src[0], src[1])); + if (qir_is_mul(qinst)) { + queue(c, qpu_m_alu2(translate[qinst->op].op, + dst, + src[0], src[1]) | unpack); + set_last_cond_mul(c, qinst->cond); } else { - insts[ni++] = qpu_inst(qpu_a_alu2(translate[qinst->op].op, - dst, src[0], src[1]), - qpu_m_NOP()); + queue(c, qpu_a_alu2(translate[qinst->op].op, + dst, + src[0], src[1]) | unpack); + set_last_cond_add(c, qinst->cond); } + handled_qinst_cond = true; + set_last_dst_pack(c, qinst); + break; } - if ((dst.mux == QPU_MUX_A || dst.mux == QPU_MUX_B) && - dst.addr < 32) - insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP()); + assert(qinst->cond == QPU_COND_ALWAYS || + handled_qinst_cond); + + if (qinst->sf) + *last_inst(c) |= QPU_SF; + } + + uint32_t cycles = qpu_schedule_instructions(c); + uint32_t inst_count_at_schedule_time = c->qpu_inst_count; + + /* thread end can't have VPM write or read */ + if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_WADDR_ADD) == QPU_W_VPM || + QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_WADDR_MUL) == QPU_W_VPM || + QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_RADDR_A) == QPU_R_VPM || + QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_RADDR_B) == QPU_R_VPM) { + qpu_serialize_one_inst(c, qpu_NOP()); + } + + /* thread end can't have uniform read */ + if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_RADDR_A) == QPU_R_UNIF || + QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_RADDR_B) == QPU_R_UNIF) { + qpu_serialize_one_inst(c, qpu_NOP()); } - /* thread end can't have VPM write */ - if (QPU_GET_FIELD(insts[ni - 1], QPU_WADDR_ADD) == QPU_W_VPM || - QPU_GET_FIELD(insts[ni - 1], QPU_WADDR_MUL) == QPU_W_VPM) - insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP()); + /* thread end can't have TLB operations */ + if (qpu_inst_is_tlb(c->qpu_insts[c->qpu_inst_count - 1])) + qpu_serialize_one_inst(c, qpu_NOP()); - insts[ni - 1] = qpu_set_sig(insts[ni - 1], QPU_SIG_PROG_END); - insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP()); - insts[ni++] = qpu_inst(qpu_a_NOP(), qpu_m_NOP()); + /* Make sure there's no existing signal set (like for a small + * immediate) + */ + if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_SIG) != QPU_SIG_NONE) { + qpu_serialize_one_inst(c, qpu_NOP()); + } + + c->qpu_insts[c->qpu_inst_count - 1] = + qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1], + QPU_SIG_PROG_END); + qpu_serialize_one_inst(c, qpu_NOP()); + qpu_serialize_one_inst(c, qpu_NOP()); switch (c->stage) { case QSTAGE_VERT: case QSTAGE_COORD: break; case QSTAGE_FRAG: - insts[2] = qpu_set_sig(insts[2], QPU_SIG_WAIT_FOR_SCOREBOARD); - insts[ni - 1] = qpu_set_sig(insts[ni - 1], - QPU_SIG_SCOREBOARD_UNLOCK); + c->qpu_insts[c->qpu_inst_count - 1] = + qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1], + QPU_SIG_SCOREBOARD_UNLOCK); break; } - c->qpu_insts = insts; - c->num_qpu_insts = ni; + cycles += c->qpu_inst_count - inst_count_at_schedule_time; + + if (vc4_debug & VC4_DEBUG_SHADERDB) { + fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d estimated cycles\n", + qir_get_stage_name(c->stage), + c->program_id, c->variant_id, + cycles); + } if (vc4_debug & VC4_DEBUG_QPU) vc4_dump_program(c); - vc4_qpu_validate(insts, ni); -} + vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count); + free(temp_registers); +}