X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_qpu_emit.c;h=397e6f26dd2f89713bac2d44f3c61821575bcc85;hb=c4b0dd53568fa276079f6b6bf7ba4b857ddd65a5;hp=985f2c4bdab7673dfa5a2b13be16404e00a56192;hpb=3e5325e8c9a389c087bb4943f99f7a8db9e8347c;p=mesa.git

diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c b/src/gallium/drivers/vc4/vc4_qpu_emit.c
index 985f2c4bdab..397e6f26dd2 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_emit.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c
@@ -66,6 +66,27 @@ set_last_cond_add(struct vc4_compile *c, uint32_t cond)
         *last_inst(c) = qpu_set_cond_add(*last_inst(c), cond);
 }
 
+/**
+ * Some special registers can be read from either file, which lets us resolve
+ * raddr conflicts without extra MOVs.
+ */
+static bool
+swap_file(struct qpu_reg *src)
+{
+        switch (src->addr) {
+        case QPU_R_UNIF:
+        case QPU_R_VARY:
+                if (src->mux == QPU_MUX_A)
+                        src->mux = QPU_MUX_B;
+                else
+                        src->mux = QPU_MUX_A;
+                return true;
+
+        default:
+                return false;
+        }
+}
+
 /**
  * This is used to resolve the fact that we might register-allocate two
  * different operands of an instruction to the same physical register file
@@ -77,14 +98,17 @@ set_last_cond_add(struct vc4_compile *c, uint32_t cond)
  */
 static void
 fixup_raddr_conflict(struct vc4_compile *c,
-               struct qpu_reg src0, struct qpu_reg *src1)
+                     struct qpu_reg *src0, struct qpu_reg *src1)
 {
-        if ((src0.mux != QPU_MUX_A && src0.mux != QPU_MUX_B) ||
-            src0.mux != src1->mux ||
-            src0.addr == src1->addr) {
+        if ((src0->mux != QPU_MUX_A && src0->mux != QPU_MUX_B) ||
+            src0->mux != src1->mux ||
+            src0->addr == src1->addr) {
                 return;
         }
 
+        if (swap_file(src0) || swap_file(src1))
+                return;
+
         queue(c, qpu_a_MOV(qpu_r3(), *src1));
         *src1 = qpu_r3();
 }
@@ -402,6 +426,11 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
                                             qpu_rb(QPU_R_XY_PIXEL_COORD)));
                         break;
 
+                case QOP_FRAG_REV_FLAG:
+                        queue(c, qpu_a_ITOF(dst,
+                                            qpu_rb(QPU_R_MS_REV_FLAGS)));
+                        break;
+
                 case QOP_FRAG_Z:
                 case QOP_FRAG_W:
                         /* QOP_FRAG_Z/W don't emit instructions, just allocate
@@ -528,7 +557,7 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
                         if (qir_get_op_nsrc(qinst->op) == 1)
                                 src[1] = src[0];
 
-                        fixup_raddr_conflict(c, src[0], &src[1]);
+                        fixup_raddr_conflict(c, &src[0], &src[1]);
 
                         if (translate[qinst->op].is_mul) {
                                 queue(c, qpu_m_alu2(translate[qinst->op].op,