X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_qpu_emit.c;h=7926bfd39dad38d0842ed2c61d77567d87ce28ea;hb=2e94cb66933fd7b130011b53b47e0816eb8a76d5;hp=9001643507ef728506ba1bb390abe5d74e18317e;hpb=a59da513d3229c883809ac2088c9612abcec1470;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c b/src/gallium/drivers/vc4/vc4_qpu_emit.c index 9001643507e..7926bfd39da 100644 --- a/src/gallium/drivers/vc4/vc4_qpu_emit.c +++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c @@ -96,6 +96,60 @@ swap_file(struct qpu_reg *src) } } +/** + * Sets up the VPM read FIFO before we do any VPM read. + * + * VPM reads (vertex attribute input) and VPM writes (varyings output) from + * the QPU reuse the VRI (varying interpolation) block's FIFOs to talk to the + * VPM block. In the VS/CS (unlike in the FS), the block starts out + * uninitialized, and you need to emit setup to the block before any VPM + * reads/writes. + * + * VRI has a FIFO in each direction, with each FIFO able to hold four + * 32-bit-per-vertex values. VPM reads come through the read FIFO and VPM + * writes go through the write FIFO. The read/write setup values from QPU go + * through the write FIFO as well, with a sideband signal indicating that + * they're setup values. Once a read setup reaches the other side of the + * FIFO, the VPM block will start asynchronously reading vertex attributes and + * filling the read FIFO -- that way hopefully the QPU doesn't have to block + * on reads later. + * + * VPM read setup can configure 16 32-bit-per-vertex values to be read at a + * time, which is 4 vec4s. If more than that is being read (since we support + * 8 vec4 vertex attributes), then multiple read setup writes need to be done. + * + * The existence of the FIFO makes it seem like you should be able to emit + * both setups for the 5-8 attribute cases and then do all the attribute + * reads. However, once the setup value makes it to the other end of the + * write FIFO, it will immediately update the VPM block's setup register. + * That updated setup register would be used for read FIFO fills from then on, + * breaking whatever remaining VPM values were supposed to be read into the + * read FIFO from the previous attribute set. + * + * As a result, we need to emit the read setup, pull every VPM read value from + * that setup, and only then emit the second setup if applicable. + */ +static void +setup_for_vpm_read(struct vc4_compile *c, struct qblock *block) +{ + if (c->num_inputs_in_fifo) { + c->num_inputs_in_fifo--; + return; + } + + c->num_inputs_in_fifo = MIN2(c->num_inputs_remaining, 16); + + queue(block, + qpu_load_imm_ui(qpu_vrsetup(), + c->vpm_read_offset | + 0x00001a00 | + ((c->num_inputs_in_fifo & 0xf) << 20))); + c->num_inputs_remaining -= c->num_inputs_in_fifo; + c->vpm_read_offset += c->num_inputs_in_fifo; + + c->num_inputs_in_fifo--; +} + /** * This is used to resolve the fact that we might register-allocate two * different operands of an instruction to the same physical register file @@ -103,7 +157,7 @@ swap_file(struct qpu_reg *src) * address. * * In that case, we need to move one to a temporary that can be used in the - * instruction, instead. We reserve ra31/rb31 for this purpose. + * instruction, instead. We reserve ra14/rb14 for this purpose. */ static void fixup_raddr_conflict(struct qblock *block, @@ -129,9 +183,9 @@ fixup_raddr_conflict(struct qblock *block, * in case of unpacks. */ if (qir_is_float_input(inst)) - queue(block, qpu_a_FMAX(qpu_rb(31), *src0, *src0)); + queue(block, qpu_a_FMAX(qpu_rb(14), *src0, *src0)); else - queue(block, qpu_a_MOV(qpu_rb(31), *src0)); + queue(block, qpu_a_MOV(qpu_rb(14), *src0)); /* If we had an unpack on this A-file source, we need to put * it into this MOV, not into the later move from regfile B. @@ -140,19 +194,19 @@ fixup_raddr_conflict(struct qblock *block, *last_inst(block) |= *unpack; *unpack = 0; } - *src0 = qpu_rb(31); + *src0 = qpu_rb(14); } else { - queue(block, qpu_a_MOV(qpu_ra(31), *src0)); - *src0 = qpu_ra(31); + queue(block, qpu_a_MOV(qpu_ra(14), *src0)); + *src0 = qpu_ra(14); } } static void set_last_dst_pack(struct qblock *block, struct qinst *inst) { - bool had_pm = *last_inst(block) & QPU_PM; - bool had_ws = *last_inst(block) & QPU_WS; - uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK); + ASSERTED bool had_pm = *last_inst(block) & QPU_PM; + ASSERTED bool had_ws = *last_inst(block) & QPU_WS; + ASSERTED uint32_t unpack = QPU_GET_FIELD(*last_inst(block), QPU_UNPACK); if (!inst->dst.pack) return; @@ -172,10 +226,14 @@ static void handle_r4_qpu_write(struct qblock *block, struct qinst *qinst, struct qpu_reg dst) { - if (dst.mux != QPU_MUX_R4) + if (dst.mux != QPU_MUX_R4) { queue(block, qpu_a_MOV(dst, qpu_r4())); - else if (qinst->sf) - queue(block, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4())); + set_last_cond_add(block, qinst->cond); + } else { + assert(qinst->cond == QPU_COND_ALWAYS); + if (qinst->sf) + queue(block, qpu_a_MOV(qpu_ra(QPU_W_NOP), qpu_r4())); + } } static void @@ -231,11 +289,13 @@ vc4_generate_code_block(struct vc4_compile *c, [QOP_MOV] = { QPU_A_OR }, [QOP_FMOV] = { QPU_A_FMAX }, [QOP_MMOV] = { QPU_M_V8MIN }, + + [QOP_MIN_NOIMM] = { QPU_A_MIN }, }; uint64_t unpack = 0; - struct qpu_reg src[4]; - for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) { + struct qpu_reg src[ARRAY_SIZE(qinst->src)]; + for (int i = 0; i < qir_get_nsrc(qinst); i++) { int index = qinst->src[i].index; switch (qinst->src[i].file) { case QFILE_NULL: @@ -268,6 +328,7 @@ vc4_generate_code_block(struct vc4_compile *c, assert(src[i].addr <= 47); break; case QFILE_VPM: + setup_for_vpm_read(c, block); assert((int)qinst->src[i].index >= last_vpm_read_index); (void)last_vpm_read_index; @@ -284,11 +345,19 @@ vc4_generate_code_block(struct vc4_compile *c, case QFILE_FRAG_REV_FLAG: src[i] = qpu_rb(QPU_R_MS_REV_FLAGS); break; + case QFILE_QPU_ELEMENT: + src[i] = qpu_ra(QPU_R_ELEM_QPU); + break; case QFILE_TLB_COLOR_WRITE: case QFILE_TLB_COLOR_WRITE_MS: case QFILE_TLB_Z_WRITE: case QFILE_TLB_STENCIL_SETUP: + case QFILE_TEX_S: + case QFILE_TEX_S_DIRECT: + case QFILE_TEX_T: + case QFILE_TEX_R: + case QFILE_TEX_B: unreachable("bad qir src file"); } } @@ -321,6 +390,23 @@ vc4_generate_code_block(struct vc4_compile *c, dst = qpu_ra(QPU_W_TLB_STENCIL_SETUP); break; + case QFILE_TEX_S: + case QFILE_TEX_S_DIRECT: + dst = qpu_rb(QPU_W_TMU0_S); + break; + + case QFILE_TEX_T: + dst = qpu_rb(QPU_W_TMU0_T); + break; + + case QFILE_TEX_R: + dst = qpu_rb(QPU_W_TMU0_R); + break; + + case QFILE_TEX_B: + dst = qpu_rb(QPU_W_TMU0_B); + break; + case QFILE_VARY: case QFILE_UNIF: case QFILE_SMALL_IMM: @@ -328,11 +414,12 @@ vc4_generate_code_block(struct vc4_compile *c, case QFILE_FRAG_X: case QFILE_FRAG_Y: case QFILE_FRAG_REV_FLAG: + case QFILE_QPU_ELEMENT: assert(!"not reached"); break; } - bool handled_qinst_cond = false; + ASSERTED bool handled_qinst_cond = false; switch (qinst->op) { case QOP_RCP: @@ -361,6 +448,7 @@ vc4_generate_code_block(struct vc4_compile *c, } handle_r4_qpu_write(block, qinst, dst); + handled_qinst_cond = true; break; @@ -369,6 +457,29 @@ vc4_generate_code_block(struct vc4_compile *c, queue(block, qpu_load_imm_ui(dst, qinst->src[0].index)); break; + case QOP_LOAD_IMM_U2: + queue(block, qpu_load_imm_u2(dst, qinst->src[0].index)); + break; + + case QOP_LOAD_IMM_I2: + queue(block, qpu_load_imm_i2(dst, qinst->src[0].index)); + break; + + case QOP_ROT_MUL: + /* Rotation at the hardware level occurs on the inputs + * to the MUL unit, and they must be accumulators in + * order to have the time necessary to move things. + */ + assert(src[0].mux <= QPU_MUX_R3); + + queue(block, + qpu_m_rot(dst, src[0], qinst->src[1].index - + QPU_SMALL_IMM_MUL_ROT) | unpack); + set_last_cond_mul(block, qinst->cond); + handled_qinst_cond = true; + set_last_dst_pack(block, qinst); + break; + case QOP_MS_MASK: src[1] = qpu_ra(QPU_R_MS_REV_FLAGS); fixup_raddr_conflict(block, dst, &src[0], &src[1], @@ -389,33 +500,27 @@ vc4_generate_code_block(struct vc4_compile *c, *last_inst(block) = qpu_set_sig(*last_inst(block), QPU_SIG_COLOR_LOAD); handle_r4_qpu_write(block, qinst, dst); + handled_qinst_cond = true; break; case QOP_VARY_ADD_C: queue(block, qpu_a_FADD(dst, src[0], qpu_r5()) | unpack); break; - case QOP_TEX_S: - case QOP_TEX_T: - case QOP_TEX_R: - case QOP_TEX_B: - queue(block, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S + - (qinst->op - QOP_TEX_S)), - src[0]) | unpack); - break; - - case QOP_TEX_DIRECT: - fixup_raddr_conflict(block, dst, &src[0], &src[1], - qinst, &unpack); - queue(block, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S), - src[0], src[1]) | unpack); - break; case QOP_TEX_RESULT: queue(block, qpu_NOP()); *last_inst(block) = qpu_set_sig(*last_inst(block), QPU_SIG_LOAD_TMU0); handle_r4_qpu_write(block, qinst, dst); + handled_qinst_cond = true; + break; + + case QOP_THRSW: + queue(block, qpu_NOP()); + *last_inst(block) = qpu_set_sig(*last_inst(block), + QPU_SIG_THREAD_SWITCH); + c->last_thrsw = last_inst(block); break; case QOP_BRANCH: @@ -427,6 +532,14 @@ vc4_generate_code_block(struct vc4_compile *c, handled_qinst_cond = true; break; + case QOP_UNIFORMS_RESET: + fixup_raddr_conflict(block, dst, &src[0], &src[1], + qinst, &unpack); + + queue(block, qpu_a_ADD(qpu_ra(QPU_W_UNIFORMS_ADDRESS), + src[0], src[1])); + break; + default: assert(qinst->op < ARRAY_SIZE(translate)); assert(translate[qinst->op].op != 0); /* NOPs */ @@ -441,7 +554,7 @@ vc4_generate_code_block(struct vc4_compile *c, * argument slot as well so that we don't take up * another raddr just to get unused data. */ - if (qir_get_op_nsrc(qinst->op) == 1) + if (qir_get_non_sideband_nsrc(qinst) == 1) src[1] = src[0]; fixup_raddr_conflict(block, dst, &src[0], &src[1], @@ -475,32 +588,17 @@ vc4_generate_code_block(struct vc4_compile *c, void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) { - struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c); - uint32_t inputs_remaining = c->num_inputs; - uint32_t vpm_read_fifo_count = 0; - uint32_t vpm_read_offset = 0; struct qblock *start_block = list_first_entry(&c->blocks, struct qblock, link); + struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c); + if (!temp_registers) + return; + switch (c->stage) { case QSTAGE_VERT: case QSTAGE_COORD: - /* There's a 4-entry FIFO for VPMVCD reads, each of which can - * load up to 16 dwords (4 vec4s) per vertex. - */ - while (inputs_remaining) { - uint32_t num_entries = MIN2(inputs_remaining, 16); - queue(start_block, - qpu_load_imm_ui(qpu_vrsetup(), - vpm_read_offset | - 0x00001a00 | - ((num_entries & 0xf) << 20))); - inputs_remaining -= num_entries; - vpm_read_offset += num_entries; - vpm_read_fifo_count++; - } - assert(vpm_read_fifo_count <= 4); - + c->num_inputs_remaining = c->num_inputs; queue(start_block, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00)); break; case QSTAGE_FRAG: @@ -510,6 +608,23 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) qir_for_each_block(block, c) vc4_generate_code_block(c, block, temp_registers); + /* Switch the last SIG_THRSW instruction to SIG_LAST_THRSW. + * + * LAST_THRSW is a new signal in BCM2708B0 (including Raspberry Pi) + * that ensures that a later thread doesn't try to lock the scoreboard + * and terminate before an earlier-spawned thread on the same QPU, by + * delaying switching back to the later shader until earlier has + * finished. Otherwise, if the earlier thread was hitting the same + * quad, the scoreboard would deadlock. + */ + if (c->last_thrsw) { + assert(QPU_GET_FIELD(*c->last_thrsw, QPU_SIG) == + QPU_SIG_THREAD_SWITCH); + *c->last_thrsw = ((*c->last_thrsw & ~QPU_SIG_MASK) | + QPU_SET_FIELD(QPU_SIG_LAST_THREAD_SWITCH, + QPU_SIG)); + } + uint32_t cycles = qpu_schedule_instructions(c); uint32_t inst_count_at_schedule_time = c->qpu_inst_count;