X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_qpu_emit.c;h=bbfefebbbe4f8086181a5b892997a292b8c7e5b7;hb=8786544b3e3a024ccb04bb0c85f2afc07bb57f63;hp=4e69fcbc1c4886e79664eb641a8c8eea352dabcb;hpb=4bca922878a4d433077d21d4918b1db71b3a15f7;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c b/src/gallium/drivers/vc4/vc4_qpu_emit.c index 4e69fcbc1c4..bbfefebbbe4 100644 --- a/src/gallium/drivers/vc4/vc4_qpu_emit.c +++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c @@ -66,6 +66,27 @@ set_last_cond_add(struct vc4_compile *c, uint32_t cond) *last_inst(c) = qpu_set_cond_add(*last_inst(c), cond); } +/** + * Some special registers can be read from either file, which lets us resolve + * raddr conflicts without extra MOVs. + */ +static bool +swap_file(struct qpu_reg *src) +{ + switch (src->addr) { + case QPU_R_UNIF: + case QPU_R_VARY: + if (src->mux == QPU_MUX_A) + src->mux = QPU_MUX_B; + else + src->mux = QPU_MUX_A; + return true; + + default: + return false; + } +} + /** * This is used to resolve the fact that we might register-allocate two * different operands of an instruction to the same physical register file @@ -77,14 +98,19 @@ set_last_cond_add(struct vc4_compile *c, uint32_t cond) */ static void fixup_raddr_conflict(struct vc4_compile *c, - struct qpu_reg src0, struct qpu_reg *src1) + struct qpu_reg *src0, struct qpu_reg *src1) { - if ((src0.mux == QPU_MUX_A || src0.mux == QPU_MUX_B) && - (src1->mux == QPU_MUX_A || src1->mux == QPU_MUX_B) && - src0.addr != src1->addr) { - queue(c, qpu_a_MOV(qpu_r3(), *src1)); - *src1 = qpu_r3(); + if ((src0->mux != QPU_MUX_A && src0->mux != QPU_MUX_B) || + src0->mux != src1->mux || + src0->addr == src1->addr) { + return; } + + if (swap_file(src0) || swap_file(src1)) + return; + + queue(c, qpu_a_MOV(qpu_r3(), *src1)); + *src1 = qpu_r3(); } static void @@ -208,43 +234,13 @@ serialize_insts(struct vc4_compile *c) } void -vc4_generate_code(struct vc4_compile *c) +vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c) { - struct qpu_reg allocate_to_qpu_reg[3 + 32 + 32]; - bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)]; - int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated)); - int *reg_uses_remaining = - calloc(c->num_temps, sizeof(*reg_uses_remaining)); + struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c); bool discard = false; - for (int i = 0; i < ARRAY_SIZE(reg_in_use); i++) - reg_in_use[i] = false; - for (int i = 0; i < c->num_temps; i++) - reg_allocated[i] = -1; - for (int i = 0; i < 3; i++) - allocate_to_qpu_reg[i] = qpu_rn(i); - for (int i = 0; i < 32; i++) - allocate_to_qpu_reg[i + 3] = qpu_ra(i); - for (int i = 0; i < 32; i++) - allocate_to_qpu_reg[i + 3 + 32] = qpu_rb(i); - make_empty_list(&c->qpu_inst_list); - struct simple_node *node; - foreach(node, &c->instructions) { - struct qinst *qinst = (struct qinst *)node; - - if (qinst->dst.file == QFILE_TEMP) - reg_uses_remaining[qinst->dst.index]++; - for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) { - if (qinst->src[i].file == QFILE_TEMP) - reg_uses_remaining[qinst->src[i].index]++; - } - if (qinst->op == QOP_TLB_PASSTHROUGH_Z_WRITE || - qinst->op == QOP_FRAG_Z) - reg_in_use[3 + 32 + QPU_R_FRAG_PAYLOAD_ZW] = true; - } - switch (c->stage) { case QSTAGE_VERT: case QSTAGE_COORD: @@ -257,6 +253,7 @@ vc4_generate_code(struct vc4_compile *c) break; } + struct simple_node *node; foreach(node, &c->instructions) { struct qinst *qinst = (struct qinst *)node; @@ -304,18 +301,7 @@ vc4_generate_code(struct vc4_compile *c) src[i] = qpu_rn(0); break; case QFILE_TEMP: - if (reg_allocated[index] == -1) { - fprintf(stderr, "undefined reg use: "); - qir_dump_inst(qinst); - fprintf(stderr, "\n"); - - src[i] = qpu_rn(0); - } else { - src[i] = allocate_to_qpu_reg[reg_allocated[index]]; - reg_uses_remaining[index]--; - if (reg_uses_remaining[index] == 0) - reg_in_use[reg_allocated[index]] = false; - } + src[i] = temp_registers[index]; break; case QFILE_UNIF: src[i] = qpu_unif(); @@ -331,36 +317,9 @@ vc4_generate_code(struct vc4_compile *c) case QFILE_NULL: dst = qpu_ra(QPU_W_NOP); break; - case QFILE_TEMP: - if (reg_allocated[qinst->dst.index] == -1) { - int alloc; - for (alloc = 0; - alloc < ARRAY_SIZE(reg_in_use); - alloc++) { - /* The pack flags require an A-file register. */ - if (qinst->op == QOP_PACK_SCALED && - allocate_to_qpu_reg[alloc].mux != QPU_MUX_A) { - continue; - } - - if (!reg_in_use[alloc]) - break; - } - assert(alloc != ARRAY_SIZE(reg_in_use) && "need better reg alloc"); - reg_in_use[alloc] = true; - reg_allocated[qinst->dst.index] = alloc; - } - - dst = allocate_to_qpu_reg[reg_allocated[qinst->dst.index]]; - - reg_uses_remaining[qinst->dst.index]--; - if (reg_uses_remaining[qinst->dst.index] == 0) { - reg_in_use[reg_allocated[qinst->dst.index]] = - false; - } + dst = temp_registers[qinst->dst.index]; break; - case QFILE_VARY: case QFILE_UNIF: assert(!"not reached"); @@ -377,7 +336,6 @@ vc4_generate_code(struct vc4_compile *c) break; case QOP_SF: - fixup_raddr_conflict(c, src[0], &src[1]); queue(c, qpu_a_MOV(qpu_ra(QPU_W_NOP), src[0])); *last_inst(c) |= QPU_SF; break; @@ -469,15 +427,10 @@ vc4_generate_code(struct vc4_compile *c) break; case QOP_FRAG_Z: - queue(c, qpu_a_ITOF(dst, - qpu_rb(QPU_R_FRAG_PAYLOAD_ZW))); - break; - - case QOP_FRAG_RCP_W: - queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP), - qpu_ra(QPU_R_FRAG_PAYLOAD_ZW))); - - queue(c, qpu_a_MOV(dst, qpu_r4())); + case QOP_FRAG_W: + /* QOP_FRAG_Z/W don't emit instructions, just allocate + * the register to the Z/W payload. + */ break; case QOP_TLB_DISCARD_SETUP: @@ -486,9 +439,12 @@ vc4_generate_code(struct vc4_compile *c) *last_inst(c) |= QPU_SF; break; - case QOP_TLB_PASSTHROUGH_Z_WRITE: - queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z), - qpu_rb(QPU_R_FRAG_PAYLOAD_ZW))); + case QOP_TLB_STENCIL_SETUP: + queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_STENCIL_SETUP), src[0])); + break; + + case QOP_TLB_Z_WRITE: + queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z), src[0])); if (discard) { set_last_cond_add(c, QPU_COND_ZS); } @@ -550,15 +506,41 @@ vc4_generate_code(struct vc4_compile *c) case QOP_R4_UNPACK_B: case QOP_R4_UNPACK_C: case QOP_R4_UNPACK_D: - queue(c, qpu_a_MOV(dst, qpu_r4())); + assert(src[0].mux == QPU_MUX_R4); + queue(c, qpu_a_MOV(dst, src[0])); *last_inst(c) |= QPU_PM; - *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_R4_8A + + *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A + (qinst->op - QOP_R4_UNPACK_A), QPU_UNPACK); break; + case QOP_UNPACK_8A: + case QOP_UNPACK_8B: + case QOP_UNPACK_8C: + case QOP_UNPACK_8D: { + assert(src[0].mux == QPU_MUX_A); + + /* And, since we're setting the pack bits, if the + * destination is in A it would get re-packed. + */ + struct qpu_reg orig_dst = dst; + if (orig_dst.mux == QPU_MUX_A) + dst = qpu_rn(3); + + queue(c, qpu_a_FMAX(dst, src[0], src[0])); + *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A + + (qinst->op - + QOP_UNPACK_8A), + QPU_UNPACK); + + if (orig_dst.mux == QPU_MUX_A) { + queue(c, qpu_a_MOV(orig_dst, dst)); + } + } + break; + default: assert(qinst->op < ARRAY_SIZE(translate)); assert(translate[qinst->op].op != 0); /* NOPs */ @@ -570,7 +552,7 @@ vc4_generate_code(struct vc4_compile *c) if (qir_get_op_nsrc(qinst->op) == 1) src[1] = src[0]; - fixup_raddr_conflict(c, src[0], &src[1]); + fixup_raddr_conflict(c, &src[0], &src[1]); if (translate[qinst->op].is_mul) { queue(c, qpu_m_alu2(translate[qinst->op].op, @@ -595,6 +577,14 @@ vc4_generate_code(struct vc4_compile *c) serialize_one_inst(c, qpu_NOP()); } + /* thread end can't have uniform read */ + if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_RADDR_A) == QPU_R_UNIF || + QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1], + QPU_RADDR_B) == QPU_R_UNIF) { + serialize_one_inst(c, qpu_NOP()); + } + c->qpu_insts[c->qpu_inst_count - 1] = qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1], QPU_SIG_PROG_END); @@ -616,4 +606,6 @@ vc4_generate_code(struct vc4_compile *c) vc4_dump_program(c); vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count); + + free(temp_registers); }