X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_register_allocate.c;h=203b459abf89ddf8c33646982540ad725b9c509b;hb=0adf2ec0eefa70905fb9ca45c1681149c0688ce9;hp=204c080467e194fa3c8573a1c12839cf2d3963ce;hpb=71e5ba9c011939c962018af7f3ca78b600c95148;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_register_allocate.c b/src/gallium/drivers/vc4/vc4_register_allocate.c index 204c080467e..203b459abf8 100644 --- a/src/gallium/drivers/vc4/vc4_register_allocate.c +++ b/src/gallium/drivers/vc4/vc4_register_allocate.c @@ -36,110 +36,135 @@ static const struct qpu_reg vc4_regs[] = { { QPU_MUX_R3, 0}, { QPU_MUX_R4, 0}, QPU_R(A, 0), - QPU_R(A, 1), - QPU_R(A, 2), - QPU_R(A, 3), - QPU_R(A, 4), - QPU_R(A, 5), - QPU_R(A, 6), - QPU_R(A, 7), - QPU_R(A, 8), - QPU_R(A, 9), - QPU_R(A, 10), - QPU_R(A, 11), - QPU_R(A, 12), - QPU_R(A, 13), - QPU_R(A, 14), - QPU_R(A, 15), - QPU_R(A, 16), - QPU_R(A, 17), - QPU_R(A, 18), - QPU_R(A, 19), - QPU_R(A, 20), - QPU_R(A, 21), - QPU_R(A, 22), - QPU_R(A, 23), - QPU_R(A, 24), - QPU_R(A, 25), - QPU_R(A, 26), - QPU_R(A, 27), - QPU_R(A, 28), - QPU_R(A, 29), - QPU_R(A, 30), - QPU_R(A, 31), QPU_R(B, 0), + QPU_R(A, 1), QPU_R(B, 1), + QPU_R(A, 2), QPU_R(B, 2), + QPU_R(A, 3), QPU_R(B, 3), + QPU_R(A, 4), QPU_R(B, 4), + QPU_R(A, 5), QPU_R(B, 5), + QPU_R(A, 6), QPU_R(B, 6), + QPU_R(A, 7), QPU_R(B, 7), + QPU_R(A, 8), QPU_R(B, 8), + QPU_R(A, 9), QPU_R(B, 9), + QPU_R(A, 10), QPU_R(B, 10), + QPU_R(A, 11), QPU_R(B, 11), + QPU_R(A, 12), QPU_R(B, 12), + QPU_R(A, 13), QPU_R(B, 13), + QPU_R(A, 14), QPU_R(B, 14), + QPU_R(A, 15), QPU_R(B, 15), + QPU_R(A, 16), QPU_R(B, 16), + QPU_R(A, 17), QPU_R(B, 17), + QPU_R(A, 18), QPU_R(B, 18), + QPU_R(A, 19), QPU_R(B, 19), + QPU_R(A, 20), QPU_R(B, 20), + QPU_R(A, 21), QPU_R(B, 21), + QPU_R(A, 22), QPU_R(B, 22), + QPU_R(A, 23), QPU_R(B, 23), + QPU_R(A, 24), QPU_R(B, 24), + QPU_R(A, 25), QPU_R(B, 25), + QPU_R(A, 26), QPU_R(B, 26), + QPU_R(A, 27), QPU_R(B, 27), + QPU_R(A, 28), QPU_R(B, 28), + QPU_R(A, 29), QPU_R(B, 29), + QPU_R(A, 30), QPU_R(B, 30), + QPU_R(A, 31), QPU_R(B, 31), }; #define ACC_INDEX 0 -#define A_INDEX (ACC_INDEX + 5) -#define B_INDEX (A_INDEX + 32) +#define AB_INDEX (ACC_INDEX + 5) static void vc4_alloc_reg_set(struct vc4_context *vc4) { - assert(vc4_regs[A_INDEX].addr == 0); - assert(vc4_regs[B_INDEX].addr == 0); - STATIC_ASSERT(ARRAY_SIZE(vc4_regs) == B_INDEX + 32); + assert(vc4_regs[AB_INDEX].addr == 0); + assert(vc4_regs[AB_INDEX + 1].addr == 0); + STATIC_ASSERT(ARRAY_SIZE(vc4_regs) == AB_INDEX + 64); if (vc4->regs) return; - vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs)); + vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs), true); vc4->reg_class_any = ra_alloc_reg_class(vc4->regs); + vc4->reg_class_a_or_b_or_acc = ra_alloc_reg_class(vc4->regs); + vc4->reg_class_r4_or_a = ra_alloc_reg_class(vc4->regs); + vc4->reg_class_a = ra_alloc_reg_class(vc4->regs); for (uint32_t i = 0; i < ARRAY_SIZE(vc4_regs); i++) { - /* Reserve r3 for now, since we're using it for spilling-like - * operations in vc4_qpu_emit.c + /* Reserve ra31/rb31 for spilling fixup_raddr_conflict() in + * vc4_qpu_emit.c */ - if (vc4_regs[i].mux == QPU_MUX_R3) + if (vc4_regs[i].addr == 31) continue; /* R4 can't be written as a general purpose register. (it's * TMU_NOSWAP as a write address). */ - if (vc4_regs[i].mux == QPU_MUX_R4) + if (vc4_regs[i].mux == QPU_MUX_R4) { + ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a, i); + ra_class_add_reg(vc4->regs, vc4->reg_class_any, i); continue; + } ra_class_add_reg(vc4->regs, vc4->reg_class_any, i); + ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc, i); } - vc4->reg_class_a = ra_alloc_reg_class(vc4->regs); - for (uint32_t i = A_INDEX; i < A_INDEX + 32; i++) + for (uint32_t i = AB_INDEX; i < AB_INDEX + 64; i += 2) { ra_class_add_reg(vc4->regs, vc4->reg_class_a, i); + ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a, i); + } ra_set_finalize(vc4->regs, NULL); } +struct node_to_temp_map { + uint32_t temp; + uint32_t priority; +}; + +static int +node_to_temp_priority(const void *in_a, const void *in_b) +{ + const struct node_to_temp_map *a = in_a; + const struct node_to_temp_map *b = in_b; + + return a->priority - b->priority; +} + +#define CLASS_BIT_A (1 << 0) +#define CLASS_BIT_B_OR_ACC (1 << 1) +#define CLASS_BIT_R4 (1 << 2) + /** * Returns a mapping from QFILE_TEMP indices to struct qpu_regs. * @@ -148,13 +173,11 @@ vc4_alloc_reg_set(struct vc4_context *vc4) struct qpu_reg * vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c) { - struct simple_node *node; - uint32_t def[c->num_temps]; - uint32_t use[c->num_temps]; + struct node_to_temp_map map[c->num_temps]; + uint32_t temp_to_node[c->num_temps]; + uint8_t class_bits[c->num_temps]; struct qpu_reg *temp_registers = calloc(c->num_temps, sizeof(*temp_registers)); - memset(def, 0, sizeof(def)); - memset(use, 0, sizeof(use)); /* If things aren't ever written (undefined values), just read from * r0. @@ -167,70 +190,138 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c) struct ra_graph *g = ra_alloc_interference_graph(vc4->regs, c->num_temps); - for (uint32_t i = 0; i < c->num_temps; i++) - ra_set_node_class(g, i, vc4->reg_class_any); + /* Compute the live ranges so we can figure out interference. */ + qir_calculate_live_intervals(c); - /* Compute the live ranges so we can figure out interference, and - * figure out our register classes and preallocated registers. + for (uint32_t i = 0; i < c->num_temps; i++) { + map[i].temp = i; + map[i].priority = c->temp_end[i] - c->temp_start[i]; + } + qsort(map, c->num_temps, sizeof(map[0]), node_to_temp_priority); + for (uint32_t i = 0; i < c->num_temps; i++) { + temp_to_node[map[i].temp] = i; + } + + /* Figure out our register classes and preallocated registers. We + * start with any temp being able to be in any file, then instructions + * incrementally remove bits that the temp definitely can't be in. */ - uint32_t ip = 0; - foreach(node, &c->instructions) { - struct qinst *inst = (struct qinst *)node; + memset(class_bits, + CLASS_BIT_A | CLASS_BIT_B_OR_ACC | CLASS_BIT_R4, + sizeof(class_bits)); - if (inst->dst.file == QFILE_TEMP) { - def[inst->dst.index] = ip; - use[inst->dst.index] = ip; - } - - for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) { - if (inst->src[i].file == QFILE_TEMP) - use[inst->src[i].index] = ip; + int ip = 0; + qir_for_each_inst_inorder(inst, c) { + if (qir_writes_r4(inst)) { + /* This instruction writes r4 (and optionally moves + * its result to a temp), so nothing else can be + * stored in r4 across it. + */ + for (int i = 0; i < c->num_temps; i++) { + if (c->temp_start[i] < ip && c->temp_end[i] > ip) + class_bits[i] &= ~CLASS_BIT_R4; + } + } else { + /* R4 can't be written as a general purpose + * register. (it's TMU_NOSWAP as a write address). + */ + if (inst->dst.file == QFILE_TEMP) + class_bits[inst->dst.index] &= ~CLASS_BIT_R4; } switch (inst->op) { case QOP_FRAG_Z: - def[inst->dst.index] = 0; - ra_set_node_reg(g, inst->dst.index, - B_INDEX + QPU_R_FRAG_PAYLOAD_ZW); + ra_set_node_reg(g, temp_to_node[inst->dst.index], + AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2 + 1); break; case QOP_FRAG_W: - def[inst->dst.index] = 0; - ra_set_node_reg(g, inst->dst.index, - A_INDEX + QPU_R_FRAG_PAYLOAD_ZW); + ra_set_node_reg(g, temp_to_node[inst->dst.index], + AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2); break; - case QOP_TEX_RESULT: - case QOP_TLB_COLOR_READ: - assert(vc4_regs[ACC_INDEX + 4].mux == QPU_MUX_R4); - ra_set_node_reg(g, inst->dst.index, - ACC_INDEX + 4); + default: break; + } - case QOP_PACK_SCALED: - /* The pack flags require an A-file dst register. */ - ra_set_node_class(g, inst->dst.index, vc4->reg_class_a); - break; + if (inst->dst.pack && !qir_is_mul(inst)) { + /* The non-MUL pack flags require an A-file dst + * register. + */ + class_bits[inst->dst.index] &= CLASS_BIT_A; + } - default: - break; + /* Apply restrictions for src unpacks. The integer unpacks + * can only be done from regfile A, while float unpacks can be + * either A or R4. + */ + for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) { + if (inst->src[i].file == QFILE_TEMP && + inst->src[i].pack) { + if (qir_is_float_input(inst)) { + class_bits[inst->src[i].index] &= + CLASS_BIT_A | CLASS_BIT_R4; + } else { + class_bits[inst->src[i].index] &= + CLASS_BIT_A; + } + } } ip++; } + for (uint32_t i = 0; i < c->num_temps; i++) { + int node = temp_to_node[i]; + + switch (class_bits[i]) { + case CLASS_BIT_A | CLASS_BIT_B_OR_ACC | CLASS_BIT_R4: + ra_set_node_class(g, node, vc4->reg_class_any); + break; + case CLASS_BIT_A | CLASS_BIT_B_OR_ACC: + ra_set_node_class(g, node, vc4->reg_class_a_or_b_or_acc); + break; + case CLASS_BIT_A | CLASS_BIT_R4: + ra_set_node_class(g, node, vc4->reg_class_r4_or_a); + break; + case CLASS_BIT_A: + ra_set_node_class(g, node, vc4->reg_class_a); + break; + default: + fprintf(stderr, "temp %d: bad class bits: 0x%x\n", + i, class_bits[i]); + abort(); + break; + } + } + for (uint32_t i = 0; i < c->num_temps; i++) { for (uint32_t j = i + 1; j < c->num_temps; j++) { - if (!(def[i] >= use[j] || def[j] >= use[i])) - ra_add_node_interference(g, i, j); + if (!(c->temp_start[i] >= c->temp_end[j] || + c->temp_start[j] >= c->temp_end[i])) { + ra_add_node_interference(g, + temp_to_node[i], + temp_to_node[j]); + } } } bool ok = ra_allocate(g); - assert(ok); + if (!ok) { + fprintf(stderr, "Failed to register allocate:\n"); + qir_dump(c); + abort(); + } - for (uint32_t i = 0; i < c->num_temps; i++) - temp_registers[i] = vc4_regs[ra_get_node_reg(g, i)]; + for (uint32_t i = 0; i < c->num_temps; i++) { + temp_registers[i] = vc4_regs[ra_get_node_reg(g, temp_to_node[i])]; + + /* If the value's never used, just write to the NOP register + * for clarity in debug output. + */ + if (c->temp_start[i] == c->temp_end[i]) + temp_registers[i] = qpu_ra(QPU_W_NOP); + } ralloc_free(g);