X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_state.c;h=1e4657a79227394084dcc8a13eefb1e75f517cc6;hb=9b24028426702f8d4c8c1f563ff9d32b99532357;hp=a234ce53b20ce1b1a495b7fd626f9a4b43f286bc;hpb=1469ccb7464836c752fa2664c36d8fae7e80606c;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_state.c b/src/gallium/drivers/vc4/vc4_state.c index a234ce53b20..1e4657a7922 100644 --- a/src/gallium/drivers/vc4/vc4_state.c +++ b/src/gallium/drivers/vc4/vc4_state.c @@ -23,6 +23,7 @@ */ #include "pipe/p_state.h" +#include "util/u_framebuffer.h" #include "util/u_inlines.h" #include "util/u_math.h" #include "util/u_memory.h" @@ -79,7 +80,7 @@ static void vc4_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask) { struct vc4_context *vc4 = vc4_context(pctx); - vc4->sample_mask = (uint16_t)sample_mask; + vc4->sample_mask = sample_mask & ((1 << VC4_MAX_SAMPLES) - 1); vc4->dirty |= VC4_DIRTY_SAMPLE_MASK; } @@ -94,6 +95,9 @@ vc4_create_rasterizer_state(struct pipe_context *pctx, const struct pipe_rasterizer_state *cso) { struct vc4_rasterizer_state *so; + struct V3D21_DEPTH_OFFSET depth_offset = { V3D21_DEPTH_OFFSET_header }; + struct V3D21_POINT_SIZE point_size = { V3D21_POINT_SIZE_header }; + struct V3D21_LINE_WIDTH line_width = { V3D21_LINE_WIDTH_header }; so = CALLOC_STRUCT(vc4_rasterizer_state); if (!so) @@ -109,7 +113,9 @@ vc4_create_rasterizer_state(struct pipe_context *pctx, /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835, * BCM21553). */ - so->point_size = MAX2(cso->point_size, .125f); + point_size.point_size = MAX2(cso->point_size, .125f); + + line_width.line_width = cso->line_width; if (cso->front_ccw) so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; @@ -117,8 +123,29 @@ vc4_create_rasterizer_state(struct pipe_context *pctx, if (cso->offset_tri) { so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; - so->offset_units = float_to_187_half(cso->offset_units); - so->offset_factor = float_to_187_half(cso->offset_scale); + depth_offset.depth_offset_units = + float_to_187_half(cso->offset_units); + depth_offset.depth_offset_factor = + float_to_187_half(cso->offset_scale); + } + + if (cso->multisample) + so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; + + V3D21_DEPTH_OFFSET_pack(NULL, so->packed.depth_offset, &depth_offset); + V3D21_POINT_SIZE_pack(NULL, so->packed.point_size, &point_size); + V3D21_LINE_WIDTH_pack(NULL, so->packed.line_width, &line_width); + + if (cso->tile_raster_order_fixed) { + so->tile_raster_order_flags |= VC4_SUBMIT_CL_FIXED_RCL_ORDER; + if (cso->tile_raster_order_increasing_x) { + so->tile_raster_order_flags |= + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X; + } + if (cso->tile_raster_order_increasing_y) { + so->tile_raster_order_flags |= + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y; + } } return so; @@ -298,24 +325,6 @@ vc4_set_vertex_buffers(struct pipe_context *pctx, vc4->dirty |= VC4_DIRTY_VTXBUF; } -static void -vc4_set_index_buffer(struct pipe_context *pctx, - const struct pipe_index_buffer *ib) -{ - struct vc4_context *vc4 = vc4_context(pctx); - - if (ib) { - pipe_resource_reference(&vc4->indexbuf.buffer, ib->buffer); - vc4->indexbuf.index_size = ib->index_size; - vc4->indexbuf.offset = ib->offset; - vc4->indexbuf.user_buffer = ib->user_buffer; - } else { - pipe_resource_reference(&vc4->indexbuf.buffer, NULL); - } - - vc4->dirty |= VC4_DIRTY_INDEXBUF; -} - static void vc4_blend_state_bind(struct pipe_context *pctx, void *hwcso) { @@ -371,14 +380,13 @@ vc4_vertex_state_bind(struct pipe_context *pctx, void *hwcso) } static void -vc4_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index, - struct pipe_constant_buffer *cb) +vc4_set_constant_buffer(struct pipe_context *pctx, + enum pipe_shader_type shader, uint index, + const struct pipe_constant_buffer *cb) { struct vc4_context *vc4 = vc4_context(pctx); struct vc4_constbuf_stateobj *so = &vc4->constbuf[shader]; - assert(index == 0); - /* Note that the state tracker can unbind constant buffers by * passing NULL here. */ @@ -388,7 +396,10 @@ vc4_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index, return; } - assert(!cb->buffer); + if (index == 1 && so->cb[index].buffer_size != cb->buffer_size) + vc4->dirty |= VC4_DIRTY_UBO_1_SIZE; + + pipe_resource_reference(&so->cb[index].buffer, cb->buffer); so->cb[index].buffer_offset = cb->buffer_offset; so->cb[index].buffer_size = cb->buffer_size; so->cb[index].user_buffer = cb->user_buffer; @@ -404,38 +415,10 @@ vc4_set_framebuffer_state(struct pipe_context *pctx, { struct vc4_context *vc4 = vc4_context(pctx); struct pipe_framebuffer_state *cso = &vc4->framebuffer; - unsigned i; - - vc4_flush(pctx); - - for (i = 0; i < framebuffer->nr_cbufs; i++) - pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]); - for (; i < vc4->framebuffer.nr_cbufs; i++) - pipe_surface_reference(&cso->cbufs[i], NULL); - cso->nr_cbufs = framebuffer->nr_cbufs; + vc4->job = NULL; - pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf); - - cso->width = framebuffer->width; - cso->height = framebuffer->height; - - /* If we're binding to uninitialized buffers, no need to load their - * contents before drawing.. - */ - if (cso->cbufs[0]) { - struct vc4_resource *rsc = - vc4_resource(cso->cbufs[0]->texture); - if (!rsc->writes) - vc4->cleared |= PIPE_CLEAR_COLOR0; - } - - if (cso->zsbuf) { - struct vc4_resource *rsc = - vc4_resource(cso->zsbuf->texture); - if (!rsc->writes) - vc4->cleared |= PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL; - } + util_copy_framebuffer_state(cso, framebuffer); /* Nonzero texture mipmap levels are laid out as if they were in * power-of-two-sized spaces. The renderbuffer config infers its @@ -461,10 +444,8 @@ vc4_set_framebuffer_state(struct pipe_context *pctx, } static struct vc4_texture_stateobj * -vc4_get_stage_tex(struct vc4_context *vc4, unsigned shader) +vc4_get_stage_tex(struct vc4_context *vc4, enum pipe_shader_type shader) { - vc4->dirty |= VC4_DIRTY_TEXSTATE; - switch (shader) { case PIPE_SHADER_FRAGMENT: vc4->dirty |= VC4_DIRTY_FRAGTEX; @@ -542,7 +523,7 @@ vc4_create_sampler_state(struct pipe_context *pctx, static void vc4_sampler_states_bind(struct pipe_context *pctx, - unsigned shader, unsigned start, + enum pipe_shader_type shader, unsigned start, unsigned nr, void **hwcso) { struct vc4_context *vc4 = vc4_context(pctx); @@ -556,12 +537,10 @@ vc4_sampler_states_bind(struct pipe_context *pctx, if (hwcso[i]) new_nr = i + 1; stage_tex->samplers[i] = hwcso[i]; - stage_tex->dirty_samplers |= (1 << i); } for (; i < stage_tex->num_samplers; i++) { stage_tex->samplers[i] = NULL; - stage_tex->dirty_samplers |= (1 << i); } stage_tex->num_samplers = new_nr; @@ -571,7 +550,7 @@ static struct pipe_sampler_view * vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, const struct pipe_sampler_view *cso) { - struct vc4_sampler_view *so = malloc(sizeof(*so)); + struct vc4_sampler_view *so = CALLOC_STRUCT(vc4_sampler_view); struct vc4_resource *rsc = vc4_resource(prsc); if (!so) @@ -579,7 +558,10 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, so->base = *cso; - pipe_reference(NULL, &prsc->reference); + so->base.texture = NULL; + pipe_resource_reference(&so->base.texture, prsc); + so->base.reference.count = 1; + so->base.context = pctx; /* There is no hardware level clamping, and the start address of a * texture may be misaligned, so in that case we have to copy to a @@ -588,38 +570,57 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, * Also, Raspberry Pi doesn't support sampling from raster textures, * so we also have to copy to a temporary then. */ - if (cso->u.tex.first_level || - rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R) { - struct vc4_resource *shadow_parent = vc4_resource(prsc); - struct pipe_resource tmpl = shadow_parent->base.b; - struct vc4_resource *clone; - - tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; - tmpl.width0 = u_minify(tmpl.width0, cso->u.tex.first_level); - tmpl.height0 = u_minify(tmpl.height0, cso->u.tex.first_level); - tmpl.last_level = cso->u.tex.last_level - cso->u.tex.first_level; - + if ((cso->u.tex.first_level && + (cso->u.tex.first_level != cso->u.tex.last_level)) || + rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R || + rsc->vc4_format == ~0) { + struct vc4_resource *shadow_parent = rsc; + struct pipe_resource tmpl = { + .target = prsc->target, + .format = prsc->format, + .width0 = u_minify(prsc->width0, + cso->u.tex.first_level), + .height0 = u_minify(prsc->height0, + cso->u.tex.first_level), + .bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET, + .last_level = cso->u.tex.last_level - cso->u.tex.first_level, + .nr_samples = prsc->nr_samples, + }; + + /* Create the shadow texture. The rest of the texture + * parameter setup will use the shadow. + */ prsc = vc4_resource_create(pctx->screen, &tmpl); if (!prsc) { free(so); return NULL; } rsc = vc4_resource(prsc); - clone = vc4_resource(prsc); - clone->shadow_parent = &shadow_parent->base.b; + vc4_bo_label(vc4_screen(pctx->screen), rsc->bo, + "tiling shadow %dx%d", + tmpl.width0, tmpl.height0); + /* Flag it as needing update of the contents from the parent. */ - clone->writes = shadow_parent->writes - 1; + rsc->writes = shadow_parent->writes - 1; + assert(rsc->vc4_format != VC4_TEXTURE_TYPE_RGBA32R); + + so->texture = prsc; + } else { + pipe_resource_reference(&so->texture, prsc); - assert(clone->vc4_format != VC4_TEXTURE_TYPE_RGBA32R); + if (cso->u.tex.first_level) { + so->force_first_level = true; + } } - so->base.texture = prsc; - so->base.reference.count = 1; - so->base.context = pctx; so->texture_p0 = - (VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) | + (VC4_SET_FIELD((rsc->slices[0].offset + + cso->u.tex.first_layer * + rsc->cube_map_stride) >> 12, VC4_TEX_P0_OFFSET) | VC4_SET_FIELD(rsc->vc4_format & 15, VC4_TEX_P0_TYPE) | - VC4_SET_FIELD(cso->u.tex.last_level - + VC4_SET_FIELD(so->force_first_level ? + cso->u.tex.last_level : + cso->u.tex.last_level - cso->u.tex.first_level, VC4_TEX_P0_MIPLVLS) | VC4_SET_FIELD(cso->target == PIPE_TEXTURE_CUBE, VC4_TEX_P0_CMMODE)); @@ -628,19 +629,25 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, VC4_SET_FIELD(prsc->height0 & 2047, VC4_TEX_P1_HEIGHT) | VC4_SET_FIELD(prsc->width0 & 2047, VC4_TEX_P1_WIDTH)); + if (prsc->format == PIPE_FORMAT_ETC1_RGB8) + so->texture_p1 |= VC4_TEX_P1_ETCFLIP_MASK; + return &so->base; } static void vc4_sampler_view_destroy(struct pipe_context *pctx, - struct pipe_sampler_view *view) + struct pipe_sampler_view *pview) { + struct vc4_sampler_view *view = vc4_sampler_view(pview); + pipe_resource_reference(&pview->texture, NULL); pipe_resource_reference(&view->texture, NULL); free(view); } static void -vc4_set_sampler_views(struct pipe_context *pctx, unsigned shader, +vc4_set_sampler_views(struct pipe_context *pctx, + enum pipe_shader_type shader, unsigned start, unsigned nr, struct pipe_sampler_view **views) { @@ -651,18 +658,14 @@ vc4_set_sampler_views(struct pipe_context *pctx, unsigned shader, assert(start == 0); - vc4->dirty |= VC4_DIRTY_TEXSTATE; - for (i = 0; i < nr; i++) { if (views[i]) new_nr = i + 1; pipe_sampler_view_reference(&stage_tex->textures[i], views[i]); - stage_tex->dirty_samplers |= (1 << i); } for (; i < stage_tex->num_textures; i++) { pipe_sampler_view_reference(&stage_tex->textures[i], NULL); - stage_tex->dirty_samplers |= (1 << i); } stage_tex->num_textures = new_nr; @@ -682,7 +685,6 @@ vc4_state_init(struct pipe_context *pctx) pctx->set_viewport_states = vc4_set_viewport_states; pctx->set_vertex_buffers = vc4_set_vertex_buffers; - pctx->set_index_buffer = vc4_set_index_buffer; pctx->create_blend_state = vc4_create_blend_state; pctx->bind_blend_state = vc4_blend_state_bind;