X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fvc4%2Fvc4_state.c;h=408a9e0af2a478fb5d7bdaf57087affbcb096c32;hb=e0c6135625e1a2e2dc21a4e1472acb331af043cc;hp=fe3394623086dcad44b1566a5806087b1e4431ef;hpb=330d0607ed60fd3edca192e54b4246310f06652f;p=mesa.git diff --git a/src/gallium/drivers/vc4/vc4_state.c b/src/gallium/drivers/vc4/vc4_state.c index fe339462308..408a9e0af2a 100644 --- a/src/gallium/drivers/vc4/vc4_state.c +++ b/src/gallium/drivers/vc4/vc4_state.c @@ -23,6 +23,7 @@ */ #include "pipe/p_state.h" +#include "util/u_framebuffer.h" #include "util/u_inlines.h" #include "util/u_math.h" #include "util/u_memory.h" @@ -94,6 +95,9 @@ vc4_create_rasterizer_state(struct pipe_context *pctx, const struct pipe_rasterizer_state *cso) { struct vc4_rasterizer_state *so; + struct V3D21_DEPTH_OFFSET depth_offset = { V3D21_DEPTH_OFFSET_header }; + struct V3D21_POINT_SIZE point_size = { V3D21_POINT_SIZE_header }; + struct V3D21_LINE_WIDTH line_width = { V3D21_LINE_WIDTH_header }; so = CALLOC_STRUCT(vc4_rasterizer_state); if (!so) @@ -109,7 +113,9 @@ vc4_create_rasterizer_state(struct pipe_context *pctx, /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835, * BCM21553). */ - so->point_size = MAX2(cso->point_size, .125f); + point_size.point_size = MAX2(cso->point_size, .125f); + + line_width.line_width = cso->line_width; if (cso->front_ccw) so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; @@ -117,13 +123,31 @@ vc4_create_rasterizer_state(struct pipe_context *pctx, if (cso->offset_tri) { so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; - so->offset_units = float_to_187_half(cso->offset_units); - so->offset_factor = float_to_187_half(cso->offset_scale); + depth_offset.depth_offset_units = + float_to_187_half(cso->offset_units); + depth_offset.depth_offset_factor = + float_to_187_half(cso->offset_scale); } if (cso->multisample) so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; + V3D21_DEPTH_OFFSET_pack(NULL, so->packed.depth_offset, &depth_offset); + V3D21_POINT_SIZE_pack(NULL, so->packed.point_size, &point_size); + V3D21_LINE_WIDTH_pack(NULL, so->packed.line_width, &line_width); + + if (cso->tile_raster_order_fixed) { + so->tile_raster_order_flags |= VC4_SUBMIT_CL_FIXED_RCL_ORDER; + if (cso->tile_raster_order_increasing_x) { + so->tile_raster_order_flags |= + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X; + } + if (cso->tile_raster_order_increasing_y) { + so->tile_raster_order_flags |= + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y; + } + } + return so; } @@ -363,8 +387,6 @@ vc4_set_constant_buffer(struct pipe_context *pctx, struct vc4_context *vc4 = vc4_context(pctx); struct vc4_constbuf_stateobj *so = &vc4->constbuf[shader]; - assert(index == 0); - /* Note that the state tracker can unbind constant buffers by * passing NULL here. */ @@ -374,7 +396,10 @@ vc4_set_constant_buffer(struct pipe_context *pctx, return; } - assert(!cb->buffer); + if (index == 1 && so->cb[index].buffer_size != cb->buffer_size) + vc4->dirty |= VC4_DIRTY_UBO_1_SIZE; + + pipe_resource_reference(&so->cb[index].buffer, cb->buffer); so->cb[index].buffer_offset = cb->buffer_offset; so->cb[index].buffer_size = cb->buffer_size; so->cb[index].user_buffer = cb->user_buffer; @@ -390,21 +415,10 @@ vc4_set_framebuffer_state(struct pipe_context *pctx, { struct vc4_context *vc4 = vc4_context(pctx); struct pipe_framebuffer_state *cso = &vc4->framebuffer; - unsigned i; vc4->job = NULL; - for (i = 0; i < framebuffer->nr_cbufs; i++) - pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]); - for (; i < vc4->framebuffer.nr_cbufs; i++) - pipe_surface_reference(&cso->cbufs[i], NULL); - - cso->nr_cbufs = framebuffer->nr_cbufs; - - pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf); - - cso->width = framebuffer->width; - cso->height = framebuffer->height; + util_copy_framebuffer_state(cso, framebuffer); /* Nonzero texture mipmap levels are laid out as if they were in * power-of-two-sized spaces. The renderbuffer config infers its @@ -544,7 +558,10 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, so->base = *cso; - pipe_reference(NULL, &prsc->reference); + so->base.texture = NULL; + pipe_resource_reference(&so->base.texture, prsc); + so->base.reference.count = 1; + so->base.context = pctx; /* There is no hardware level clamping, and the start address of a * texture may be misaligned, so in that case we have to copy to a @@ -555,34 +572,46 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, */ if ((cso->u.tex.first_level && (cso->u.tex.first_level != cso->u.tex.last_level)) || - rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R) { - struct vc4_resource *shadow_parent = vc4_resource(prsc); - struct pipe_resource tmpl = shadow_parent->base.b; - struct vc4_resource *clone; - - tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; - tmpl.width0 = u_minify(tmpl.width0, cso->u.tex.first_level); - tmpl.height0 = u_minify(tmpl.height0, cso->u.tex.first_level); - tmpl.last_level = cso->u.tex.last_level - cso->u.tex.first_level; - + rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R || + rsc->vc4_format == ~0) { + struct vc4_resource *shadow_parent = rsc; + struct pipe_resource tmpl = { + .target = prsc->target, + .format = prsc->format, + .width0 = u_minify(prsc->width0, + cso->u.tex.first_level), + .height0 = u_minify(prsc->height0, + cso->u.tex.first_level), + .bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET, + .last_level = cso->u.tex.last_level - cso->u.tex.first_level, + .nr_samples = prsc->nr_samples, + }; + + /* Create the shadow texture. The rest of the texture + * parameter setup will use the shadow. + */ prsc = vc4_resource_create(pctx->screen, &tmpl); if (!prsc) { free(so); return NULL; } rsc = vc4_resource(prsc); - clone = vc4_resource(prsc); - clone->shadow_parent = &shadow_parent->base.b; + vc4_bo_label(vc4_screen(pctx->screen), rsc->bo, + "tiling shadow %dx%d", + tmpl.width0, tmpl.height0); + /* Flag it as needing update of the contents from the parent. */ - clone->writes = shadow_parent->writes - 1; + rsc->writes = shadow_parent->writes - 1; + assert(rsc->vc4_format != VC4_TEXTURE_TYPE_RGBA32R); - assert(clone->vc4_format != VC4_TEXTURE_TYPE_RGBA32R); - } else if (cso->u.tex.first_level) { - so->force_first_level = true; + so->texture = prsc; + } else { + pipe_resource_reference(&so->texture, prsc); + + if (cso->u.tex.first_level) { + so->force_first_level = true; + } } - so->base.texture = prsc; - so->base.reference.count = 1; - so->base.context = pctx; so->texture_p0 = (VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) | @@ -606,8 +635,10 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc, static void vc4_sampler_view_destroy(struct pipe_context *pctx, - struct pipe_sampler_view *view) + struct pipe_sampler_view *pview) { + struct vc4_sampler_view *view = vc4_sampler_view(pview); + pipe_resource_reference(&pview->texture, NULL); pipe_resource_reference(&view->texture, NULL); free(view); }