X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fwinsys%2Famdgpu%2Fdrm%2Famdgpu_cs.c;h=e2f297450d3e0946fc3bcfe5eb50bd67e68a60e1;hb=6d89a4067627fdf568c6c4e3d9a201fd45d5352b;hp=fb517b9ac54c05262c57c7b26825fb4cbc68aab8;hpb=44bbfedbd9983c61f6a461cbfe2e0dc74eda6d37;p=mesa.git diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index fb517b9ac54..e2f297450d3 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -35,7 +35,7 @@ #include #include -#include "../../../drivers/radeonsi/sid.h" +#include "amd/common/sid.h" /* FENCES */ @@ -137,6 +137,28 @@ static bool amdgpu_fence_wait_rel_timeout(struct radeon_winsys *rws, return amdgpu_fence_wait(fence, timeout, false); } +static struct pipe_fence_handle * +amdgpu_cs_get_next_fence(struct radeon_winsys_cs *rcs) +{ + struct amdgpu_cs *cs = amdgpu_cs(rcs); + struct pipe_fence_handle *fence = NULL; + + if (cs->next_fence) { + amdgpu_fence_reference(&fence, cs->next_fence); + return fence; + } + + fence = amdgpu_fence_create(cs->ctx, + cs->csc->request.ip_type, + cs->csc->request.ip_instance, + cs->csc->request.ring); + if (!fence) + return NULL; + + amdgpu_fence_reference(&cs->next_fence, fence); + return fence; +} + /* CONTEXTS */ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws) @@ -227,9 +249,10 @@ static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs) cs->request.ip_type != AMDGPU_HW_IP_VCE; } -static bool amdgpu_cs_has_chaining(enum ring_type ring_type) +static bool amdgpu_cs_has_chaining(struct amdgpu_cs *cs) { - return ring_type == RING_GFX; + return cs->ctx->ws->info.chip_class >= CIK && + cs->ring_type == RING_GFX; } static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type) @@ -268,63 +291,69 @@ int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo * return -1; } -static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs, - struct amdgpu_winsys_bo *bo, - enum radeon_bo_usage usage, - enum radeon_bo_domain domains, - unsigned priority, - enum radeon_bo_domain *added_domains) +static int +amdgpu_lookup_or_add_buffer(struct amdgpu_cs *acs, struct amdgpu_winsys_bo *bo) { struct amdgpu_cs_context *cs = acs->csc; struct amdgpu_cs_buffer *buffer; - unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1); - int i = -1; - - assert(priority < 64); - *added_domains = 0; - - i = amdgpu_lookup_buffer(cs, bo); + unsigned hash; + int idx = amdgpu_lookup_buffer(cs, bo); - if (i >= 0) { - buffer = &cs->buffers[i]; - buffer->priority_usage |= 1llu << priority; - buffer->usage |= usage; - *added_domains = domains & ~buffer->domains; - buffer->domains |= domains; - cs->flags[i] = MAX2(cs->flags[i], priority / 4); - return i; - } + if (idx >= 0) + return idx; /* New buffer, check if the backing array is large enough. */ if (cs->num_buffers >= cs->max_num_buffers) { - uint32_t size; - cs->max_num_buffers += 10; + unsigned new_max = + MAX2(cs->max_num_buffers + 16, (unsigned)(cs->max_num_buffers * 1.3)); + struct amdgpu_cs_buffer *new_buffers; + amdgpu_bo_handle *new_handles; + uint8_t *new_flags; + + new_buffers = MALLOC(new_max * sizeof(*new_buffers)); + new_handles = MALLOC(new_max * sizeof(*new_handles)); + new_flags = MALLOC(new_max * sizeof(*new_flags)); + + if (!new_buffers || !new_handles || !new_flags) { + fprintf(stderr, "amdgpu_lookup_or_add_buffer: allocation failed\n"); + FREE(new_buffers); + FREE(new_handles); + FREE(new_flags); + return -1; + } - size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer); - cs->buffers = realloc(cs->buffers, size); + memcpy(new_buffers, cs->buffers, cs->num_buffers * sizeof(*new_buffers)); + memcpy(new_handles, cs->handles, cs->num_buffers * sizeof(*new_handles)); + memcpy(new_flags, cs->flags, cs->num_buffers * sizeof(*new_flags)); - size = cs->max_num_buffers * sizeof(amdgpu_bo_handle); - cs->handles = realloc(cs->handles, size); + FREE(cs->buffers); + FREE(cs->handles); + FREE(cs->flags); - cs->flags = realloc(cs->flags, cs->max_num_buffers); + cs->max_num_buffers = new_max; + cs->buffers = new_buffers; + cs->handles = new_handles; + cs->flags = new_flags; } - /* Initialize the new buffer. */ - cs->buffers[cs->num_buffers].bo = NULL; - amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo); - cs->handles[cs->num_buffers] = bo->bo; - cs->flags[cs->num_buffers] = priority / 4; + idx = cs->num_buffers; + buffer = &cs->buffers[idx]; + memset(buffer, 0, sizeof(*buffer)); + amdgpu_winsys_bo_reference(&buffer->bo, bo); + cs->handles[idx] = bo->bo; + cs->flags[idx] = 0; p_atomic_inc(&bo->num_cs_references); - buffer = &cs->buffers[cs->num_buffers]; - buffer->bo = bo; - buffer->priority_usage = 1llu << priority; - buffer->usage = usage; - buffer->domains = domains; + cs->num_buffers++; + + hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1); + cs->buffer_indices_hashlist[hash] = idx; - cs->buffer_indices_hashlist[hash] = cs->num_buffers; + if (bo->initial_domain & RADEON_DOMAIN_VRAM) + acs->main.base.used_vram += bo->base.size; + else if (bo->initial_domain & RADEON_DOMAIN_GTT) + acs->main.base.used_gart += bo->base.size; - *added_domains = domains; - return cs->num_buffers++; + return idx; } static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs, @@ -336,17 +365,19 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs, /* Don't use the "domains" parameter. Amdgpu doesn't support changing * the buffer placement during command submission. */ - struct amdgpu_cs *cs = amdgpu_cs(rcs); + struct amdgpu_cs *acs = amdgpu_cs(rcs); + struct amdgpu_cs_context *cs = acs->csc; struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf; - enum radeon_bo_domain added_domains; - unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain, - priority, &added_domains); + struct amdgpu_cs_buffer *buffer; + int index = amdgpu_lookup_or_add_buffer(acs, bo); - if (added_domains & RADEON_DOMAIN_VRAM) - cs->csc->used_vram += bo->base.size; - else if (added_domains & RADEON_DOMAIN_GTT) - cs->csc->used_gart += bo->base.size; + if (index < 0) + return 0; + buffer = &cs->buffers[index]; + buffer->priority_usage |= 1llu << priority; + buffer->usage |= usage; + cs->flags[index] = MAX2(cs->flags[index], priority / 4); return index; } @@ -362,7 +393,7 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib) * is the largest power of two that fits into the size field of the * INDIRECT_BUFFER packet. */ - if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib)->ring_type)) + if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib))) buffer_size = 4 *util_next_power_of_two(ib->max_ib_size); else buffer_size = 4 *util_next_power_of_two(4 * ib->max_ib_size); @@ -455,7 +486,7 @@ static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs, unreachable("unhandled IB type"); } - if (!amdgpu_cs_has_chaining(cs->ring_type)) { + if (!amdgpu_cs_has_chaining(cs)) { ib_size = MAX2(ib_size, 4 * MIN2(util_next_power_of_two(ib->max_ib_size), amdgpu_ib_max_submit_dwords(ib_type))); @@ -525,26 +556,6 @@ static bool amdgpu_init_cs_context(struct amdgpu_cs_context *cs, break; } - cs->max_num_buffers = 512; - cs->buffers = (struct amdgpu_cs_buffer*) - CALLOC(1, cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer)); - if (!cs->buffers) { - return false; - } - - cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle)); - if (!cs->handles) { - FREE(cs->buffers); - return false; - } - - cs->flags = CALLOC(1, cs->max_num_buffers); - if (!cs->flags) { - FREE(cs->handles); - FREE(cs->buffers); - return false; - } - for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) { cs->buffer_indices_hashlist[i] = -1; } @@ -571,8 +582,6 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs) } cs->num_buffers = 0; - cs->used_gart = 0; - cs->used_vram = 0; amdgpu_fence_reference(&cs->fence, NULL); for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) { @@ -688,16 +697,6 @@ amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs) return &cs->const_preamble_ib.base; } -#define OUT_CS(cs, value) (cs)->current.buf[(cs)->current.cdw++] = (value) - -static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs, - struct pb_buffer *buf) -{ - struct amdgpu_cs *cs = amdgpu_cs(rcs); - - return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf); -} - static bool amdgpu_cs_validate(struct radeon_winsys_cs *rcs) { return true; @@ -721,7 +720,7 @@ static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw) if (rcs->current.max_dw - rcs->current.cdw >= dw) return true; - if (!amdgpu_cs_has_chaining(cs->ring_type)) + if (!amdgpu_cs_has_chaining(cs)) return false; /* Allocate a new chunk */ @@ -751,14 +750,14 @@ static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw) /* Pad with NOPs and add INDIRECT_BUFFER packet */ while ((rcs->current.cdw & 7) != 4) - OUT_CS(rcs, 0xffff1000); /* type3 nop packet */ + radeon_emit(rcs, 0xffff1000); /* type3 nop packet */ - OUT_CS(rcs, PKT3(ib->ib_type == IB_MAIN ? PKT3_INDIRECT_BUFFER_CIK + radeon_emit(rcs, PKT3(ib->ib_type == IB_MAIN ? PKT3_INDIRECT_BUFFER_CIK : PKT3_INDIRECT_BUFFER_CONST, 2, 0)); - OUT_CS(rcs, va); - OUT_CS(rcs, va >> 32); + radeon_emit(rcs, va); + radeon_emit(rcs, va >> 32); new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw]; - OUT_CS(rcs, S_3F2_CHAIN(1) | S_3F2_VALID(1)); + radeon_emit(rcs, S_3F2_CHAIN(1) | S_3F2_VALID(1)); assert((rcs->current.cdw & 7) == 0); assert(rcs->current.cdw <= rcs->current.max_dw); @@ -784,30 +783,6 @@ static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw) return true; } -static bool amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, - uint64_t vram, uint64_t gtt) -{ - struct amdgpu_cs *cs = amdgpu_cs(rcs); - struct amdgpu_winsys *ws = cs->ctx->ws; - - vram += cs->csc->used_vram; - gtt += cs->csc->used_gart; - - /* Anything that goes above the VRAM size should go to GTT. */ - if (vram > ws->info.vram_size) - gtt += vram - ws->info.vram_size; - - /* Now we just need to check if we have enough GTT. */ - return gtt < ws->info.gart_size * 0.7; -} - -static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs) -{ - struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc; - - return cs->used_vram + cs->used_gart; -} - static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs, struct radeon_bo_list_item *list) { @@ -832,44 +807,42 @@ DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false) static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs) { struct amdgpu_cs_context *cs = acs->csc; - int i, j; + int i; cs->request.number_of_dependencies = 0; for (i = 0; i < cs->num_buffers; i++) { - for (j = 0; j < RING_LAST; j++) { - struct amdgpu_cs_fence *dep; - unsigned idx; - - struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j]; - if (!bo_fence) - continue; - - if (bo_fence->ctx == acs->ctx && - bo_fence->fence.ip_type == cs->request.ip_type && - bo_fence->fence.ip_instance == cs->request.ip_instance && - bo_fence->fence.ring == cs->request.ring) - continue; - - if (amdgpu_fence_wait((void *)bo_fence, 0, false)) - continue; - - if (bo_fence->submission_in_progress) - os_wait_until_zero(&bo_fence->submission_in_progress, - PIPE_TIMEOUT_INFINITE); - - idx = cs->request.number_of_dependencies++; - if (idx >= cs->max_dependencies) { - unsigned size; - - cs->max_dependencies = idx + 8; - size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence); - cs->request.dependencies = realloc(cs->request.dependencies, size); - } - - dep = &cs->request.dependencies[idx]; - memcpy(dep, &bo_fence->fence, sizeof(*dep)); + struct amdgpu_cs_fence *dep; + unsigned idx; + + struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence; + if (!bo_fence) + continue; + + if (bo_fence->ctx == acs->ctx && + bo_fence->fence.ip_type == cs->request.ip_type && + bo_fence->fence.ip_instance == cs->request.ip_instance && + bo_fence->fence.ring == cs->request.ring) + continue; + + if (amdgpu_fence_wait((void *)bo_fence, 0, false)) + continue; + + if (bo_fence->submission_in_progress) + os_wait_until_zero(&bo_fence->submission_in_progress, + PIPE_TIMEOUT_INFINITE); + + idx = cs->request.number_of_dependencies++; + if (idx >= cs->max_dependencies) { + unsigned size; + + cs->max_dependencies = idx + 8; + size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence); + cs->request.dependencies = realloc(cs->request.dependencies, size); } + + dep = &cs->request.dependencies[idx]; + memcpy(dep, &bo_fence->fence, sizeof(*dep)); } } @@ -935,7 +908,7 @@ void amdgpu_cs_submit_ib(void *job, int thread_index) fprintf(stderr, "amdgpu: Not enough memory for command submission.\n"); else fprintf(stderr, "amdgpu: The CS has been rejected, " - "see dmesg for more information.\n"); + "see dmesg for more information (%i).\n", r); amdgpu_fence_signalled(cs->fence); } else { @@ -984,26 +957,36 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, switch (cs->ring_type) { case RING_DMA: /* pad DMA ring to 8 DWs */ - while (rcs->current.cdw & 7) - OUT_CS(rcs, 0x00000000); /* NOP packet */ + if (ws->info.chip_class <= SI) { + while (rcs->current.cdw & 7) + radeon_emit(rcs, 0xf0000000); /* NOP packet */ + } else { + while (rcs->current.cdw & 7) + radeon_emit(rcs, 0x00000000); /* NOP packet */ + } break; case RING_GFX: /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */ - while (rcs->current.cdw & 7) - OUT_CS(rcs, 0xffff1000); /* type3 nop packet */ + if (ws->info.gfx_ib_pad_with_type2) { + while (rcs->current.cdw & 7) + radeon_emit(rcs, 0x80000000); /* type2 nop packet */ + } else { + while (rcs->current.cdw & 7) + radeon_emit(rcs, 0xffff1000); /* type3 nop packet */ + } /* Also pad the const IB. */ if (cs->const_ib.ib_mapped) while (!cs->const_ib.base.current.cdw || (cs->const_ib.base.current.cdw & 7)) - OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */ + radeon_emit(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */ if (cs->const_preamble_ib.ib_mapped) while (!cs->const_preamble_ib.base.current.cdw || (cs->const_preamble_ib.base.current.cdw & 7)) - OUT_CS(&cs->const_preamble_ib.base, 0xffff1000); + radeon_emit(&cs->const_preamble_ib.base, 0xffff1000); break; case RING_UVD: while (rcs->current.cdw & 15) - OUT_CS(rcs, 0x80000000); /* type2 nop packet */ + radeon_emit(rcs, 0x80000000); /* type2 nop packet */ break; default: break; @@ -1031,10 +1014,16 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, /* Create a fence. */ amdgpu_fence_reference(&cur->fence, NULL); - cur->fence = amdgpu_fence_create(cs->ctx, - cur->request.ip_type, - cur->request.ip_instance, - cur->request.ring); + if (cs->next_fence) { + /* just move the reference */ + cur->fence = cs->next_fence; + cs->next_fence = NULL; + } else { + cur->fence = amdgpu_fence_create(cs->ctx, + cur->request.ip_type, + cur->request.ip_instance, + cur->request.ring); + } if (fence) amdgpu_fence_reference(fence, cur->fence); @@ -1043,7 +1032,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, amdgpu_add_fence_dependencies(cs); for (i = 0; i < num_buffers; i++) { p_atomic_inc(&cur->buffers[i].bo->num_active_ioctls); - amdgpu_fence_reference(&cur->buffers[i].bo->fence[cs->ring_type], + amdgpu_fence_reference(&cur->buffers[i].bo->fence, cur->fence); } pipe_mutex_unlock(ws->bo_fence_lock); @@ -1073,6 +1062,9 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, if (cs->const_preamble_ib.ib_mapped) amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE); + cs->main.base.used_gart = 0; + cs->main.base.used_vram = 0; + ws->num_cs_flushes++; return error_code; } @@ -1092,6 +1084,7 @@ static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs) FREE(cs->const_preamble_ib.base.prev); amdgpu_destroy_cs_context(&cs->csc1); amdgpu_destroy_cs_context(&cs->csc2); + amdgpu_fence_reference(&cs->next_fence, NULL); FREE(cs); } @@ -1115,13 +1108,11 @@ void amdgpu_cs_init_functions(struct amdgpu_winsys *ws) ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib; ws->base.cs_destroy = amdgpu_cs_destroy; ws->base.cs_add_buffer = amdgpu_cs_add_buffer; - ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer; ws->base.cs_validate = amdgpu_cs_validate; ws->base.cs_check_space = amdgpu_cs_check_space; - ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit; - ws->base.cs_query_memory_usage = amdgpu_cs_query_memory_usage; ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list; ws->base.cs_flush = amdgpu_cs_flush; + ws->base.cs_get_next_fence = amdgpu_cs_get_next_fence; ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced; ws->base.cs_sync_flush = amdgpu_cs_sync_flush; ws->base.fence_wait = amdgpu_fence_wait_rel_timeout;