X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fieee754%2Ffcvt%2Fupsize.py;h=e225a2afb4b7b4642f40a6b56be6c4fba38acf0b;hb=f202152c8467afc84e9377b5e8f224eb8a9784e6;hp=483ddbbc462a883a8ecf21285565a2d8ad1db3af;hpb=5104d9bfc2df4104193a1e9e5930630242f11bf0;p=ieee754fpu.git

diff --git a/src/ieee754/fcvt/upsize.py b/src/ieee754/fcvt/upsize.py
index 483ddbbc..e225a2af 100644
--- a/src/ieee754/fcvt/upsize.py
+++ b/src/ieee754/fcvt/upsize.py
@@ -8,13 +8,13 @@ import functools
 from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTUpConvertMod(FPModBase):
+class FPCVTUpConvertMod(PipeModBase):
     """ FP up-conversion (lower to higher bitwidth)
     """
     def __init__(self, in_pspec, out_pspec):